Datasheet FDP8880, FDB8880 Datasheet (Fairchild)

Page 1
0
May 2008
FDP8880 / FDB8880
FDP8880 / FDB 8880 N-Channel PowerTrench
30V, 54A, 11.6mΩ Features
r
= 14.5mΩ, V
DS(ON)
r
= 11.6mΩ, V
DS(ON)
High pe rformance trench tech nology for e xtremely low r
DS(ON)
Low gat e ch arge
High power and current handling capability
RoHS Complicant
= 4.5V, ID = 40A
GS
= 10V, ID = 40A
GS
MOSFET
General Description
This N- Channe l MOSF ET has been desig ned sp ecif icall y to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM contro llers. It ha s be en optimize d for low gate cha r ge , low r
and fast switching speed.
DS(ON)
Application
DC / DC Converters
tmM
DRAIN
(FLANGE)
GATE
SOURCE
TO-263AB
FDB SERIES
©2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1
(FLANGE)
DRAIN
1
TO-220AB
FDP SERIES
DRAIN
GATE
SOURCE
D
G
S
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Page 2
FDP8880 / FDB8880
MOSFET Maximum Ratings T
= 25°C unless otherwise noted
C
Symbol Parameter Ratings Units
V
DSS
V
GS
Drain to Sou r c e Voltage 30 V Gate to Source Voltage ±20 V Drain Cur re nt Continuous (T
I
D
Continuous (T Continuous (T
= 25oC, VGS = 10V)
C
= 25oC, VGS = 4.5V) 48 A
C
= 25oC, VGS = 10V, with R
amb
= 43oC/W) 11 A
θJA
54 A
Pulsed Figure 4 A
E
AS
P
D
T
, T
J
STG
Single Pulse Avalanche Energy (Note 1) 31 mJ Power dissipation 55 W Derate above 25
o
C0.37W/
Operating and Storage Temperature -55 to 175
Thermal Characteristics
R
θJC
R
θJA
R
θJA
Thermal Resistance Junction to Case TO-220,TO-263 2.73 Thermal Resistance Junction to Am bient TO-220,TO-262 ( Note 2) 62 Thermal Resistance Junction to Am bient TO-263, 1in2 copper pad ar ea 43
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDP8880 FDP8880 TO-220AB Tube N/A 50 units FDB8880 FDB8880 TO-263AB 330mm 24mm 800 units F F
o
C/W
o
C/W
o
C/W
o
C
o
C
Electrical Characteristics
TC = 25°C unless otherwise noted
Symbol Parameter Test Condit ions Min Typ Max Units
Off Characteristics
B I
DSS
I
GSS
VDSS
Drain to Sou r c e Br ea k down Voltage ID = 250µA, VGS = 0V 30 - - V
V
= 24V - - 1
Zero Gate Voltage Drain Current
DS
= 0V TC = 150oC- -250
V
GS
Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
V
GS(TH)
r
DS(ON)
Gate to Source Threshold Vo ltage VGS = VDS, ID = 250µA 1.2 - 2.5 V
I
= 40A, VGS = 10V - 0.0095 0.011 6
D
= 40A, VGS = 4.5V - 0.012 0.0145
I
Drain to S ou r c e On Re si st ance
D
I
= 40A, VGS = 10V,
D
T
= 175oC
J
- 0.015 0.019
µA
Ω
©2008 Fairchild Semiconductor Corporation
DP8880 / FDB8880 Rev. A
F
1
2
www.fairchildsemicom
Page 3
Dynamic Characteristics
C C C R Q Q Q Q Q Q
ISS OSS RSS G
g(TOT) g(5) g(TH) gs gs2 gd
Input Capacitance Output Capacit ance - 255 - pF Reverse Transfer Capacitance - 147 - pF Gate Resistance VGS = 0.5V, f = 1MHz - 2.7 - Ω Total Gate Charge at 10V VGS = 0V to 10V Total Gate Charge at 5V VGS = 0V to 5V - 12 16 nC Threshold Gate Charge VGS = 0V to 1V - 1.6 2.1 nC Gate to Source Gate Charg e - 3.2 - nC Gate Charge Threshold to Plateau - 2.0 - nC Gate to Drain “Miller” Charge - 4.8 - nC
= 15V, VGS = 0V,
V
DS
f = 1MHz
V
DD
I
= 40A
D
= 1.0m A
I
g
FDP8880 / FDB8880
- 1240 - pF
-2229nC
= 15V
Switching Characteristics
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Turn-On Time Turn-On Delay Time - 8 - ns Rise Time - 107 - ns Turn-Off Delay Time - 47 - ns Fall Time - 51 - ns Turn-Off Time - - 147 ns
(VGS = 10V)
Drain-Source Diode Characteristics
V
SD
t
rr
Q
RR
Notes: 1: Starting TJ = 25°C, L = 34uH, IAS = 43A,Vdd = 27V, Vgs = 10V. 2: Pulse width = 100s. 3
Source to Drain Diode Voltage Reverse Recovery Time ISD = 40A, dISD/dt = 100A/µs- -27ns
Reverse Recovered Charge ISD = 40A, dISD/dt = 100A/µs- -18nC
--171ns
= 15V, ID = 40A
V
DD
= 10V, RGS = 13.6Ω
V
GS
I
= 40A - - 1.25 V
SD
I
= 3.5A - - 1.0 V
SD
©2008 Fairchild Semiconductor Corporation
DP8880 / FDB8880 Rev. A
F
1
3
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Page 4
FDP8880 / FDB8880
Typical Characteristics T
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0255075100 175
TC, CASE TEMPERATURE (oC)
= 25°C unless otherwise noted
C
150
125
Figure 1. Normalized Power Dissipation vs Case
Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
θJC
Z
THERMAL IMPEDANCE
0.01
-5
10
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
60
40
20
, DRAIN CURRENT (A)
D
I
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
Figure 2. Maximum Continuous Drain Curr ent vs
Case Temperature
P
DM
t
1
t
x R
2
2
+ T
θJC
C
1
10
NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z
-2
10
-1
10
θJC
10
0
Figure 3. Normalized Maximum Transient Thermal Impedance
600
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
VGS = 4.5V
, PEAK CURRENT (A)
100
DM
I
50
-5
10
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
-4
10
1
VGS = 10V
-3
10
-2
10
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
4
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
I = I
-1
10
175 - T
25
150
0
10
C
1
10
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Page 5
FDP8880 / FDB8880
Typical Characteristics T
400
100
10
OPERATION IN THIS
AREA MAY BE
, DRAIN CURRENT (A)
D
I
LIMITED BY r
1
SINGLE PULSE TJ = MAX RATED
TC = 25oC
0.1 11040
Figure 5. Forward Bias Safe Operating Area
80
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
V
= 15V
DD
60
40
, DRAIN CURRENT (A)
D
I
20
TJ = 25oC
DS(ON)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TJ = 175oC
= 25°C unless otherwise noted
C
10µs
100µs
1ms
10ms
DC
TJ = -55oC
500
100
10
, AVALANCHE CURRENT (A)
AS
I
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
160
120
80
, DRAIN CURRENT (A)
D
I
40
If R = 0 tAV = (L)(IAS)/(1.3*RATED BV
If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV
STARTING TJ = 150oC
1
0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)
DSS
- VDD)
Capability
VGS = 4.5V
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
- VDD) +1]
DSS
ST ARTING TJ = 25oC
10
VGS = 3.5V
VGS = 3V
TC = 25oC
100
0
1.5 2.0 2.5 3.0 3.5 VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Charact eristics Figure 8. Saturation Characteristics
20
ID = 54A
16
, DRAIN TO SOURCE
12
ON RESISTANCE (mΩ)
DS(ON)
r
ID = 5A
8
246810
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
Figure 9. Drain to So urce On Resistance vs Gate
Voltage and Drain Current
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
1
4.0
VGS = 2.5V
0
0 0.25 0.5 0.75 1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.7
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
1.53
1.36
1.19
ON RESISTANCE
1.02
0.85
NORMALIZED DRAIN TO SOURCE
0.7
-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
VGS = 10V, ID = 54A
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
5
www.fairchildsemicom
Page 6
FDP8880 / FDB8880
Typical Characteristics T
1.5
1.2
0.9
NORMALIZED GATE
THRESHOLD VOLTAGE
0.6
0.3
-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
= 25°C unless otherwise noted
C
VGS = VDS, ID = 250µA
Figure 11. Normalized G ate Threshol d Voltage vs
Junction Temperature
2000
C
= CGS + C
1000
ISS
C
OSS
≅ C
GD
+ C
DS
GD
1.1 ID = 250µA
1.0
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0.9
-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
VDD = 15V
8
6
C
= C
RSS
GD
C, CAPACITANCE (pF)
V
= 0V, f = 1MHz
GS
100
0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Sour ce
Voltage
4
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
30
0 5 10 15 20 25
Qg, GATE CHARGE (nC)
WAVEFORMS IN DESCENDING ORDER:
ID = 54A ID = 5A
Figure 14. Gat e Charge Waveforms for Constant
Gate Current
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
1
6
www.fairchildsemicom
Page 7
Test Circuits and Waveforms
V
DS
L
VARY tP TO OBTAIN REQUIRED PEAK I
V
GS
R
AS
G
+
V
DD
-
I
AS
DUT
t
0V
P
I
AS
0.01Ω
0
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
V
DS
V
DD
L
V
I
g(REF)
GS
DUT
+
V
DD
-
V
GS
0
I
g(REF)
= 1V
Q
gs2
Q
g(TH)
Q
gs
Q
0
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
BV
DSS
t
P
t
AV
Q
g(TOT)
V
DS
Q
g(5)
V
V
GS
VGS = 5V
gd
FDP8880 / FDB8880
DS
V
DD
V
= 10V
GS
V
GS
R
GS
V
GS
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
1
V
DS
R
L
+
V
DD
-
V
DS
0
DUT
V
GS
10%
0
7
t
d(ON)
90%
t
ON
t
r
t
d(OFF)
t
OFF
t
f
90%
10%
10%
90%
PULSE WIDTH
50%50%
www.fairchildsemicom
Page 8
PSPICE Electrical Model
.SUBCKT FDP8880 2 1 3 ; rev October 2004 Ca 12 8 9.5e-10 Cb 15 14 9.5e-10 Cin 6 8 1.15e-9
Dbod y 7 5 Dbody M OD Dbreak 5 11 D breakMOD Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 32.88 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1
It 8 17 1 Lgat e 1 9 5.3e-9
Ldrain 2 5 1.0e -9 Lsou rce 3 7 1.7e-9
RLgate 1 9 53 RLdr ai n 2 5 10 RLsource 3 7 17
Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.0e-3 Rgate 9 20 2.2 RSLC1 5 51 RSL CM OD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 6.8e-3 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD
Vbat 22 19 DC 1
GATE
1
LGATE
RLGATE
RGATE
9
CA
-
ESG
+
EVTEMP +
-
18 22
20
S1A
12
13814
S1B
EGS EDS
13
6 8
10
RSLC2
6
13
+
+
6 8
-
-
DPLCAP
EVTHRES
+
19
8
S2A
S2B
15
CIN
CB
-
+
-
5
51
5
51
21
MSTRO
14
5 8
RSLC1
+
ESLC
­50
RDRAIN
16
8
MMED
DBREAK
EBREAK
MWEAK
RSOURCE
RBREAK
17 18
IT
8
RVTHRES
FDP8880 / FDB8880
LDRAIN
RLDRAIN
11
+
17
DBODY
18
-
LSOURCE
7
RLSOURCE
RVTEMP 19
­VBAT
+
22
DRAIN
2
SOURCE
3
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))* (P WR(V(5,51)/(1e-6*170),5))} .MODEL DbodyMOD D (IS=3E-12 IKF=10 N=1.01 RS=5e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=4.8e-10 M=0.55 TT=1e -11 XTI=2) .MODEL DbreakMOD D (RS= 0.2 TRS1=1e-3 TRS2=-8.8e-6) .MODEL DplcapMOD D (CJO=5.5e-10 IS=1e-30 N=10 M=0.45)
.MODEL Mstro M OD NMOS (VTO=2.10 K P =170 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedM OD NMOS (VTO=1.75 KP=10 IS=1 e-30 N=10 TOX=1 L=1u W=1u RG=2.2) .MODEL Mwe akMOD NMOS (VTO =1.39 KP=0. 05 IS=1e-30 N= 10 TO X = 1 L=1u W=1u RG=22 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.0e-4 TC2=-8e-7) .MODEL Rd rai nMOD RES (TC1=-12e-3 TC2=.35e-4) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .MODEL RvtempMOD RES (TC1=-2.78 e-3 TC2=1.5e-6) .MODEL RvthresMOD RES (TC1=-1e -3 T C2=-8.2e-6)
MODEL S1AMOD VSWITCH (RON=1e- 5 ROFF =0. 1 VON=- 4 VOF F=-3 .5 ) .MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 3. 5 VOFF =-4 ) .MODEL S2AMOD VSWITC H (RON =1e- 5 ROF F= 0. 1 VON=- 1. 3 VOFF =-0 .8 ) .MODEL S2BMOD VSWITC H (RON =1e- 5 ROF F= 0. 1 VON=- 0. 8 VOFF =-1 .3 ) .ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Rec o rds, 1991, writ ten by William J. Hepp and C. Frank Wheatley.
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
1
8
www.fairchildsemicom
Page 9
SABER Electrical Model
rev October 2004 template FDP8880 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=3e-12,ikf=10,nl=1.01,rs=5e-3,trs1=8e-4,trs2=2e-7,cjo=4.8e-10,m=0.55,tt=1e-11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3 ,t rs 2=-8.8e-6) dp..model dplcapmod = (cjo=5.5e-10,isl=10e-30,nl=10,m=0.45) m..model mstrongmod = (type=_n,vto=2.10,kp=170,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.75,kp=10,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.39,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1,von=-3.5, vof f =-4) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-1.3, vof f =-0.8) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=-0.8, vof f =-1.3) c.ca n12 n8 = 9. 5e-10 c.cb n15 n14 = 9.5e-10 c.cin n6 n8 = 1.15 e-9
dp.dbody n7 n5 = model=dbodym od dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 32.88 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1
GATE
1
LGATE
9
RLGATE
RGATE
ESG
EVTEMP +
18 22
20
spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1
CA
S1A
12
S1B
l.lgate n1 n9 = 5.3e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.7e-9
res.rlgate n1 n9 = 53 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 17
m.mmed n16 n6 n8 n8 = m odel=mmedm od, l= 1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u
DPLCAP
10
RSLC2
­6
8
EVTHRES
+
+
19
8
6
-
S2A
13814
13
S2B
13
+
+
6
EGS EDS
8
-
-
5
RSLC1
51
ISCL
8
MMED
8
DBREAK
11
MWEAK
EBREAK
+
RSOURCE
RBREAK
17 18
IT
RVTHRES
17 18
­7
50 RDRAIN
16
21
-
MSTRO
CIN
15
CB
14
+
5 8
-
LDRAIN
RLDRAIN
DBODY
LSOURCE
RLSOURCE
RVTEMP 19
­VBAT
+
22
DRAIN
2
SOURCE
3
FDP8880 / FDB8880
res.rbreak n17 n18 = 1, tc1=8.0e- 4, tc 2=-8e-7 res.rdrain n50 n16 = 1.0e-3, tc 1=-12e-3,tc2= .35e-4 res.rgate n9 n20 = 2. 2 res.rslc1 n5 n51 = 1e-6, tc1=9e -4, tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsour ce n8 n7 = 6.8e-3, tc1= 5e-3,tc2=1e- 6 res.rvthres n22 n8 = 1, tc1=-1e- 3,tc2=-8.2e -6 res. r v temp n18 n19 = 1, tc 1=-2. 78e- 3,tc2= 1.5e- 6 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model = s1 bmod sw_vcsp.s2 a n6 n15 n14 n13 = model = s2 amod sw_vcsp.s2 b n13 n15 n14 n13 = model = s 2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n 51))))*((abs (v(n5,n51)* 1e6/170))** 5))} }
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
1
9
www.fairchildsemicom
Page 10
FDP8880 / FDB8880
PSPICE Thermal Model
REV 23 December 2003 FDP8880T CTHERM1 TH 6 8e-4
CTHERM2 6 5 1e-3 CTHERM3 5 4 2. 5e-3 CTHERM4 4 3 2. 6e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 1.5e-2
RTHERM1 TH 6 1.44e-1 RTHERM2 6 5 1. 9e-1 RTHERM3 5 4 3. 0e-1 RTHERM4 4 3 4. 0e-1 RTHERM5 3 2 5. 7e-1 RTHERM6 2 TL 5.8e-1
SABER Thermal Model
SABER therm al m odel F DP8880T template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =8e-4 ctherm.ctherm2 6 5 =1e-3 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =2.6e-3 ctherm.ctherm5 3 2 =8e-3 ctherm.ctherm6 2 tl =1.5e-2
rtherm.rth erm 1 th 6 =1.44e-1 rtherm.rtherm2 6 5 =1.9e-1 rtherm.rtherm3 5 4 =3.0e-1 rtherm.rtherm4 4 3 =4.0e-1 rtherm.rtherm5 3 2 =5.7e-1 rtherm.rtherm6 2 tl =5.8 e-1 }
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
JUNCTION
th
CTHERM1
6
CTHERM2
5
CTHERM3
4
CTHERM4
3
CTHERM5
RTHERM6
2
CTHERM6
tl
CASE
©2008 Fairchild Semiconductor Corporation F
DP8880 / FDB8880 Rev. A
1
10
www.fairchildsemicom
Page 11
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®
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are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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TinyBoost™ TinyBuck™ TinyLogic
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
in the labeling, can be reasonably expected to result in a significant injury of the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data; supplementary data will be pub-
Preliminary First Production
lished at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production
Obsolete Not In Production
@2008 Fairchild Semiconductor Corporation WWW. fairchildsemicom
FDP8880 / FDB8880 Rev.A1
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I34
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