Datasheet fdb3672_f085 Datasheet

FDB3672_F085

N-Channel PowerTrench® MOSFET

FDB3672_F085

January 2009

100V, 44A, 28m Ω

Features

•r

•Qg(tot) = 24nC (Typ.), V

• Low Miller Charge

•Low QRR Body Diode

• Optimized efficiency at high frequencies

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

• RoHS Compliant

Formerly developmental type 82760

MOSFET Maximum Ratings

V
V

I

D

E
P
TJ, T

= 24mΩ (Typ.), V

DS(ON)

GATE

SOURCE

TO-263AB

FDB SERIES

Symbol Parameter Ratings Units

DSS
GS

AS

D

STG

Drain to Source Voltage 100 V
Gate to Source Voltage ±20 V
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 10V) 31 A
Continuous (T
Pulsed Figure 4 A
Single Pulse Avalanche Energy (Note 1) 120 mJ
Power dissipation 120 W
Derate above 25oC0.8W/
Operating and Storage Temperature -55 to 175

= 10V, ID = 44A

GS

= 10V

GS

DRAIN

(FLANGE)

= 25oC, VGS = 10V, R

amb

TC = 25°C unless otherwise noted

= 43oC/W) 7.2 A

θJA

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Rectifier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Load Control

• Electronic Valve Train Systems

D

G

S

44 A

N-Channel PowerTrench

®

MOSFET

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product ha s bee n desi gned to meet the ex trem e tes t cond iti ons an d envi ronm ent de mand ed by th e auto mo tive in dust ry. For a

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

Thermal Resistance Junction to Case TO-263 1.25
Thermal Resistance Junction to Ambient TO-263 (Note 2) 62
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

certification.

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB3672

FDB3672_F085

TO-263AB 330mm 24mm 800 units

FDB3672_F085

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 100 - - V

V

= 80V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC= 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

I

Drain to Source On Resistance

= 44A, V

D

= 21A, VGS = 6V, - 0.031 0.047

D

I

=44A, VGS=10V, TC=175oC - 0.054 0. 068

D

= 10V - 0.024 0.028

GS

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 247 - pF
Reverse Transfer Capacitance - 62 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 3.5 4.5 nC
Gate to Source Gate Charge - 11 - nC
Gate Charge Threshold to Plateau - 7.2 - nC

V

DD

I

= 44A

D

= 1.0mA

I

g

= 50V

Gate to Drain “M iller” Charge - 4.5 - nC

- 1710 - pF

-2431nC

µA

N-Channel PowerTrench

ΩI

®

MOSFET

Resistive Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 11 - ns
Rise Time - 59 - ns
Turn-Off Delay Time - 26 - ns
Fall Time - 44 - ns
Turn-Off Time - - 104 ns

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes:
1: Starting T
2: Pulse Width = 100s

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 44A, dISD/dt =100A/µs- - 52ns

Reverse Recovered Charge ISD = 44A, dISD/dt =100A/µs- - 80nC

= 25°C, L = 0.6mH, IAS = 20A.

J

(VGS = 10V)

V

DD

V

GS

I

SD

I

SD

- - 104 ns

= 50V, ID = 44A
= 10V, RGS = 11.0Ω

= 44A - - 1.25 V

= 21A - - 1.0 V

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

FDB3672_F085

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

= 25°C unless otherwise noted

C

125

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

150

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

V

= 10V

GS

Figure 2. Maximum Contin uous Drain Current vs

Case Temperature

N-Channel PowerTrench

®

MOSFET

P

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

SINGLE PULSE

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

DM

t

1

t

2

1/t2

x R

+ T

θJC

θJC

C

0

10

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

500

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

30

-5

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

10

-3

10

t, PULSE WIDT H (s)

-2

10

-1

10

TC = 25oC

FOR TEMPERATURES

o

ABOVE 25
CURRENT AS FOLLOWS:

I = I

25

10

C DERATE PEAK

175 - T

150

0

C

1

10

Figure 4. Peak Current Capability

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

Typical Characteristics T

= 25°C unless otherwise noted

C

FDB3672_F085

200
100

10

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

1

, DRAIN CURRENT (A)

D

I

SINGLE PULSE
TJ = MAX RATED

T

= 25oC

C

0.1
110100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

10µs

100µs

1ms

10ms

DC

200

Figure 5. Forward Bias Safe Oper atin g Area

80

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

60

40

TJ = 25oC

20

, DRAIN CURRENT (A)

D

I

0

3.5 4.0 4.5 5.0 5.5 6.0 6.5
VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

300

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

0.001 0.01 0.1 1
tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Applica tion N ote s AN7514 and AN7515

Figure 6. Unclamped Inductive Switch ing

Capability

80

TC = 25oC

60

40

, DRAIN CURRENT (A)

20

D

I

0

0 0.5 1.0 1.5 2.0 2.5 3.0

VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 7V

VGS = 6V

N-Channel PowerTrench

10

®

MOSFET

Figure 7. Transfer Characterist ics Figure 8. Saturation Characteristics

40

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

35

30

25

20

15

DRAIN TO SOURCE ON RESISTANCE (m Ω)

0 1020304050

VGS = 6V

VGS = 10V

I

, DRAIN CURRENT (A)

D

Figure 9. Drain to Sour ce On Resistan ce vs Drain

Current

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 44A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

Typical Characteristics T

= 25°C unless otherwise noted

C

FDB3672_F085

1.2
VGS = VDS, ID = 250µA

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

Figure 11. Normalized Gate Thresho ld Voltage vs

Junction Temperature

3000

C

= CGS + C

1000

100

ISS

C

≅ C

+ C

OSS

DS

GD

C

= C

RSS

GD

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 50V

8

6

4

N-Channel PowerTrench

®

MOSFET

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Source

Voltage

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 44A

= 22A

I

D

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

Test Circuits and Waveforms

FDB3672_F085

BV

DSS

t

P

t

AV

V

DS

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

V

DS

L

0.01Ω

+

V

DD

-

0

R

AS

G

DUT

I

AS

I

AS

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

DUT

+

V

DD

-

V

DD

V

GS

V

= 2V

GS

Q

0

Q

g(TH)

I

g(REF)

0

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

DD

N-Channel PowerTrench

®

V

= 10V

GS

MOSFET

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serves as the basis for establishing the rating of the part.

P

DM

TJMTA–()

------------------- ----------=

R

θJA

(EQ. 1)

In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

DM

is

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

80

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

0.1

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

110

Pad Area

FDB3672_F085

N-Channel PowerTrench

®

MOSFET

Thermal resistances corresponding to other copper area s
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

R

R

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

θJA

θJA

26.51

26.51

19.84

-------------------------------------+=

0.262 Area+()

Area in Inches Squared

128

----------------------------------+=

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDB3672 2 1 3 ; rev May 2004
CA 12 8 5.8e-10
Cb 15 14 6.8e-10
Cin 6 8 1.6e-9

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 105
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgate 1 9 9.56e-9

Ldrain 2 5 1.0e-9
Lsource 3 7 4.45 e -9

RLgate 1 9 95.6
RLdrain 2 5 10
RLsource 3 7 44.5

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 6.0e-3
Rgate 9 20 1.5
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 9.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

18
22

20

S1A

12

13

8

S1B

EGS EDS

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

6

-

S2A

14
13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

51

­50

RDRAIN

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

ESLC

16

8

MMED

8

DBREAK

11

+

17

EBREAK

18

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB3672_F085

N-Channel PowerTrench

®

MOSFET

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))}
.MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6

+ CJO=1.2e-9 M=0.58 TT=3.75e-8 XTI=4.0)
.MODEL DbreakMOD D (RS=15 TRS1=4.0e-3 TRS2=-5.0e-6)
.MODEL DplcapMOD D (CJO=3 .8e-10 IS=1.0e-30 N=10 M=0.60)

.MODEL MmedMOD NM OS (VTO =3 .6 KP= 3 IS =1 e- 4 0 N=1 0 TOX=1 L=1u W=1u RG=1.5)
.MODEL MstroMOD NMOS (VT O=4.3 KP=59 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.09 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1)

.MODEL RbreakMOD RES (TC1=9.0e-4 TC2=-1.0e-7)
.MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-3.5e-3 TC2=-1.5e-5)
.MODEL RvtempMOD RES (TC1=- 4.3e-3 TC2=1.5e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)

.ENDS
Note: For further disc ussio n of the PSPI CE model, c onsult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

SABER Electrical Model

REV May 2004
template FDB3672 n2,n1,n3
electrical n2,n1, n3
{
var i iscl
dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0)
dp..model dbreakmod = (rs=15,trs1=4.0e-3,trs2=-5.0e-6)
dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60)
m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1)
m..model mstrong mod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0)

DPLCAP

10

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5)
c.ca n12 n8 = 5.8e-10

RSLC2

c.cb n15 n14 = 6.8e-10
c.cin n6 n8 = 1.6e-9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 105

GATE

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1

LGATE

1

RLGATE

RGATE

9

ESG

EVTEMP
+

18
22

20

-

6
8

EVTHRES

+

+

-

19

8

6

-

CIN

spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 95.6e-9

l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.45e-9

res.rlgate n1 n9 = 9.56
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 44.5

CA

S1A

12

S1B

S2A

14

13

13

8

S2B

13

+

+

6

EGS EDS

8

-

-

15

CB

+

5
8

-

m.mmed n16 n6 n8 n8 = model=mmedm od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model= mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e-7
res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5
res.rgate n9 n20 = 1.5
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=1.0e-6
res.rslc2 n5 n50 = 1. 0e3
res.rsource n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6
res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5
res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3))
}

5

RSLC1

51

50

RDRAIN

21

MSTRO

14

ISCL

16

8

MMED

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

-

17
18

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB3672_F085

N-Channel PowerTrench

®

MOSFET

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

SPICE Thermal Model

REV May 2004
FDB3672
CTHERM1 TH 6 3.2e-3

CTHERM2 6 5 3.3e-3
CTHERM3 5 4 3.4e-3
CTHERM4 4 3 3.5e-3
CTHERM5 3 2 6.4e-3
CTHERM6 2 TL 1.9e-2

RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.4e-1
RTHERM6 2 TL 3.5e-1

SABER Thermal Model

SABER thermal model FDB3672
template thermal_model th tl
thermal_c th, tl
{
cctherm.ctherm1 th 6 =3.2e-3
ctherm.ctherm2 6 5 =3.3e-3
ctherm.ctherm3 5 4 =3.4e-3
ctherm.ctherm4 4 3 =3.5e-3
ctherm.ctherm5 3 2 =6.4e-3
ctherm.ctherm6 2 t l =1.9e-2

th

RTHERM1

6

RTHERM2

5

RTHERM3

4

RTHERM4

JUNCTION

CTHERM1

CTHERM2

CTHERM3

CTHERM4

FDB3672_F085

N-Channel PowerTrench

®

MOSFET

rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =5.0e-3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =10.5e-2
rtherm.rtherm5 3 2 =3.4e-1
rtherm.rtherm6 2 tl =3.5e-1
}

RTHERM5

RTHERM6

3

CTHERM5

2

CTHERM6

tl

CASE

©2009 Fairchild Semiconductor Corporation FDB3672_F085 Rev. A

tm

®

tm

tm

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N-Channel PowerTrench

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PRODUCT STATUS DEFINITIONS
Definition of Terms

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Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

©2009 Fairchild Semiconductor Corporation

Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.

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Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.

FDB3672_F085 Rev. A

Rev. I37