Datasheet fdb3652_f085 Datasheet

FDB3652_F085

®

N-Channel PowerTrench
100V, 61A, 16mΩ

Features

•r

•Qg(tot) = 41nC (Typ.), V

• Low Miller Charge

•Low QRR Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

• RoHS Compliant

Formerly developmental type 82769

= 14mΩ (Typ.), V

DS(ON)

= 10V, ID = 61A

GS

= 10V

GS

MOSFET

Applications

• DC/DC C onverters an d Of f- li ne UPS

• Distributed Power Archi tectures and VRMs

• Primary Sw itc h for 24V and 4 8V Syste ms

• High Voltage Synchronous Re ctifier

• Direct Injection / Diesel Injection Systems

• 42V Automot ive Lo ad Control

• Electronic Valve Train Systems

FD
B3652_F085 N-Channel PowerTrench

October 2008

DRAIN

(FLANGE)

GATE

SOURCE

TO-263AB

FDB SERIES

TC = 25°C unless ot herwise noted

MOSFET Maximum Ratings

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

E

AS

P

D

TJ, T

Drain to Source Voltage 100 V
Gate to Source Voltage ±20 V
Drain Cur re nt
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 10V) 43 A
Continuous (T
Pulsed Figure 4 A
Single Pulse Aval anche Energy (Note 1) 182 mJ
Power dissipation 150 W
Derate above 25oC1.0W/
Operating an d Stora ge Temper ature -55 to 175

STG

= 25oC, VGS = 10V) with R

amb

= 43oC/W) 9 A

θJA

D

G

S

61 A

®

MOSFET

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and environme nt demande d by the automot ive indus t ry. For a

All Fairchild Semiconductor pr oducts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

©2008 Fairchild Semiconductor Corporation FDB3652_F085 Rev. A1

Thermal Resistance Junction to Case TO-263 1.0
Thermal Resistance Junction to Ambient TO-263 (Note 2) 62
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

1

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB3652 FDB3652_F085 TO-263AB 330mm 24mm 800 units

FDB3652_F085 N-Channel PowerTrench

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltage ID = 250µA, VGS = 0V 100 - - V
Zero Gate Voltage Drain Current

VDS = 80V - - 1

= 0V TC= 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

= 61A, VGS = 10V - 0.014 0.016

I

D

Drain to S ou r c e On Re si st ance

ID = 30A, VGS = 6V - 0.018 0.026
ID = 61A, VGS = 10V,

TJ = 175oC

- 0.035 0.043

Dynamic Characteristics

C

ISS

C

OSS

C

RSS

Q

g(TOT)

Q

g(TH)

Q

gs

Q

gs2

Q

gd

Input Capacitance
Output Capacitance - 390 - pF
Reverse Transfer Capacitance - 100 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 5 6.5 nC
Gate to Source Gate Charg e - 15 - nC
Gate Charge Threshold to Plateau - 10 - nC

VDD = 50V

= 61A

I

D

I

= 1.0m A

g

Gate to Drain “Miller” Charge - 10 - nC

- 2880 - pF

41 53 nC

µA

Ω

®

MOSFET

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 12 - ns
Rise Time - 85 - ns
Turn-Off Delay Time - 26 - ns
Fall Time - 45 - ns
Turn-Off Time - - 107 ns

(VGS = 10V)

--146ns

VDD = 50V, ID = 61A
VGS = 10V, RGS = 6.8Ω

Drain-Source Diode Characteristics

I

= 61A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 0.228mH, IAS = 40A.
2: Pulse Width = 100s

©2008 Fairchild Semiconductor Corporation FDB3652 _F085 Rev. A1

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 61A, dISD/dt = 100A/µs- -62ns

Reverse Recovered Charge ISD = 61A, dISD/dt = 100A/µs- -45nC

SD

ISD = 30A - - 1.0 V

2

FDB3652_F085 N-Channel PowerTrench

Typical Characteristics

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

TC, CASE TEMPERATURE (oC)

TC = 25°C unless otherwise noted

125

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

10

75

50

25

, DRAIN CURRENT (A)

D

I

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

-1

10

θJC

10

0

x R

®

MOSFET

t

1

t

2

2

+ T

θJC

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

, PEAK CURRENT (A)

DM

I

100

50

-5

10

-4

10

-3

10

-2

10

t, PULSE WIDTH (s)

-1

10

TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev. A1

3

Typical Characteristics

TC = 25°C unless otherwise noted

FDB3652_F085 N-Channel PowerTrench

1000

10µs

100

100µs

10

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

, DRAIN CURRENT (A)

D

I

1

SINGLE PULSE

TJ = MAX RATED
TC = 25oC

0.1
110100200

DS(ON)

1ms

10ms

DC

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 5. Forward Bias Safe Operating Area

125

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 15V

DD

100

75

TJ = 175oC

50

, DRAIN CURRENT (A)

D

I

TJ = 25oC

25

0

34567

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

500

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ¼ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV

100

10

, AVALANCHE CURRENT (A)

AS

STARTING TJ = 150oC

I

1

0.01
tAV, TIME IN AVALANCHE (ms)

0.1 1 10

- VDD)

DSS

DSS

STARTING TJ = 25oC

- VDD) +1]

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

125

VGS = 7VVGS = 10V

100

75

50

, DRAIN CURRENT (A)

D

I

25

VGS = 5V

0

01234

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 6V

TC = 25oC

®

MOSFET

Figure 7. Transfer Charact eristics Figure 8. Saturation Characteristics

20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

18

16

14

DRAIN TO SOURCE ON RESISTANCE(mΩ)

12

0 204060

VGS = 6V

VGS = 10V

ID, DRAIN CURRENT (A)

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev.

3.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 61A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

4

A1

Typical Characteristics

TC = 25°C unless otherwise noted

FDB3652_F085 N-Channel PowerTrench

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperature

5000

C

= CGS + C

ISS

C

≅ C

+ C

OSS

DS

1000

C

C, CAPACITANCE (pF)

100

V

GS

40

0.1 1 10 100

GD

= C

RSS

GD

= 0V, f = 1MHz

VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 50V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 1020304050

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 61A
ID = 30A

®

MOSFET

Figure 13. Capacitance vs Drain to Sour ce

Voltage

©2008 Fairchild Semiconductor Corporation FDB3652_F085 Rev. A1

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

5

Test Circuits and Waveforms

V

DS

L

I

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

t

0V

P

0.01Ω

+

V

DD

-

0

R

AS

G

DUT

I

AS

AS

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

BV

DSS

t

P

t

AV

FDB3652_F085 N-Channel PowerTrench

V

DS

V

DD

V

DS

I

g(REF)

V

DD

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

0

= 2V

Q

gs2

Q

g(TH)

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

10%

PULSE WIDTH

®

MOSFET

GS

t

d(OFF)

90%

V

= 10V

GS

t

OFF

t

f

90%

10%

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev. A1

6

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum al lowab le de vice p ower di ssip atio n, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and th ermal res istance R
must be reviewed to ensure that TJM is never exceeded.

θJA

(oC/W)

Equation 1 mathematically represents the relationship and
serve s as the basis for est ablishing the rating of the part.

=

P

DM

TJMTA–()

----------------- ------------

R

θJA

(EQ. 1)

In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power d issipati on rating s. Precise d etermin ation of PDM is
comple x and influenced by many factors:

1. Mounting pad area onto which the dev ice is attached and
whethe r the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air f low and board orientation.

6. For no n steady st ate applic ations, the pulse widt h, the
duty cycle and the tran sient thermal response of the part,
the boa rd and the enviro nment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 bo ar d with 1oz copp er after 1 00 0 se c o n ds
of stea dy st ate powe r w ith n o air flow . Th is gr aph prov ides
the necessary information for calc ulation of the steady s tate
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manu ally utilizin g the normal ized
maximum transient thermal impedance curve.

80

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

1100.1

Pad Area

FDB3652_F085 N-Channel PowerTrench

®

MOSFET

Therma l resist ances corresp onding to other co pper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

19.84

-------------------------------------

R

=

θJA

R

=

θJA

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev. A1

26.51

26.51

+

0.262 Area+()

Area in Iches Squared

128

----------------------------------

+

1.69 Area+()

Area in Centimeter Squared

(EQ. 2)

(EQ. 3)

7

PSPICE Electrical Model

.SUB CK T F DP 3 652 2 1 3 rev Mar ch 200 2
Ca 12 8 1.1e-9
Cb 15 14 1.1e-9
Cin 6 8 2.8e-9

Dbod y 7 5 Dbody M OD
Dbreak 5 11 D breakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 108.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 7.16e -9

Ldrain 2 5 1.0e -9
Lsource 3 7 2.29e-9

RLgate 1 9 71.6
RLdr ai n 2 5 10
RLsource 3 7 22.9

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.7e-3
Rgate 9 20 1.06
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13814

S1B

EGS EDS

­6

8

13

10

RSLC2

6

13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

S2A

S2B

5

RSLC1

51

+

5

51

­50

RDRAIN

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

ESLC

16

8

MMED

8

DBREAK

11

+

17

EBREAK

IT

18

-

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

7

+

RVTEMP
19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB3652_F085 N-Channel PowerTrench

®

MOSFET

ESLC 51 50 VALUE={(V(5,5 1)/ABS(V(5, 51)))*(PWR(V(5,51)/(1e-6*150),7))}
.MODEL DbodyMOD D (IS=1.5E-11 N=1.06 RS=2.5e-3 TRS1=2.4e-3 TRS2=1.1e-6

+ CJO=1.9e-9 M= 5.8e-1 TT=2.5 e-8 XTI=3.9)
.MODEL DbreakMOD D (RS= 2. 7e-1 TRS1=1e-3 TRS 2=-8.9e-6)
.MODEL DplcapMOD D (CJO=7e-10 IS=1e-30 N=10 M=0.58)
.MODEL MmedMOD NMOS (VTO= 3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06)
.MODEL Mstro M OD NMOS (VTO=4.3 KP=110 IS=1e-30 N=10 T OX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO= 3 KP=0.03 IS=1e-3 0 N=10 TOX=1 L=1u W=1u RG=1.06e1 RS=.1)
.MODEL RbreakMOD RES (T C1=1.05e-3 TC 2=1e-6)
.MODEL Rd rai nMOD RES (TC 1=1.7e-2 TC2=3.2e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-7)
.MODEL RsourceMOD RES (TC 1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (T C1=-5.3e-3 TC 2=-1.2e-5)
.MODEL RvtempMOD RES (T C1=-3.3e-3 TC 2=1.3e-6)

.MODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 8 VOFF =-5 )
.MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 5 VOFF =-8 )
.MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1 VOFF =0.5)
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .5 VOFF= -1)

.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronic s S pecialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev. A1

8

SABER Electrical Model

REV March 2002
template FDP3652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9)
dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e- 6)
dp..m odel dplcap m od = (cjo=7e-10,i sl = 10e- 30 , nl=1 0,m=0.58)
m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1)
sw_vcsp.. mo del s1amod = (ron=1e- 5,roff=0.1,vo n=-8,voff=-5)
sw_vcsp.. mo del s1bmod = (ron=1e- 5,roff=0.1,vo n=-5,voff=-8)
sw_vcsp.. mo del s2amod = (ron=1e- 5,roff=0.1,vo n=-1,voff=0.5)
sw_vcsp.. mo del s2bmod = (ron=1e- 5,roff=0.1,vo n=0.5,voff=-1)
c.ca n12 n8 = 1. 1e-9
c.cb n15 n14 = 1.1e-9
c.cin n6 n8 = 2.8e -9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 108.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1

GATE

spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1

LGATE

1

9

RLGATE

RGATE

ESG

EVTEMP
+

20

spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1

CA

S1A

12

S1B

l.lgate n1 n9 = 7.16e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.29e-9

res.rlgate n1 n9 = 71.6
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 22.9

m.mmed n16 n6 n8 n8 = m odel=mmedmod, l= 1u, w=1u
m.mstrong n16 n6 n8 n8 = model=ms tr ongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakm od, l=1u, w=1u

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

6

-

18
22

S2A

13814

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

50
RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

17
18

­7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB3652_F085 N-Channel PowerTrench

®

MOSFET

res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=1e-6
res.rdrain n50 n16 = 5.7e-3, tc1=1. 7e-2,tc2=3. 2e-5
res.rgate n9 n20 = 1.06
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsour ce n8 n7 = 6.5e-3, tc1=1e-3,tc2=1e- 6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.2e-5
res.rvtemp n18 n19 = 1, tc1=-3.3e-3,tc2=1.3e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model= s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model= s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model= s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5, n51)/(1e-9+abs(v(n5,n51) )))*((abs(v(n5,n51)*1e 6/ 150))** 7))
}
}

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev. A1

9

SPICE Thermal Model

REV 23 March 2002
FDP3652
CTHERM1 TH 6 1e-2

CTHERM2 6 5 1. 5e-2
CTHERM3 5 4 2e-2
CTHERM4 4 3 2. 1e-2
CTHERM5 3 2 2. 2e-2
CTHERM6 2 TL 9e-2

RTHERM1 TH 6 2.7e-2
RTHERM2 6 5 2. 8e-2
RTHERM3 5 4 7. 8e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 2. 7e-1
RTHERM6 2 TL 2.87e-1

SABER Thermal Model

SABER therm al m odel F DP3652
template thermal_model th tl
thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =1e-2
ctherm.ctherm2 6 5 =1.5e-2
ctherm.ctherm3 5 4 =2e-2
ctherm.ctherm4 4 3 =2.1e-2
ctherm.ctherm5 3 2 =2.2e-2
ctherm.ctherm6 2 tl =9e-2

rtherm.rtherm1 th 6 =2.7e-2
rtherm.rther m 2 6 5 =2.8e -2
rtherm.rther m 3 5 4 =7.8e -2
rtherm.rther m 4 4 3 =9e-2
rtherm.rther m 5 3 2 =2.7e -1
rtherm.rther m 6 2 tl =2.87 e- 1
}

th

RTHERM1

6

RTHERM2

5

RTHERM3

4

RTHERM4

3

RTHERM5

2

FDB3652_F085 N-Channel PowerTrench

JUNCTION

CTHERM1

CTHERM2

CTHERM3

®

MOSFET

CTHERM4

CTHERM5

RTHERM6

tl

©2008 Fairchild Semiconductor Corporation FDB3652_F085Rev. A1

10

CTHERM6

CASE

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Rev. I37

©2008 Fairchild Semiconductor Corporation FDB3652_F085 Rev. A1

11