Datasheet FDP2532, FDB2532 Datasheet (Fairchild Semiconductor)

FDB2532 / FDP2532 / FDI2532

N-Channel PowerTrench® MOSFET 150V, 79A, 16mΩ

FDB2532 / FDP2532 / FDI2532

August 2002

Features

•r

•Q

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82884

= 14mΩ (Typ.), V

DS(ON)

(tot) = 82nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 33A

GS

= 10V

GS

Applications

• DC/DC converters and Off-Line UPS

• Distributed Pow er Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Re ctifier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Lo ad Control

• Electronic Valve T rain System s

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

GATE

SOURCE

TO-220AB

FDPSERIES

MOSFET Maximum Ratings T

DRAIN

(FLANGE)

TO-263AB

FDB SERIES

= 25°C unless otherwise noted

C

DRAIN

(FLANGE)

SOURCE

TO-262AB

FDISERIES

DRAIN

GATE

G

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 150 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 56 A

C

= 25oC, VGS = 10V, R

amb

= 43oC/W) 8 A

θJA

79 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 400 mJ Power dissipation 310 W

o

Derate above 25

C2.07W/

Operating and Storage Temperature -55 to 175

D

S

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and envir onment deman ded by the automot ive indus t ry. For a

All Fairchild Semiconductor prod ucts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

Thermal Resistance Junction t o Case TO-220, TO-263, TO -262 0.48 Thermal Resistance Junction t o Ambient TO-220, TO-262 (Note 2) 62 Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad ar ea 43

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

FDB2532 / FDP2532 / FDI2532 Rev. B

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB2532 FDB2532 TO-263AB 330mm 24mm 800 units FDP2532 FDP2532 TO-220AB Tube N/A 50 units

FDI2532 FDI2532 TO-262AB Tube N/A 50 units

FDB2532 / FDP2532 / FDI2532

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain t o Source Breakdown Volta ge ID = 250µA, VGS = 0V 150 - - V

V

= 120V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

= 33A, VGS = 10V - 0.014 0.016

I

D

I

= 16A, VGS = 6V, - 0.016 0.024

Drain to Source On Resistance

D

= 33A, VGS = 10V,

I

D

T

= 175oC

C

- 0.040 0.048

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitance - 615 - pF Reverse Transfer Capacitance - 135 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total G ate Ch arg e at 10 V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 11 14 nC Gate to Source Gate Charge - 23 - nC Gate Charge Threshold to Plateau - 13 - nC

V

DD

I

= 33A

D

I

= 1.0m A

g

= 75V

Gate to Drain “Miller” Charge - 19 - nC

-5870- pF

-82107nC

µA

Ω

Resistive Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time Turn-On Delay Time - 16 - ns Rise Time - 30 - ns T u rn-Off Delay Time - 39 - ns Fall Time - 17 - ns Turn-Off Time - - 84 ns

(VGS = 10V)

V

DD

V

GS

--69ns

= 75V, ID = 33A = 10V, RGS = 3.6Ω

Drain-Source Diode Characteristics

I

= 33A - - 1 .25 V

V

SD

t

rr

Q

RR

Notes: 1: Starting T 2: Pulse Width = 100s

Source to Drain Di ode Voltage Reverse Recovery Time ISD = 33A, dISD/dt= 100A/µs- - 105ns

Reverse Recovery Charge ISD = 33A, dISD/dt= 100A/µs - - 327 nC

= 25°C, L = 0.5 mH, IAS = 40A.

J

SD

= 16A - - 1.0 V

I

SD

FDB2532 / FDP2532 / FDI2532

Typical Characteristics T

= 25°C unless otherwise noted

A

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2.0 DUTY CYCLE - DESCENDING ORDER

0.5

1.0

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

125

V

= 10V

GS

100

75

50

, DRAIN CURRENT (A)

D

I

25

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

10-1 10

θJC

1/t2

0

x R

t

θJC

1

t

2

+ T

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

, PEAK CURRENT (A)

DM

I

2000

1000

100

50

VGS = 10V

-5

10

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC FOR TEMPERATURES

o

ABOVE 25

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

C

150

1

10

Figure 4. Peak Current Capability

Typical Characteristics T

= 25°C unl ess otherwise noted

A

FDB2532 / FDP2532 / FDI2532

1000

100

OPERATION IN THIS

10

, DRAIN CURRENT (A)

D

I

1

0.1

AREA MAY BE

LIMITED BY r

SINGLE PULSE TJ = MAX RATED

T

= 25oC

C

1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

10µs

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

180

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

150

V

= 15V

DD

120

90

60

, DRAIN CURRENT (A)

D

I

30

0

TJ = 25oC

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

200

STARTING TJ = 25oC

STARTING TJ = 150oC

- VDD)

DSS

= (L/R)ln[(IAS*R)/(1.3*RATED BV

tAV, TIME IN AVALANCHE (ms)

DSS

300

100

10

If R = 0

, AVALANCHE CURRENT (A)

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0 t

AV

1

0.001 0.01 0.1 1

NOTE: Refer to Fairchild Application Notes AN7515 and AN7517

Figure 6. Unclamped Inductive Switching

Capability

180

150

120

90

60

, DRAIN CURRENT (A)

D

I

30

0

0.0 1.0 2.0 3.0 4.0 5.0 6.0

VGS = 10V

VGS = 5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 7V

VGS = 6V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

- VDD) +1]

TC = 25oC

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

18

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

17

16

15

14

13

DRAIN TO SOURCE ON RESISTANCE (m Ω)

VGS = 6V

VGS = 10V

0 20406080

I

, DRAIN CURRENT (A)

D

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

3.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID =33A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB2532 / FDP2532 / FDI2532

Typical Characteristics T

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unl ess otherwise noted

A

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

10000

C

= CGS + C

1000

ISS

C

≅ C

+ C

OSS

DS

GD

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 75V

8

6

C

= C

RSS

GD

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

50

0.1 1 10 150 VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 20406080100

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 33A I

= 16A

D

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

Test Circuits and Waveforms

FDB2532 / FDP2532 / FDI2532

BV

DSS

t

P

V

DS

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

V

= 2V

GS

Q

0

Q

g(TH)

I

g(REF)

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

0

V

DD

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

Thermal Resistance vs. Mounting Pad Area

80

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maxi mum al lowab le de vice p ower di ssip ation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

serve s as the basis for establ ishing the rating of the part.

TJMTA–()

P

----------------- ------------=

DM

R

θJA

DM

(oC/W)

θJA

(EQ. 1)

, in an

60

C/W)

o

(

θJA

R

40

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

FDB2532 / FDP2532 / FDI2532

In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR- 4 bo ar d with 1 oz c opper after 1 000 se c on ds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary inf ormation for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or ma nually utiliz ing the norm alized maximum transient thermal impedance curve.

20

1100.1

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Therma l resi stances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

19.84

26.51

=

R

θJA

26.51

=

R

θJA

-------------------------------------+

0.262 Area+()

Area in Inches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDB2532 2 1 3 ; rev April 2002 CA 12 8 1.4e -9 CB 15 14 1.6e-9 CIN 6 8 5.61e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 159 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 9.56e-9

Ldrain 2 5 1.0e -9 Lsource 3 7 7.71e-9

RLgate 1 9 95.6 RLdr ai n 2 5 10 RLsource 3 7 77.1

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 9.6e-3 Rgate 9 20 1.01 RSLC1 5 51 RSL CM OD 1.0e-6 RSLC2 5 50 1.0e 3 Rsource 8 7 RsourceMOD 3.0e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

-

13

10

6 8

+

RSLC2

6

S2A

14 13

S2B

6 8

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

RSLC1

51

5

51

50

RDRAIN

21

MSTRO

14

5 8

+

ESLC

16

8

MMED

8

DBREAK

11

+

17

EBREAK

IT

18

-

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

7

RLSOURCE

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB2532 / FDP2532 / FDI2532

ESLC 51 50 VALUE = {(V(5,5 1)/ABS(V (5,51)))*(PWR(V(5 ,51)/(1e-6*190),3))} .MODEL DbodyMOD D (IS=6.0E-11 N=1.09 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6

+ CJO=3.9e-9 M= 0.65 TT=4.8e-8 XTI=4.2) .MODEL DbreakMOD D (R S=0.17 TRS1 =3.0e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.0e-9 IS=1.0e-30 N=10 M=0.6)

.MODEL MmedM OD NMOS (VTO=3.55 KP= 10 I S=1e-30 N=10 TO X = 1 L=1u W=1u RG =1. 01) .MODEL Mstro M OD NMOS (VTO=4. 2 K P=145 IS=1e-30 N=10 TOX=1 L= 1u W=1u) .MODEL MweakMOD NMOS (VT O=2.9 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=10.1 RS =0.1)

.MODEL Rb reakMOD RES (TC1=1.1e-3 TC2=-9.0e-7) .MODEL Rd rai nMOD RES (T C1=9.0e-3 TC2=3.5e-5) .MODEL RSLCMOD RES (TC1=3.4e-3 TC2=1.5e-6) .MODEL RsourceMOD RES (T C1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RE S (TC1=-4.1e-3 TC2=-1 .4e-5) .MODEL RvtempMOD RE S (T C1=-4.0e-3 T C2=3.5e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 6. 0 VOFF =-4 .0 ) .MODEL S1BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4. 0 VOFF =-6 .0 ) .MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.4 VO FF=1.0) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 1 .0 VOFF= -1.4)

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electro ni cs Specialist Confere nce Records, 1991, writte n by William J. Hepp and C. Frank Wheatley.

SABER Electrical Model

REV April 2002 ttemplate F DB 2532 n2,n1,n 3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=6.0e-11,nl=1.09,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=3.9e-9,m=0.65,tt=4.8e-8,xti=4.2) dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e -6) dp..m odel dpl capmod = (cjo=1.0 e-9,isl= 10.0e- 30,nl=10,m=0.6) m..model mmedmod = (type=_n,vto=3.55,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.2,kp=145,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.9,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron= 1e-5,roff=0.1,von=-6.0,voff=-4.0) sw_vcsp.. mo del s1bmod = (ron= 1e-5,roff=0.1,von=-4.0,voff=-6.0) sw_vcsp.. mo del s2amod = (ron= 1e-5,roff=0.1,von=-1.4,voff=1.0)

DPLCAP

10

sw_vcsp.. mo del s2bmod = (ron= 1e-5,roff=0.1,von=1.0,voff=-1.4) c.ca n12 n8 = 1.4e -9 c.cb n15 n14 = 1.6e-9

RSLC2

c.cin n6 n8 = 5.61 e-9 dp.dbody n7 n5 = model=dbody m od

dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dpl capmod

spe.ebreak n11 n7 n17 n18 = 159 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1

GATE

1

spe.esg n6 n10 n6 n8 = 1

LGATE

RLGATE

RGATE

9

ESG

EVTEMP

+

20

6

8

EVTHRES

+

6

-

18 22

spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 9.56e-9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 7.71e-9

res.rlgate n1 n9 = 95.6 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 77.1

12

CA

S1A

13

14

8

13

S1B

13

+

6

EGS EDS

8

-

S2A

S2B

m.mmed n16 n6 n8 n8 = m odel=mmed m od, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=m strongmod, l= 1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w = 1u

5

RSLC1

51

ISCL

8

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

50 RDRAIN

16

+

21

-

19

8

MSTRO

CIN

15

CB

14

+

5 8

-

17 18

7

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB2532 / FDP2532 / FDI2532

res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-9.0e-7 res.rdrain n50 n16 = 9.6e-3, tc 1=9. 0e-3,tc2 =3.5e-5 res.rgate n9 n20 = 1.01 res.rslc1 n5 n51 = 1.0e-6, tc1 =3.4e-3,tc2=1.5e-6 res.rslc2 n5 n50 = 1.0e3 res.rsour ce n8 n7 = 3.0e-3, tc1=4.0e-3,tc 2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-4. 1e-3,tc2= -1.4e-5 res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=3.5e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2 a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2 b n13 n15 n14 n13 = mod el= s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51) )))*((abs(v(n5,n51) * 1e6/190))** 3)) } }

FDB2532 / FDP2532 / FDI2532

SPICE Thermal Model

REV 26 February 2002 FDB2532 CTHERM1 TH 6 7.5e-3

CTHERM2 6 5 8. 0e-3 CTHERM3 5 4 9. 0e-3 CTHERM4 4 3 2. 4e-2 CTHERM5 3 2 3. 4e-2 CTHERM6 2 TL 6.5e-2

RTHERM1 TH 6 3.1e-4 RTHERM2 6 5 2. 5e-3 RTHERM3 5 4 2. 0e-2 RTHERM4 4 3 8. 0e-2 RTHERM5 3 2 1. 2e-1 RTHERM6 2 TL 1.3e-1

SABER Thermal Model

SABER therm al m odel F DB2532 template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =7.5e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =2.4e-2 ctherm.ctherm5 3 2 =3.4e-2 ctherm.ctherm6 2 tl =6.5e-2

rrtherm.rtherm1 th 6 =3.1e-4 rtherm.rt herm2 6 5 =2.5e-3 rtherm.rt herm3 5 4 =2.0e-2 rtherm.rt herm4 4 3 =8.0e-2 rtherm.rt herm5 3 2 =1.2e-1 rthe r m.rtherm6 2 tl =1.3 e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

CASE

tl

TRADEMARKS

The following are registe red and unr egistered trademarks Fairchild Semiconductor owns or is aut horized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ ActiveArray™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™

2

E

CMOS™

EnSigna™

FACT™ FACT Quiet Series™

®

FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™

2

I

C™ Across the board. Around the world.™ The Power Franchise™ Programma ble Active Droop™

ImpliedDisconnect™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC

®

OPTOPLANAR™

PACMAN™ POP™ Power247™ PowerTrench

®

QFET™ QS™ QT Optoelectronics™ Quiet Ser ies™ RapidConfigure™ RapidConnect™ SILENT SWITCHER SMART START™

SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET

®

VCX™

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) ar e int ende d fo r s urgic al i mpla nt into the bo dy, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Adva nce Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supple m entary data will be published at a later dat e. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the righ t to make chan ges at any time without notice in order to improve design.

that has been discontinued b y Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I1