Datasheet FB2041BB Datasheet (Philips)

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FB2041

7-bit Futurebus+ transceiver

Product specification IC19 Data Handbook

1995 May 25

INTEGRATED CIRCUITS

Page 2

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25 853-1561 15279

DESCRIPTION

The FB2041 is a 7-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2041 is an inverting transceiver.

The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V .

FEA TURES

•7-bit BTL transceiver

•Separate I/O on TTL A-port

•Inverting

•Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit

arrangement

•Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Each BTL driver has a dedicated Bus GND for a signal return

•Glitch-free power up/power down operation

•Low I

current

•Tight output skew

•Supports live insertion

•Pins for the optional JTAG boundary scan function are provided

•High density packaging in plastic Quad Flatpack

QUICK REFERENCE DA TA

SYMBOL PARAMETER TYPICAL UNIT

PLH

Propagation delay 3.7

PHL

AIn to Bn 2.7

PLH

Propagation delay 3.4

PHL

Bn to AOn 3.2

Output capacitance (B0 - B6 only) 6 pF

Output current (B0 - B6 only) 100 mA

Standby 19

AIn to Bn (outputs Low or High) 40

Supply Current

Bn to AOn (outputs Low) 22

Bn to AOn (outputs High) 19

ORDERING INFORMATION

PACKAGE

COMMERCIAL RANGE

VCC = 5V±10%; T

amb

= 0 to +70°C

INDUSTRIAL RANGE

VCC = 5V±10%; T

amb

= -40 to +85°C

DWG

No.

52-pin Plastic Quad Flatpack FB2041BB CD3207BB SOT379-1

Page 3

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

PIN CONFIGURATION

52 51 50 49 48 47 46 45 44 43 42 41 40

39 38 37 36 35 34 33

32 31 30 29 28 27

1 2 3 4 5 6 7

9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND

LOGIC GND

AI1

AI2

AO2

LOGIC GND

AO3

LOGIC GND

AI3

AI4

AO4

LOGIC GND

AO5

LOGIC GND

AI5

LOGIC GND

AO6

LOGIC GND

TDO (option)

TDI (option)

AI6

OEB3

BUS V

LOGIC V

AO1

AO0

OEA1

TCK (option)

TMS (option)

BUS GND

OEB1

BIAS V

BUS V

LOGIC V

OEB0

7-Bit Transceiver

FB2041

52-lead PQFP

AI0

OEB2

OEA3

OEA2

The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.

There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1

, output drivers for bits 1–2–3 are enabled with

OEA2/OEB2

and output drivers for bits 4–5–6 are enabled with

OEA3/OEB3

The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEAn goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEAn goes Low, A-port drivers become High impedance without any extra delay. During power on/of f cycles, the A-port drivers are held in a High impedance state when V

is below 2.5V .

The B-port has an output enable, OEB0, which affects all seven drivers. When OEB0 is High and OEBn

is Low the output driver will

be enabled. When OEB0 is Low or if OEBn

is High, the B-port

drivers will be inactive and at the level of the backplane signal.

To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while V

is Low. If live insertion is not a requirement, the

BIAS V pin should be tied to a V

pin.

The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot.

The LOGIC V

and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together.

JTAG boundary scan functionality is provided as an option with signals TMS, TCK, TDI and TDO. When this option is not present, TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally.

Page 4

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

AI0 – AI6 51, 2, 3, 8, 9, 14, 18 Input Data inputs (TTL)

AO0 – AO6 50, 52, 4, 6, 10, 12, 16 Output 3-state outputs (TTL)

B0 – B6 40, 38, 36, 34, 32, 30, 28 I/O Data inputs/Open Collector outputs, High current drive (BTL)

OEB0 46 Input Enables the Bn outputs when High OEB1 45 Input Enables the B0 output when Low OEB2 25 Input Enables the B1 – B3 outputs when Low OEB3 26 Input Enables the B4 – B6 outputs when Low OEA1 47 Input Enables the A0 outputs when High OEA2 20 Input Enables the A1 – A3 outputs when High OEA3 24 Input Enables the A4 – A6 outputs when High

BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V)

LOGIC GND 1, 5, 7, 11, 13, 15, 19 GND Logic ground (0V)

BUS V

23, 43 Power Positive supply voltage

LOGIC V

17, 49 Power Positive supply voltage

BIAS V 48 Power Positive supply voltage

TMS 42 Input Test Mode Select (no-connect) TCK 44 Input Test Clock (no-connect)

TDI 22 Input Test Data In (shorted to TDO)

TDO 21 Output Test Data Out (TDI)

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

PARAMETER RATING UNIT

Supply voltage -0.5 to +7.0 V

AI0 – AI6, OEB0, OEBn, OEAn -1.2 to +7.0 V

In ut voltage

B0 – B6 -1.2 to +5.5

Input current -18 to +5.0 mA

OUT

Voltage applied to output in High output state -0.5 to +V

Current applied to output in AO0 – AO6 48 mA

OUT

Low output state B0 – B6 200

STG

Storage temperature -65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

COMMERCIAL LIMITS

VCC = 5V±10%;

amb

= 0 to +70°C

INDUSTRIAL LIMITS

VCC = 5V±10%;

amb

= -40 to +85°C

UNIT

MIN TYP MAX MIN TYP MAX

Supply voltage 4.5 5.0 5.5 4.5 5.0 5.5 V

Except B0–B6 2.0 2.0 V

VIHHigh-level in ut voltage

B0 – B6 1.62 1.55 1.62 1.55

Except B0–B6 0.8 0.8 V

VILLow-level in ut voltage

B0 – B6 1.47 1.47

Input clamp current -18 -18 mA

High-level output current AO0 – AO6 -3 -3 mA

AO0 – AO6 24 24 mA

IOLLow-level out ut current

B0 – B6 100 100

Output capacitance on B port 6 7 6 7 pF

amb

Operating free-air temperature range 0 +70 -40 +85 °C

Page 5

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

FUNCTION TABLE

MODE INPUTS OUTPUTS

AIn Bn* OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3 AOn Bn*

L — H L L L L L L Z H**

AIn to Bn H — H L L L L L L Z L

L — H L L L H H H L H** H — H L L L H H H H L L — H L X X L L L Z H**

AI0 to B0 H — H L X X L L L Z L

L — H L X X H H H L H** H — H L X X H H H H L L — H X L X L L L Z H**

AI1 – AI3 to B1 – B3 H — H X L X L L L Z L

L — H X L X H H H L H** H — H X L X H H H H L L — H X X L L L L Z H**

AI4 – AI6 to B4 – B6 H — H X X L L L L Z L

L — H X X L H H H L H** H — H X X L H H H H L

Disable Bn outputs X X L X X X X X X X H**

X X X H H H X X X X H** Disable B0 outputs X X H H X X X X X X H** Disable B1 – B3 outputs X X H X H X X X X X H** Disable B4 – B6 outputs X X H X X H X X X X H**

X L L X X X H H H H Input Bn to AOn X H L X X X H H H L Input

X L X H H H H H H H Input

X H X H H H H H H L Input

X L L X X X H X X H Input B0 to AO0 X H L X X X H X X L Input

X L X H H H H X X H Input

X H X H H H H X X L Input

X L L X X X X H X H Input B1 – B3 to AO1 – AO3 X H L X X X X H X L Input

X L X H H H X H X H Input

X H X H H H X H X L Input

X L L X X X X X H H Input B4 – B6 to AO4 – AO6 X H L X X X X X H L Input

X L X H H H X X H H Input

X H X H H H X X H L Input Disable AOn outputs X X X X X X L L L Z X Disable AO0 outputs X X X X X X L X X Z X Disable AO1 – AO3 outputs X X X X X X X L X Z X Disable AO4 – AO6 outputs X X X X X X X X L Z X

NOTES:

H = High voltage level L = Low voltage level X = Don’t care Z = High-impedance (OFF) state — = Input not externally driven H** = Goes to level of pull-up voltage B* = Precaution should be taken to ensure B inputs do not float.

If they do, they are equal to Low state.

Z = High-impedance (OFF) state — = Input not externally driven H** = Goes to level of pull-up voltage B* = Precaution should be taken to ensure B inputs do not float.

If they do, they are equal to Low state.

Page 6

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

LOGIC DIAGRAM

SG00071

OEB0

OEB1

OEA1

BTL

Levels

TTL

Levels

TMS TCK

TDI

TDO

42 44 22 21

(Future JTAG Boundary Scan option)

LOGIC V

= 17, 49 LOGIC GND = 1, 5, 7, 11, 13, 15, 19 BUS V

= 23, 43 BUS GND = 27, 29, 31, 33, 35, 37, 39, 41 BIAS V = 48

AI0

AO0

OEB2

OEA2

AI1

AO1

AI2

AO2

AI3

AO3

OEB3

OEA3

AI4

AO4

AI5

AO5

AI6

AO6

Page 7

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

LIVE INSERTION SPECIFICA TIONS

LIMITS

SYMBOL

PARAMETER

MIN TYP MAX

UNIT

BIASV

Bias pin voltage VCC = 0 to 5.25V , Bn = 0 to 2.0V 4.5 5.5 V

VCC = 0 to 4.75V , Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V

1 mA

BIASV

Bias pin DC current

VCC = 4.5 to 5.5V , Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V

10 µA

Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V

Fall current during prebias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA

Rise current during prebias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA

IBnPEAK

Peak bus current during insertion

VCC = 0 to 5.25V , B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns

10 mA

= 0 to 5.25V , OEB0 = 0.8V 100

IOLOFF

Power up current

= 0 to 2.2V, OEB0 = 0 to 5V 100

Input glitch rejection VCC = 5.0V 1.0 1.35 ns

DC ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range unless otherwise noted.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN TYP2MAX

UNIT

High level output current B0 – B6 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA

OFF

Power-off output current B0 – B6 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA

High-level output voltage

AO0 – AO6

VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 2.5 2.85 V

AO0 – AO6

VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA 0.33 0.5

Low-level output voltage B0 – B6 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA .75 1.0 1.10 V

VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA 1.15

Input clamp voltage VCC = MIN, II = I

-1.2 V

Input current at maximum input voltage

OEB0, OEBn, OEAn, AI0 – AI6 VCC = MAX, VI = GND or 5.5V ±50 µA

High-level input current

OEB0, OEBn, OEAn, AI0 – AI6 VCC = MAX, VI = 2.7V 20

B0 – B6 VCC = MAX, VI = 2.1V 100

Low-level input current

OEB0, OEBn, OEAn, AI0 – AI6

VCC = MAX, VI = 0.5V

-20

B0 – B6 VCC = MAX, VI = 0.75V -100

OZH

Off-state output current AO0 – AO6 VCC = MAX, VO = 2.7V 50 µA

OZL

Off-state output current AO0 – AO6 VCC = MAX, VO = 0.5V -50 µA

Output current AO0 – AO6 only VCC = MAX -30 -55 -150 mA

CCZ

(standby) VCC = MAX 19 30

CCB,

AIn to Bn VCC = MAX, outputs Low or High 40 60

ICCSupply current (total)

CCA,

Bn to AOn VCC = MAX, outputs Low 22 35

CCA,

Bn to AOn VCC = MAX, outputs High 19 35

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.

2. All typical values are at V

= 5V, TA = 25°C.

3. Due to test equipment limitations, actual test conditions are V

= 1.8V and VIL = 1.3V for the B side.

Page 8

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

AC ELECTRICAL CHARACTERISTICS (Commercial)

A PORT LIMITS

SYMBOL PARAMETER

TEST

CONDITION

amb

= +25°C, VCC = 5V,

CL = 50pF, RL = 500Ω

amb

= 0 to 70°C,

VCC = 5V±10%,

CL = 50pF, RL = 500Ω

UNIT

MIN TYP MAX MIN MAX

PLH

PHL

Propagation delay, Bn

to AOn

Waveform 1, 2

1.8

1.6

3.4

3.2

5.0

4.9

1.6

5.5

5.0

PZH

PZL

Output enable time, OEA to AOn

Waveform 4, 5

2.2

2.0

5.0

4.0

6.5

2.0

1.8

10.0

8.0

PHZ

PLZ

Output disable time, OEA to AOn

Waveform 4, 5

1.5

1.8

3.3

3.0

4.8

5.0

1.2

1.5

5.0

5.5

TLH

THL

Transition time, AOn Port (10% to 90% or 90% to 10%)

Test Circuit and

Waveforms

1.5

2.2

2.4

3.0

1.5

3.5

tSK(o)

Output skew between receivers in same package

Waveform 3 0.4 1.0 1.0 ns

B PORT LIMITS

SYMBOL

PARAMETER TEST CONDITION

amb

= +25°C, VCC = 5V,

CD = 30pF, RU = 9Ω

amb

= 0 to 70°C,

VCC = 5V±10%,

CD = 30pF, RU = 9Ω

UNIT

PLH

PHL

Propagation delay, AIn to Bn

Waveform 1, 2

2.4

1.5

3.7

2.7

4.9

4.4

1.9

1.5

5.7

5.0

PLH

PHL

Enable/disable time, OEB0 to Bn

Waveform 2

2.4

1.9

3.7

3.5

4.9

1.9

1.8

6.4

5.4

PLH

PHL

Enable/disable time, OEB1 to Bn

Waveform 1

2.4

1.9

4.0

3.6

5.5

1.9

2.5

5.9

TLH

THL

Transition time, Bn Port (1.3V to 1.8V)

Test Circuit and

Waveforms

1.0

0.5

1.4

1.1

3.0

1.0

0.5

3.0

tSK(o)

Output skew between drivers in same package

Waveform 3 0.3 1.0 1.0 ns

SYMBOL PARAMETER TEST CONDITION RU = 16.5Ω RU = 16.5Ω UNIT

PLH

PHL

Propagation delay, AIn to Bn

Waveform 1, 2

2.5

1.6

3.8

2.8

5.0

4.5

2.0

1.6

5.8

5.1

PLH

PHL

Enable/disable time, OEB0 to Bn

Waveform 2

2.5

2.0

3.8

3.6

5.0

2.0

1.9

6.5

5.5

PLH

PHL

Enable/disable time, OEB1 to Bn

Waveform 1

2.5

2.0

4.1

3.7

5.6

2.0

2.6

6.0

TLH

THL

Transition time, Bn Port (1.3V to 1.8V)

Test Circuit and

Waveforms

1.0

0.5

1.5

1.1

3.0

1.0

0.5

3.0

tSK(o)

Output skew between drivers in same package

Waveform 3 0.3 1.0 1.0 ns

NOTES:

1.  t

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

Page 9

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

AC ELECTRICAL CHARACTERISTICS (Industrial)

A PORT LIMITS

SYMBOL PARAMETER

TEST

CONDITION

amb

= +25°C, VCC = 5V,

CL = 50pF, RL = 500Ω

amb

= -40 to +85°C,

VCC = 5V±10%,

CL = 50pF, RL = 500Ω

UNIT

MIN TYP MAX MIN MAX

PLH

PHL

Propagation delay, Bn

to AOn

Waveform 1, 2

1.8

1.6

3.4

3.2

5.0

4.9

1.6

5.5

PZH

PZL

Output enable time, OEA to AOn

Waveform 4, 5

2.2

2.0

5.0

4.0

6.5

1.5

8.0

PHZ

PLZ

Output disable time, OEA to AOn

Waveform 4, 5

1.5

3.3

3.0

4.8

5.0

0.8

1.2

6.0

TLH

THL

Transition time, AOn Port (10% to 90% or 90% to 10%)

Test Circuit and

Waveforms

1.5

2.2

2.4

3.0

1.5

3.5

tSK(o)

Output skew between receivers in same package

Waveform 3 0.4 1.0 1.0 ns

B PORT LIMITS

SYMBOL PARAMETER TEST CONDITION

amb

= +25°C, VCC = 5V,

CD = 30pF, RU = 9Ω

amb

= -40 to +85°C,

VCC = 5V±10%,

CD = 30pF, RU = 9Ω

UNIT

PLH

PHL

Propagation delay, AIn to Bn

Waveform 1, 2

2.4

1.5

3.7

2.7

4.9

4.4

1.9

1.5

5.9

5.0

PLH

PHL

Enable/disable time, OEB0 to Bn

Waveform 2

2.4

1.9

3.7

3.5

4.9

1.9

1.8

6.4

5.9

PLH

PHL

Enable/disable time, OEB1 to Bn

Waveform 1

2.4

1.9

4.0

3.6

5.5

1.9

1.5

6.8

TLH

THL

Transition time, Bn Port (1.3V to 1.8V)

Test Circuit and

Waveforms

1.0

0.5

1.4

1.1

3.0

1.0

0.5

3.0

tSK(o)

Output skew between drivers in same package

Waveform 3 0.3 1.0 1.0 ns

SYMBOL PARAMETER TEST CONDITION RU = 16.5Ω RU = 16.5Ω UNIT

PLH

PHL

Propagation delay, AIn to Bn

Waveform 1, 2

2.5

1.6

3.8

2.8

5.0

4.5

2.0

1.6

6.0

5.1

PLH

PHL

Enable/disable time, OEB0 to Bn

Waveform 2

2.5

2.0

3.8

3.6

5.0

2.0

1.9

6.5

6.0

PLH

PHL

Enable/disable time, OEB1 to Bn

Waveform 1

2.5

2.0

4.1

3.7

5.5

2.0

1.6

6.9

TLH

THL

Transition time, Bn Port (1.3V to 1.8V)

Test Circuit and

Waveforms

1.0

0.5

1.5

1.1

3.0

1.0

0.5

3.0

tSK(o)

Output skew between drivers in same package

Waveform 3 0.3 1.0 1.0 ns

NOTES:

1.  t

actual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, V

, loading, etc.).

Page 10

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

AC WAVEFORMS

NOTE: V

= 1.55V for Bn, V

= 1.5V for all others.

AIn, Bn or Bn

OEBn

AOn or Bn

PLH

PHL

Waveform 1. Propagation Delay for Data

or Output Enable to Output

PHL

PLH

AOn, Bn

Waveform 2. Propagation Delay for Data

or Output Enable to Output

AIn, Bn

OEB0

AIn, Bn

AOn, Bn

tSK(o)

Waveform 3. Output Skews

AOn

OEA

VOH -0.3V

PHZ

PZH

Waveform 4. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

PZL

AOn

OEAn

PLZ

VOL +0.3V

Waveform 5. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

SG00079

Page 11

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

TEST CIRCUIT AND WAVEFORMS

2.5ns

2.5ns500ns

500ns

INPUT PULSE REQUIREMENTS

Rep. RateAmplitude t

TLHtTHL

1MHz3.0V

2.5ns

Input Pulse Definitions

VM = 1.55V for Bn, VM = 1.5V for all others.

Family

FB+

D.U.T.

PULSE

GENERATOR

7.0V

OUT

Test Circuit for 3-State Outputs on A Port

TEST SWITCH

SWITCH POSITION

PLZ,

PZL

All other

closed

open

DEFINITIONS:

RL= Load Resistor; see AC CHARACTERISTICS for value. CL= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

= Termination resistance should be equal to Z

OUT

of pulse generators.

CD= Load capacitance includes jig and probe capacitance; see AC

CHARACTERISTICS for value.

RU= Pull up resistor; see AC CHARACTERISTICS for value.

90%

10%

90%

10%

90%

10%

90%

10%

NEGATIVE PULSE

POSITIVE PULSE

LOW V

THL

(tf)

TLH

(tr)

BIAS

Low V

0.0V

TLH

(tr)

THL

(tf)

A Port

1MHz2.0V

2.5ns

1.0VB Port

D.U.T.

PULSE

GENERATOR

OUT

Test Circuit for Outputs on B Port

BIAS

2.0V (for RU = 9 Ω)

2.1V (for RU = 16.5 Ω)

SG00059

Page 12

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

Page 13

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

NOTES

Page 14

Philips Semiconductors Product specification

FB20417-bit Futurebus+ transceiver

1995 May 25

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 08-98 Document order number:

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Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1] Please consult the most recently issued datasheet before initiating or completing a design.