Datasheet FA13843P, FA13843N, FA13842P, FA13842N, FA13844P Datasheet (CALLM)

FA13842,13843,13844,13845

CMOS IC

F A13842, 13843, 13844, 13845

For Switching Power Supply Control

■ Description

The FA1384X series are CMOS current mode control ICs for
off-line and DC-to-DC converters.
These ICs can reduce start-up circuit loss and are optimum for
high efficiency power supplies because of the low power
dissipation achieved through changes in the CMOS fabrication
process.
These ICs can drive a power MOSFET directly.
The high-performance, compact power supply can be
designed with minimal external components .

■ Features

• CMOS process

• Low-power dissipation

• Standby current 2µA (max.), start-up current 30µA (max.)

• Pulse-by-pulse current limiting

• 5V bandgap reference

• UVLO (Undervoltage lockout) with hysteresis

• Maximum duty cycle FA13842, 13843: 96%
FA13844, 13845: 48%

• Pin-for-pin compatible with UC384X

Note: Pins are fully compatible, but characteristics are not.

When our ICs are applied to a power supply circuit
designed for other manufactures' 384X series, the
characteristics and safety features of the power supply
must be checked.

■ Dimensions, mm

Á SOP-8

5

4

4.9

1.27

0.4

8

1

±0.1

Á DIP-8

8

5

±0.2

6.4

3.9

±0.2

6.0

+0.1

–0.05

0.20

0~8°

1.7max

■ Types of FA1384X series

Type UVLO Maximum duty Package

Start threshold Stop threshold cycle

FA13842P 16.5V±1V 9V±1V 96% DIP
FA13842N SOP
FA13843P 9.6V±1V 9V±1V 96% DIP
FA13843N SOP
FA13844P 16.5V±1V 9V±1V 48% DIP
FA13844N SOP

FA13845P 9.6V±1V 9V±1V 48% DIP
FA13845N SOP

1

2.54

±0.25

9.3

1.5

4

0.46

±0.1

3.3

4.5max

3.0min

0~15˚

7.62

0.25

0~15˚

+0.1

–0.05

1

F A13842, 13843, 13844, 13845

■ Block diagram

Á FA13842, 13843

7

VCC

30V

RT/CT

4

ER AMP

2

FB

1

COMP

ISNS

3

Á FA13844, 13845

7

VCC

30V

UVLO

UVLO

2R

1R

UVLO

UVLO

1V

VCC

5V REF

ENB

2.5V

OSC

5V Controlled block

VCC

5V REF

ENB

2.5V

Pin No. Symbol Function Description

1 COMP Compensating Error amplifier output, available

8

VREF

2 FB Feedback Inverting input of the error

for loop compensation circuit

amplifier

OUTPUT
ENB

6

OUT

3 ISNS Current sensing Input voltage proportional to

inductor current

4 RT/CT Oscillator control Setting oscillation frequency

5

GND

and maximum duty-cycle with
resistor RT and capacitor CT

5 GND Ground Ground

S

Q

FF

QB

R

6 OUT Output Output for driving a power

MOSFET
7 VCC Power supply Power supply
8 VREF Reference voltage Reference voltage and

current source charging

capacitor CT through resistor

RT

VREF

8

OUTPUT

6

ENB

OUT

RT/CT

FB

COMP

ISNS

4

ER AMP

2
1

3

2R

1R

1V

OSC

5V ControlIed block

S

FF

QB

R

TFF

Q

CLK

QB

5

GND

Q

■ Absolute maximum ratings (Ta=25˚C)

Item Symbol Test condition Rating Unit

Supply voltage VCC Low impedance source 28 V

Zener clamp (Icc<10mA) Self limiting V
Zener current IZ 10 mA
Output peak current IO Source current 400 mA

Sink current 1 A
FB/ISNS terminal input voltage VIN FB, ISNS –0.3 to 5.3 V
Error amplifier sink current ISINK 10 mA
Total power dissipation Pd at Ta < 50˚C DIP 800 mW

SOP 400

Thermal resistance Rθ j-a Junction-air DIP 125 ˚C/W

SOP 250
Junction temperature Tj 150 ˚C
Ambient temperature Ta –25 to 85 ˚C
Storage temperature Tstg –40 to 150 ˚C

2

F A13842, 13843, 13844, 13845

■ Recommended operating conditions

Item Symbol Min. Max. Unit

Supply voltage VCC 10 25 V
Oscillation timing capacitor CT 0.47 10 nF
Oscillation timing resistor RT 2.0 100 kΩ
Oscillation frequency fOSC 10 500 kHz

■ Electrical characteristics (Vcc=15V, RT=10kΩ, CT=3.3nF, Ta=25˚C)
Reference voltage section

Item Symbol Test condition Min. Typ. Max. Unit

Reference voltage VREF Tj=25˚C, IL=1mA 4.75 5.00 5.25 V
Line regulation LINE Vcc=10 to 25V ±3 ±20 mV
Load current regulation LOAD IL=0 to 20mA ±3 ±25 mV
Temperature regulation VTC Ta=–25 to 85˚C ±0.3 mV/˚C
Output current at short-circuit IOS Tj=25˚C 60 mA

Oscillator section

Item Symbol Test condition Min. Typ. Max. Unit

Oscillation frequency fOSC Tj=25˚C 49 52 55 kHz

Ta=–25 to 85˚C 47 57 kHz
Voltage stability fdv Vcc=10 to 25V ±0.25 ±1%
Temperature stability fdt Ta=–25 to 85˚C –0.07 %/˚C
Oscillation amplitude VOSC Tj=25˚C 1.6 V
Discharge current IDISCHG Tj=25˚C 8.4 mA

Error amplifier section

Item Symbol Test condition Min. Typ. Max. Unit

Input voltage VFB COMP=2.5V, Tj=25˚C 2.4 2.5 2.6 V
Input leak current IFB ±2 µA
Open-loop gain AV 65 72 dB
Unity gain bandwidth fT 0.7 1 MHz
Output source current ISOURCE FB=2.3V, COMP=0V –0.8 –1.0 mA
Output sink current ISINK FB=2.7V, COMP=1V 2 15 mA
Output voltage VH COMP FB=2.3V, RL=15kΩ to GND 4.0 4.5 V

VL COMP FB=2.7V, RL=15kΩ to VREF 80 500 mV

Current sensing section

Item Symbol Test condition Min. Typ. Max. Unit

Voltage gain AV IS Tj=25˚C 2.85 3 3.15 V/V
Maximum input signal VTH IS FB=0V 0.9 1.0 1.1 V
Input bias current IIS –1 –5 µA
Delay to output TPD Tj=25˚C, ISNS to OUT 150 300 ns

3

F A13842, 13843, 13844, 13845

Output section

Item Symbol Test condition Min. Typ. Max. Unit

High-level output VOH I source=–20mA 14.5 14.75 V

I source=–100mA 12 13.5 V

Low-level output V OL I sink=20mA 0.15 0.3 V

I sink=200mA 1.5 3 V
Rise time tr CL=1nF, Tj=25˚C 40 150 ns
Fall time tf CL=1nF, Tj=25˚C 20 150 ns

Under-voltage lockout section

Item Symbol Test condition Min. Typ. Max. Unit

Start threshold VTH ON FA13842, 13844 15.5 16.5 17.5 V

FA13843, 13845 8.6 9.6 10.6 V
Min. operating voltage VTH OFF 8910V
Hysteresis VHYS FA13842, 13844 7.5 V

FA13843, 13845 0.6 V

PWM section

Item Symbol Test condition Min. Typ. Max. Unit

Maximum duty cycle Dmax FA13842, 13843 94 96 98 %

FA13844, 13845 47 48 50 %
Minimum duty cycle Dmin FB=5V, COMP=Open 0 %

Overall device

Item Symbol Test condition Min. Typ. Max. Unit

Standby current ICCL FA13842, 13844 Vcc=14V 2 µA

FA13843, 13845 Vcc=7V 2 µA
Start-up current ICC ST Vcc=Start threshold 12 30 µA
Operating current ICC OP 35mA
Zener voltage (Vcc) VZ Icc=5mA 28 30 34 V

4

F A13842, 13843, 13844, 13845

1

1025

R

T

timing resistance (kΩ)

Output maximum duty cycle (%)

40

50

60

70

80

90

100

■ Characteristic curves (Ta=25˚C)

Timing resistance vs. oscillation frequency Output dead time vs. oscillation frequency

FA13842, FA13843 FA13842, FA13843

100

10

resistance (kΩ)

T

R

1

1

CT=10nF

VCC= 15V
Ta= 25˚C

2.2nF

10 100 1000

Oscillation frequency (kHz)

470pF

100

VCC= 15V
Ta= 25˚C

10

Output dead time (%)

1

10

2.2nF

CT=10nF

100 1000

Oscillation frequency (kHz)

Timing resistance vs. oscillation frequency Output dead time vs. oscillation frequency

FA13844, FA13845 FA13844, FA13845

100

470pF

2.2nF

CT=10nF

100

VCC= 15V
Ta= 25˚C

90

80

470pF

10

resistance (kΩ)

T

R

VCC= 15V
Ta= 25˚C

1

101 100 1000

Oscillation frequency (kHz)

70

60

Output dead time (%)

50

40

10

CT=10nF

2.2nF

100 1000

Oscillation frequency (kHz)

470pF

RT/CT discharge current vs. temperature Output max. duty cycle vs. timing resistance

FA13842, FA13843

10

9.5

9

8.5

8

RT/CT discharge current (mA)

7.5

7
–50

0 50 100 150

Temperature (˚C)

5

F A13842, 13843, 13844, 13845

ISNS threshold voltage vs. COMP voltage COMP source current vs. COMP voltage

1200

= 15V

V

CC

FB= 0V

1000

OUT= off

800

600

400

ISNS threshold voltage (mV)

200

0

0

1

2

COMP voltage (V)

3

4

5

–200

–400

–600

–800

COMP source current (µA)

–1000

–1200

0

0

1

2

COMP voltage (V)

3

COMP to ISNS offset voltage vs. temperature COMP source current vs. temperature

2.5

2

–800

VCC= 15V
COMP= 0V

–900

4

5

1.5

1

0.5

COMP to ISNS offset voltage (V)

0

–50

050

Temperature (˚C)

100 150

–1000

–1100

–1200

COMP source current (µA)

–1300

–1400

–50 0 50

Temperature (˚C)

Error amp open loop voltage gain and phase vs. VREF short circuit current vs. temperature
frequency

100

80

60

40

20

0

Open loop voltage gain (dB)

–20

Phase

Gain

0

180

Phase ( ˚)

80

VCC= 15V

= 0V

V

REF

70

60

50

40

VREF short circuit current (mA)

30

100

150

–40

10 100 1.0k 10k 100k

Frequency (Hz)

6

1.0M 10M

20

500 100 150

Temperature (˚C)

F A13842, 13843, 13844, 13845

2.50V

50.0ns

VCC= 15V
OUT CL= 2.2nF
Ta= 25˚C

VCC supply current vs. VCC supply voltage VCC startup current vs. VCC supply voltage

FA13842, FA13844

8

VCC startup current (µA)

14

12

10

8

6

4

Ta= 25˚C

RT= 10kΩ

= 3.3nF

C

7

T

OUT= No load

6

5

4

3

VCC current (mA)

2

1

0

0

13843/45

10

VCC voltage (V)

13842/44

20 30

2

0

14

14.5 15 15.5 16 16.5 17
VCC voltage (V)

Output waveform

Vcc=15V, OUT CL=1nF, Ta=25˚C Vcc=15V, OUT CL=2.2nF, Ta=25˚C

VCC= 15V
OUT CL= 1nF
Ta= 25˚C

2.50V

25.0ns

7

F A13842, 13843, 13844, 13845

ENB

OUTPUT

UVLO

UVLO

VCC
ENB

2.5V

5V REF

OSC

30V

RT/CT

FB

COMP

ISNS

VREF

OUT

GND

2R

RS

MOSFET

1R

1V

S

FF

Q

QB

R

Vcc

Vin

VCC

ER AMP

RT

CT

7

4

2
1

3

5

6

8

■ Description of each circuit

1. Oscillator

The oscillation frequency is determined by timing resistance R
and timing capacitor CT, which are connected to RT/CT
terminal. C
reference, and discharged to about 1.4V by the built-in
discharge circuit. (See Fig. 1, 2, 3.)
Blanking pulses are generated in the IC during the C
discharge period.
The output is fixed in the “low” state by these pulses, and a
fixed dead time is produced. See the characteristic curves on
page 45 for the oscillation frequency , R
In the case of FA13844/45, a flip-flop causes the output to be
blanked with every other cycle. Therefore, the switching
frequency of a power MOSFET is 1/2 of the oscillation
frequency determined by R

2. Error amplifier

Inverting input and output are connected to the FB terminal
and COMP terminal, respectively. A 2.5V reference is
connected internally to the non-inverting input.
The output voltage is offset by a diode V
divided by three. The divided voltage is connected to the input
of the current sensing comparator .

3. Current sensing comparator and PWM latch

The “High” state of the OUT terminal begins at the time C
starts charging. The OUT terminal turns to “Low” when the
peak inductor current reaches the threshold level controlled by
the error amplifier output (COMP terminal).
The inductor current is converted to a voltage by sensing
resistor R
MOSFET. This voltage is monitored by the ISNS terminal.

is charged to about 3V through RT from a 5V

T

T

T and CT.

T and CT. (See Fig. 3.)

F voltage (=0.7V) and

T

S inserted between GND and the source of a power

T

Fig. 1

3V

CT

1.4V

Set

COMP
ISENS

Reset

The peak current of inductor “Ipk” is expressed as follows:
Ipk=(Vcomp–0.7) / (3•R

Vcomp: a voltage on COMP terminal

) 0.7V VF

S

The maximum value of the threshold level of the current
sensing comparator is held to 1V. Therefore, the maximum
peak current “Ipk(max)” is as follows:
Ipk(max)=1.0V/R

S

4. Undervoltage lockout (UVLO)

In order to set the IC in the operation mode before the output
stage(OUT terminal) is enabled, two under-voltage lockout
comparators are incorporated to monitor the power supply
voltage (V
The threshold level of the V
FA13842/44 and 9.6V/9V for FA13843/45. In the standby
mode, in which the V

CC) and reference voltage (VREF).

CC comparator is set at 16.5V/9V for

CC is under ON threshold, the power

supply current is maintained at nearly 0 (zero). However, a
maximum current of 30µA is required to change from standby
mode to operating mode .
The threshold level of the V

2.0V.
A 30V zener diode is connected to V
IC against overvoltages.

8

comparator is set at about 3.2V/

REF

CC

and GND to protect the

OUT

Fig. 2 FA13842, 13843

3V

CT

1.4V

Set

COMP
ISENS

Reset

OUT

Fig. 3 FA13844, 13845

5. Output stage

4

3

2

Start-up time[sec]

1

0

0 200 400 600

Start-up resistance R1 (kΩ)

C2=47µF

C2=10µF

800 1000 1200

C2=22µF

Input:100V AC

+

D3

R2

ER AMP

2R

1R

Synchronized

C4

OSC

REF

5

1

2

4

RT

CT

8

~+

~

DB

R1

D1

C2

MOSFET

Rs

6

7

FA13842

+

C1

T1

AC INPUT

+

D2

R1

D1

C2

FA13842

+

C3

+

6

7

An output stage of CMOS inverter composition is incorporated,
thereby making it possible to fully swing the gate voltage of a
power MOSFET to the V

CC.

The output stage provides a source current of 400mA and a
sink current of 1A as the peak current capacity. (When V

CC is

15V)
The output stage is held in the “Low” state in standby mode.

6. Reference voltage

The 5.0V(±5%) bandgap reference(Tj=25˚C) is built-in.
It is possible to supply a current of about 10mA to an external
circuit in addition to supplying a charge current to the timing
capacitor of the oscillator. (See characteristic curve on page

46.)
Connect a ceramic bypass capacitor of 0.1µF or higher to the
VREF terminal to stabilize this voltage.

■ Design advice

1. Start-up circuit

A typical start-up circuit is shown in Fig. 4.
The AC INPUT voltage charges capacitor C2 and supplies
start-up current to the IC through start-up resistance R1. When
this voltage reaches the ON threshold voltage, the IC reverts to
the operation mode and electric power is supplied from the
bias winding of the transformer thereafter.
Using CMOS process, the start-up current is less than 30µA.

When the start-up resistance is increased, the charging rate of
capacitor C2 decreases and start-up time increases. Select
the optimum values for R1 and C2.
The relation between the start-up resistance and start-up time
for the circuit indicated in Fig. 4 is shown in Fig. 5.
Fig. 6 indicates a method to increase the start-up resistance to
reduce loss and shorten start-up time. The start-up time is
shortened by reducing the capacitance of C2. The bias current
is supplied from C3 after start-up.

F A13842, 13843, 13844, 13845

Fig. 4

Fig. 5 Start-up time

2. Synchronized operation with external signals

The circuit shown in Fig. 7 allows synchronized operation with
external signals.
Synchronized operation is started when the RT/CT terminal
voltage is raised to about 3V or higher. (Synchronized at
leading edge.)
The external synchronizing signal should be higher than the
free-run frequency.
In the case of FA13844/45, the output frequency of the OUT
terminal is 1/2 that of the synchronizing signal frequency.

Fig. 6

Fig. 7

9

F A13842, 13843, 13844, 13845

3. Latched shutdown

A typical circuit for latched shutdown is shown in Fig. 8.
The voltage of the OUT terminal is kept low if the voltage of the
COMP terminal is low. The voltage of the COMP terminal
must be set at 0.7V or less in the application temperature
range. (See characteristic curve on page 46 ”COMP to ISNS
offset voltage vs temperature”.)
The source current from the COMP terminal is less than about

1.3mA.
Use of a thyristor such as that shown in Fig. 9 is not effective

because the saturation voltage of the thyristor is higher than

0.7V. When a thyristor is used, increase the voltage of the FB
terminal to more than 3V as shown in Fig.10. In the case of a
latched shutdown, it is necessary to supply a current larger
than the hold current of the thyristor structure circuit or of the
thyristor. This current should be provided through a start-up
resistor from the AC input.

Latched shutdown with a thyristor using the COMP
terminal is not effective.

AC INPUT

Latching signal

Tr2

R1

R3

DB

~

Tr1

R4

D4

MOSFET

+

ER AMP

T1

REF

OSC

2R

1R

5

+~

+

C1

D1

+

C2

7

8

30V

4

2

1

Latching signal

SCR1

Fig. 8

SCR2

C5

7

8

30V

4

++

2

ER AMP

1

REF

OSC

2R

1R

5

Fig. 10

7

8

30V

4

2

ER AMP

1

REF

OSC

Latching signal

2R

1R

R5

5

Fig. 9

10

F A13842, 13843, 13844, 13845

~+

~

DB

R1

D1

C2

+

MOSFET

Rs

6

1

7

FA13842

R4

R6

D5

R7

R8

PC1

Tr1

Tr2

R15

Tr5

R16

PC1

C6

R3

C1

T1

D6

R13

Tr4

+
C7

R14

AC INPUT

+

3-1 The method of detecting an overvoltage (detection

on primary side)

A typical latched shutdown circuit to protect against
overvoltages detected on the primary side is shown in Fig. 11.
When the secondary voltage increases in the flyback circuit,
the voltage of the bias winding also increases in proportion.
When this voltage increase is detected by zener diode ZD1, a
latched shutdown is accomplished. As the secondary voltage
is detected through a transformer, detection accuracy is low.

3-2 The method of detecting an overvoltage (detection

on secondary side)

A typical latched shutdown circuit to protect against
overvoltages detected on the secondary side is shown in
Fig. 12.
The detected voltage accuracy is high compared to
overvoltage detection on the primary side.

3-3 The method of detecting an overcurrent (detection

of primary current)

A typical primary overcurrent detection circuit is shown in
Fig. 13.

3-4 The method of detecting an overcurrent (detection

of secondary current)

A typical secondary overcurrent detection circuit is shown in
Fig. 14.

ZD1

AC INPUT

R6

DB

~+

~

R1

FA13842

1

+

C1

D1

+

7

C2

6

T1

MOSFET

Rs

R4

Tr1

AC INPUT

R6

Tr2

D5

R3

C6

Tr2

R3

DB

~+

~

R1

FA13842

1

AC INPUT

R6

R4

Tr1

C6

7

R7

+

6

R8

Fig. 12

DB

~+

~

R1

FA13842

13

D5

Fig. 13

+

C1

C2

PC1

D1

7

Tr3

T1

MOSFET

Rs

+

6

C8

+

C2

C1

R11

R10

D1

D6

MOSFET

R12

Rs

+

T1

C7

R9

ZD2

PC1

R3

R4

C6

Tr1

D5

Fig. 11

Fig. 14

Tr2

11

F A13842, 13843, 13844, 13845

4. Soft start

A soft-start circuit is shown in Fig. 15.
An aproximate soft-start time is determined with the following
calculation. This soft-start time is defined as the time the ISNS
terminal threshold voltage increases from 0V to 1V .

soft-start [ms]=4.3•C9[µF]

t

5. Suppression of noise at the current sensing
terminal

As each cycle current value is monitored in the current mode
control, there is the possibility that a malfunction will occur
even with a relatively low noise level. Therefore, it is
necessary to add a CR filter to reduce the level of noise at the
current sensing terminal. (See Fig. 16.)

6. ON/OFF circuit with an external signal

A typical ON/OFF circuit is shown in Fig. 17.
The output stage (OUT terminal) is enabled when the voltage
at the FB terminal is reduced to less than 2.0V and is disabled
when the FB terminal voltage increases to more than 3V .
Set the voltage of the FB terminal at a maximum of 5.3V in this
case.

D7

AC INPUT

R17
1MΩ

D8

C9

FA13842

8

4

2

1

DB

~+

~

+

ER AMP

Fig. 15

6

3

+

C1

C10

1mA

R18

REF

OSC

2R

1R

5

T1

MOSFET

Rs

ON/OFF signal

Tr6

R19

7

8

4

2

1

Fig. 16

30V

+

Fig. 17

REF

OSC

2R

ER AMP

1R

5

12

F A13842, 13843, 13844, 13845

+

+

R24

R25

C13

D1

C2

+

MOSFET

Rs

R

R1

2R

3

2

1

2.5V

C10

R18

C1

T1

D6

+

C7

+

R26

Is

Lu

-Ld

T

ON

TOFF

T

T

T

T

to

t1

Diverge

∆iL´

∆iL

7. Feedback circuit
7-1 A method that does not use an internal ER AMP

A method that does not use an internal ER AMP is shown in
Fig. 18. Connect the FB terminal to GND and connect an
optocoupler to the COMP terminal of the ER AMP output for
feedback control.
It is possible to obtain a precise power supply output voltage,
because the output voltage is monitored directly on the
secondary side.
Be sure to connect the FB terminal to the GND in this case.
There is the possibility of a malfunction occuring if the FB
terminal is open.

7-2 A method using an internal ER AMP

A method using an internal ER AMP is shown in Fig. 19.
In the flyback circuit, the bias winding voltages of the
transformer are proportional to the secondary winding voltage.
Therefore, V

CC is approximately proportional to the DC output

voltage on the secondary side.

CC is divided by resistors and monitored at the FB terminal to

V
control the output voltage.
This feedback circuit consists of a minimal number of external
components. However, regulation of the DC output voltage is
poor because the output voltage is not monitored directly.

8. Slope compensation

It is well known that a current mode converter that controls
peak current can oscillate irregularly when the inductor current
is continuous and the duty cycle is greater than 50%.
This irregular oscillation is called subharmonic oscillation.
The period of subharmonic oscillation is equal to the integral
number of the switching periods.
This phenomenon is shown in Fig. 20.
Lu indicates the positive slope of the inductor current. The
slope is determined by the input voltage and the primary
inductance value of the transformer. –Ld indicates the
negative slope, which is determined by the rate of energy
discharge to the secondary side.

PC2

C11

R19

C10

D6

T1

+

C1

MOSFET

1

2

2.5V

3

2R

+

R18

R

+

Rs

C7

+

R20

R21

PC2

R22

C12

R23

Fig. 18

Fig.19

Fig. 20 shows the inductor current waveform when T reveals
the oscillation period and Is reveals the control signal of the
peak inductor current. T

ON and TOFF vary even when having the

same T, Is, Lu and –Ld.
If it is assumed in Fig. 21 that the inductor current varies ∆ i
t0, the variation ∆ i
∆ i

L at t0. Thereafter, this inductor current variation gradually

’ of the inductor current at t1 is larger than

L

L at

increases, and as a result, subharmonic oscillation occurs.

Fig. 20

Fig. 21

13

F A13842, 13843, 13844, 13845

Fig. 22 illustrates a case when the inductor current variation

L’ at t1 is smaller than ∆ iL at t0. In this case, inductor current

∆ i
variations gradually converges and the inductor current
becomes stable.
It is necessary to apply slope compensation to the control
signals in order to prevent such subharmonic oscillations when
the inductor current is continuous and the duty cycle is greater
than 50%.

The waveform of the inductor current when slope
compensation is applied is shown in Fig. 23.
Slope compensation adds the negative slope of inclination
–Kc to the control signal of the inductor peak current.

’ shows the variation of the inductor current at t1 when

∆ i

L

slope compensation is not applied, and ∆ i

L’ s shows the

variation of the inductor current at t1 when slope compensation
is applied.
Thus, ∆ i

L’ can be changed by –Kc, and ∆ IL’ s becomes smaller

when –Kc is large. It is necessary to apply slope
compensation to satisfy the equation ∆ i

L ≥ ∆ iL’s, that is,

I –Kc I ≥ I –1/2 Ld I as the condition which achieves stable
operation.
Typical circuits are shown in Fig. 24 and 25.

∆iL

to t1

-Kc

∆iL

to

Ton

Lu

Converge

∆iL´

Fig. 22

Is

∆iL´

-Ld
∆iL´s

Compensated

T

t1

Fig. 23

Tr7

R27

Output

R25

R24

Tr7

R27

Output

R25

R24

RT

Vcc

VCC

7

30V

UVLO

UVLO

Vcc

ENB

5VREF

2.5V

OUTPUT
ENB

VREF

8
6

OUT

R18

Vin

MOSFET

CT

Rs

5

GND

C10

R26

COMP

RT/CT

FB

C13

ISNS

4
2

1
3

ER AMP

2R

1R 1V

OSC

S

Q

FF

R

QB

Fig. 24

GND

R18

C10

Vin

MOSFET

Rs

Vcc

VCC

7

RT

30V

UVLO

UVLO

Vcc

ENB

5VREF

2.5V

OUTPUT
ENB

VREF

8

OUT

6

CT

R26

COMP

RT/CT

FB

C13

ISNS

4
2

1

3

ER AMP

2R

1R

OSC

1V

S

Q

FF

R

QB

5

14

Fig. 25

VCC

ENB

2.5V

5VREF

ENB

OUTPUT

UVLO

OSC

30V

RT/CT

FB

COMP

ISNS

VREF

OUT

GND

2R

1R

1V

S

FF

Q

QB

R

VCC

UVLO

R19

C11

MOSFET

0~4A

DB

C1

C16

1000pF

2200pF

C10

100pF

C14

0.1µF

1kΩ

R18
1kΩ

8.2kΩ

R31

100Ω

560kΩ

R29

4.7kΩ

Rs

0.33Ω

R28

T1

C2

1kΩ

R20

1.2kΩ
R21

10kΩ

R22

560Ω

R32

2.2kΩ

R27

100kΩ

R30
33Ω

PC2

+

22µF

C7

C17

C18

+

+

+

+

FA13842

D10

ERA22-10

C15

470pF

R1

+

400V/220µF

0.022µF

3.3µH

0.1µF

1000µF

YG902C

L1

16V

ERA91-02

GND

C12
VR1

5k

IC

PC2

D11

ERA91-02

D1

AC80~264V

2SK2101

D9

ERA22-10

~

~

D6

7

8

6

5

1

4

2

3

R

T

C

T

4700µF 2

■ Application circuit

F A13842, 13843, 13844, 13845

Parts tolerances characteristics are not defined in the circuit design
sample shown above. When designing an actual circuit for a
product, you must determine parts tolerances and characteristics for
safe and economical operation.

15