Page 1
EDGE HIGH-PERFORMANCE PRODUCTS
SLEWADJA VCCA GNDA VEEA
SLEWADJB
DOUTA
DRIVER A
DRIVER B
DOUTB
DRVENA
DRVENA*
DHIA
DHIA*
DVH A
DVLA
DRVENB
DRVENB*
DHIB
DHIB*
DVH B
DVLB
BIAS
VCCB GNDB VEEB
EN
EN
Edge693
500 MHz Monolithic
Dual Pin Electronics Driver
Description
The Edge693 is a dual pin electronics driver solution
manufactured in a high-performance, complementary
bipolar process. In Automatic Test Equipment (ATE)
applications, the Edge693 offers two pin drivers suitable
for drive-only channels in memory testers, as well as for
bidirectional channels in memory, VLSI, and mixed- signal
test systems.
Each driver is completely isolated from the other. There
are separate data, enable, slew rate adjust, high and
low levels; as well as power supply inputs for each driver.
The driver output slew rate is adjustable from 3 V/ns to
1 V/ns, allowing the matching of edges from channel-tochannel, as well as slowing down edges for noise
sensitive applications.
Each driver is capable of driving 9 V signals over a 12 V
range, in addition to going into a high impedance state.
The Edge693 can generate ECL signals up to 500 MHz
and 3V signals in excess of 300 MHz.
Applications
• Memory Test Equipment
• Instrumentation
Functional Block Diagram
Combining two independent drivers into a 28-pin PLCC
package offers a highly integrated solution appropriate
where speed and density are at a premium.
Features
• >2.5 V/ns Driver Slew Rates
• Adjustable Driver Slew Rates
• HiZ Capability
• 12 V Output Range
• 9 V Output Swings
• 28-Pin PLCC with an Internal
Heat Spreader
Revision 1 / August 4, 2000
1
www.semtech.com
Page 2
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description
emaNniP#niPnoitpircseD
revirD
Edge693
*ANEVRD,ANEVRD
*BNEVRD,BNEVRD
*AIHD,AIHD
*BIHD,BIHD
ATUOD
BTUOD
AHVD,ALVD
BHVD,BLVD
APACHVD,APACLVD
BPACHVD,BPACLVD
AJDAWELS
BJDAWELS
SAIB1 roflevelsaiblanretniehtstesedonsihtotnitnerrucevitisopA.tupnigolanA
rewoP
BEEV,AEEV31,71.BrevirddnaArevirdrofylppusrewopevitageN
BCCV,ACCV11,91.BrevirddnaArevirdrofylppusrewopevitisoP
42,52
6,5
82,72
2,3
81
21
32,22
7,8
12,61
9,41
02
01
.Brevirddna
.Brevird
.BrevirddnaArevird
.stuptuoBrevirddnaArevirD
.tuptuo)ylevitcepserBdnaA(revirdehtta)LVDroHVD(
.etatsecnadepmihgihanidecalproegatlovagnicrofsi)ylevitcepser
BdnaA(revirdehtrehtehwenimretedtahtsniptupnilaitnereffidegatlovediW
slevelelbammargorpowtfoenoecroftahtsniptupnilaitnereffidegatlovediW
ArevirdrofsleveltuptuohgihdnawolehtmargorptahtstupnigolanadeereffuB
.niphcaeotdetcennocebdluohsdnuorgotroticapacFµ10.0.snipgolanA
dnaArevirdfosetarwelsllafdnaesirehttsujdatahtstupnitnerrucgolanA
BDNG,ADNG4,62.BrevirddnaArevirdrofdnuorgeciveD
sniPtseT
EDOIDLAMREHT51 .erutarepmetnoitcnujeidehtkcartotdesutuptuorotinomlamrehT
2 2000 Semtech Corp.
www.semtech.com
Page 3
EDGE HIGH-PERFORMANCE PRODUCTS
PIN Description (continued)
DRVENA
DRVENA*
25
24
28-Pin PLCC
DVHA
DVLA
DVHCAPA
23
22
21
SLEWADJA
20
Edge693
VCCA
19
GNDA
DHIA
DHIA*
BIAS
DHIB*
DHIB
GNDB
26
27
28
1
2
3
4
5
DRVENB
6
DRVENB*
7
DVHB
8
DVLB
9
10
DVHCAPB
SLEWADJB
18
17
16
15
14
13
12
11
VCCB
DOUTA
VEEA
DVLCAPA
THERMAL DIODE
DVLCAPB
VEEB
DOUTB
2000 Semtech Corp.
3
www.semtech.com
Page 4
EDGE HIGH-PERFORMANCE PRODUCTS
Circuit Description
Edge693
Introduction
The driver circuit will force the DOUT output to one of
three states:
1. DVH (driver high voltage level)
2. DVL (driver low voltage level)
3. High Impedance (Hi Z).
Both driver digital control inputs (DHI/DHI*, DRVEN/
DRVEN*) are wide-voltage differential inputs capable of
receiving ECL, TTL, and CMOS signals. Single-ended
operation is achievable by generating the proper
threshold levels for the inverting inputs.
Drive Enable
The drive enable (DRVEN/DRVEN*) inputs control
whether the driver is forcing a voltage or is placed in a
high-impedance state. If DRVEN is more positive than
DRVEN*, the output will force either DVL or DVH,
depending on the driver data inputs. When DRVEN is
more negative than DRVEN*, the output is set to highimpedance, independent of the driver data inputs.
Driver Levels
DVH and DVL are high-input impedance voltage controlled
inputs that establish the driver logical high and low levels
respectively.
Slew Rate Adjustment
The driver rising and falling slew rates are adjustable
from 3.0 V/ns to 1 V/ns. The SLEWADJ signals are
current controlled inputs that var y the rising and falling
edge slew rates. An input current of 2.0 mA translates
to a slew rate of 3.0 V/ns. An input current of 0.8 mA
forces a 1 V/ns edge (see Figure 1).
2.5
Slew Rate (V/ns)
1.0
Driver Data
The driver data inputs (DHI/DHI*) determine whether
the driver output is high or low. If DHI is more positive
than DHI*, the output will force DVH when the driver is
enabled. If DHI is more negative than DHI*, the output
will force DVL when the driver is enabled.
T able 1 summarizes the functionality of the driver enable
and driver data pins.
*NEVRD,NEVRD*IHD,IHDTUOD
*NEVRD>NEVRD*IHD>IHDHVD
*NEVRD>NEVRD*IHD<IHDLVD
*NEVRD<NEVRDXZiH
Table 1. DRVEN and DHI Pin Functionality
0.8 2.0
SLEWADJ (mA)
(BIAS = 1.5 mA)
Figure 1. Slew Rate Control
Notice that the driver A slew rate and driver B slew rate
are independent. However, the rising and falling edge
slew rates on each driver track each other and are not
independent (see Figure 2).
a
b
a. SLEWADJ = 2.0 mA, Rising SR = Falling SR = 2.5V/ns.
b. SLEWADJ = 0.8 mA, Rising SR = Falling SR = 1.0V/ns.
Figure 2. Output Slew Rate Adjustability
4 2000 Semtech Corp.
www.semtech.com
Page 5
EDGE HIGH-PERFORMANCE PRODUCTS
.01 µF .01 µF
DVLCAP DVHCAP
Edge693
Circuit Description (continued)
Edge693
For system level flexibility , the SLEWADJ input is designed
to allow a voltage DAC, a current DAC, or a resistor to a
fixed voltage as possible slew rate control mechanisms
(see Figure 3).
SLEWADJ
1.5KΩ
Rise/Fall
Adjust Current
Figure 3. SLEWADJ Inputs
Driver Bias
The BIAS pin is an analog current input that requires a
1.2 mA fixed reference current for the driver. Several
circuit configurations are usable to satisfy this
requirement, the most simple being a fixed resistor to a
fixed power supply , typically VCC (see Figure 4). Looking
into the BIAS node shows a .7 V voltage source with a
1.5 KW impedance, so the equation to select the fixed
resistor is:
(VCC – .7) / (R + 1.5) = 1.2 mA
DVLCAP / DVHCAP
These two analog nodes are brought out to better
stabilize the high and low driver levels. Much like placing
decoupling capacitors on the DVL and DVH input pins,
the DVLCAP and DVHCAP pins require a fixed .01 µF
chip capacitor (with good high frequency characteristics)
to ground (see Figure 5). A tight layout with minimum
etch is recommended.
Figure 5. DVLCAP and DVHCAP
Thermal Monitor
The Edge693 includes an on-chip thermal monitor
accessible through the THERMAL DIODE pin. This node
connects to 5 diodes in series to VEE (see Figure 6) and
may be used to accurately measure the junction
temperature at any time.
Thermal Diode
Bias Current
Alternatively, a current DAC could be used to either
program the BIAS current or to perform subtle
adjustments in the fixed value.
VCC
1.2 mA
Figure 4. Bias Current Generation
2000 Semtech Corp.
Edge693
R
Bias
Temperature coefficient = –10 mV/
VEE
Figure 6. Thermal Diode String
C
˚
A bias current of 100 µA is injected into this node, and
the measured voltage corresponds to a specific junction
temperature with the following equation:
T
J(˚C)
= {(V
5
THERMAL DIODE
– VEE) / 5 – .7} / (–.00208).
www.semtech.com
Page 6
EDGE HIGH-PERFORMANCE PRODUCTS
Application Information
Thermal Information
retemaraPlobmySniMpyTxaMstinU
Edge693
ecnatsiseRlamrehT
esaCotnoitcnuJ
riAotnoitcnuJ
riAllitS
MPFL05
MPFL004
θ CJ
θ AJ
θ AJ
θ AJ
31
94
63
62
o
W/C
o
W/C
o
W/C
o
W/C
Thermal equilibrium is established by applying power for at least 2 minutes while maintaining a transverse
air flow of 400 linear feet per minute over the device mounted either in the test socket or on the printed
circuit board. Thermal resistance measurements are taken with device soldered to PCB.
6 2000 Semtech Corp.
www.semtech.com
Page 7
EDGE HIGH-PERFORMANCE PRODUCTS
Package Information
PIN Descriptions
0.045 x 45
[1.143]
0.485 – 0.495
[12.32 – 12.57]
SQ
0.450 – 0.456
[11.43 – 11.58]
Pin #1
o
SQ
Pin #1 Ident
Edge693
28 Pin PLCC Package
θJA = 75 to 80˚C / W
Pin #1
0.300 REF
[7.62]
0.050
[1.27]
TYP
0.165 – 0.180
.045 x 45
o
[4.19 – 4.57]
[1.14]
0.026 – 0.032
[0.661 – 0.812]
0.390 – 0430
[9.91 – 10.92]
0.026 – 0.032
[0.661 – 0.812]
0.090 – 0.120
[2.29 – 3.04]
Notes: (unless otherwise specified)
1. Dimensions are in inches [millimeters].
2. Tolerances are: .XXX ± 0.005 [0.127].
3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers.
2000 Semtech Corp.
7
www.semtech.com
Page 8
EDGE HIGH-PERFORMANCE PRODUCTS
Recommended Operating Conditions
retemaraPlobmySniMpyTxaMstinU
ylppuSrewoPevitisoPCCV5.015.21V
ylppuSrewoPevitageNEEV0.8-2.4-V
ylppuSgolanAlatoTEEV-CCV7.410.91V
stupnIgolanA
leveLhgiHrevirD
leveLwoLrevirD
saiBrevirD
tsujdAetaRwelSArevirD
tsujdAetaRwelSBrevirD
HVD
LVD
SAIB
AJDAWELS
BJDAWELS
Edge693
5.3+EEV
9.2+EEV
5.1
8.0
8.0
9.2-CCV
5.3-CCV
V
V
Am
5.2
5.2
Am
Am
gnitarepOtneibmA
erutarepmeT
erutarepmeTnoitcnuJJT52+521+
Absolute Maximum Ratings
retemaraPlobmySniMpyTxaMstinU
)DNGotevitaleR(CCVCCV0 0.41+V
DNGotevitaleR(EEVEEV0.01-0V
ylppuSrewoPlatoTEEV-CCV0.91+V
segatloVtupnIlatigiD*NEVRD,NEVRD
segatloVgolanAHVD,LVD,TUODEEVCCVV
stnerruCtupnIgolanA
saiBrevirD
tsujdAetaRwelS
)citatS(tnerruCtuptuOrevirDTUOD05-05+
erutarepmeTgnitarepOtneibmAAT55-521+
erutarepmeTegarotSST56-051+
erutarepmeTnoitcnuJJT051+
erutarepmeTgniredloS
)nipmorf"4/1,sdnoces5(
segatloVtupnIlatigiDlaitnereffiD*NEVRD-NEVRD
AT0 07+
EEV0.7+V
*IHD,IHD
5.5-5.5+V
*IHD-IHD
SAIB
AJDAWELS
BJDAWELS
LOST062
0
0
0
o
C
o
C
5.2
0.3
0.3
Am
Am
Am
Am
o
C
o
C
o
C
o
C
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only, and functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
8 2000 Semtech Corp.
www.semtech.com
Page 9
EDGE HIGH-PERFORMANCE PRODUCTS
DC Characteristics
retemaraPlobmySniMpyTxaMstinU
tnerruCtupnIgolanA
LVD,HVD
tupnIsaiB
stupnItnemtsujdA
ecnatsiseRtupnIJDAWELS
egnaRtnerruCJDAWELS9.0
tiucriCrevirD
egnaRegatloVtuptuO
gniwSegatloVtuptuO
:tnerruCtuptuOcitatSxaM
V2-=>TUOD
V2-<TUOD
tnerruCtuptuOcimanyDxaM
)1etoN(tnerruCegakaeLTUOD
V2-=>TUOD
V2-<TUOD
NII
SAIB
KAELI
KAELI
Edge693
05-
5.1
5.1
TUODV
gniwsV
TUODI
TUODI
5.3+EEV
52.0
5302-
001-
13-
05+Aµ
0.2
5.3-CCV
0.9
53+
53+
001+
1
3
Am
KΩ
Am
V
V
Am
Am
Am
Aµ
Aµ
ycaruccAhgiHrevirD
)1etoN(tesffO
)2etoN(niaG
)3etoN(ytiraeniL
ycaruccAwoLrevirD
)1etoN(tesffO
)2etoN(niaG
)3etoN(ytiraeniL
erutarepmeTegatloVtesffO
tneiciffeoC
ecnadepmItuptuOrevirDTUOZ0.10.35.4
RRSPrevirDRRSP02Bd
stupnIlatigiD
*IHD,IHD,*NEVRD,NEVRD
tnerruCtupnI
egnaRegatloVtupnI
gniwStupnIlaitnereffiD
tnerruCylppuSrewoP
ylppuSevitisoP
ylppuSevitageN
∆ /HVD ∆ TUOD
∆ /HVD ∆ TUOD
TUOD-HVD
TUOD-LVD
TUOD-HVD
TUOD-LVD
CTTUOD1±/Vm
NII
GNRV
FFIDV
CCI
EEI061-
095951-
575951-
009-
0.2-
52.0
56-
99.
1
05-
99.
1
041
041-
04-
0.1
51+
52-
0.1
51+
009+
5.5+
0.4+
061
Vm
V/V
Vm
Vm
V/V
Vm
o
C
Ω
Aµ
V
V
Am
Am
Note 1: The offset voltage is defined as the difference betw een the measured driver output at DOUT under no
load conditions versus the programmed voltage (DVH or DVL) when forced to –1.0 V.
Note 2: The driver gain is defined as the change in driver output voltage (DOUT) divided by the change in
programmed input voltage (DVH or DVL). Measurements are tak en at –1.0 V and +4.0 V programmed
inputs with the output under no-load conditions.
Note 3: Linearity error is defined as the maximum deviation between the theoretical driver output voltage
(predicted by the straight line determined by the offset and gain) and the actual measured output
voltage under no load conditions.
2000 Semtech Corp.
9
www.semtech.com
Page 10
EDGE HIGH-PERFORMANCE PRODUCTS
AC Characteristics
retemaraPlobmySniMpyTxaMstinU
tiucriCrevirD
)1etoN(TUODotIHDmorfdpTdpT5.1sn
)2etoN(ZiHTUODotNEVRDmorfdpT 5.1sn
)2etoN(evitcATUODotNEVRDmorfdpT 5.1sn
)3etoN(semiTllaF/esiRTUOD
%08-%02,LCE
%09-%01,V3
%09-%01,V5
%09-%01,V8
JDAFroJDARotytivitisneSetaRwelSJDAI/RS839.Am/sn/V
)4etoN(etaRelggoTxamF005zHM
Edge693
fT/rT
fT/rT
fT/rT
fT/rT
6.0
2.1
8.1
57.2
sn
sn
sn
sn
ZiHniecnaticapaCtuptuOtuoC0.2Fp
)5etoN(htdiWesluPmuminiM
LCE
V3
V5
V7
0.1
0.2
7.2
5.3
sn
sn
sn
sn
The specified limits shown can be met only after thermal equilibrium has been established. Thermal
equilibrium is established by applying power for at least two minutes while maintaining the normal operating
environment. (IBIAS = 1.2 mA, SLEWADJ = 2.5 mA)
Note 1: Tpd is measured from crossover point of DHI and DHI* to the 50% point in the output. DVL
equals 0 V and DVH equals +3 V.
Note 2: Specification condition: DVL equals -1 V and DVH equals +1 V. Output is terminated to GND by
100 Ω. Tpd is measured from the crossover point of DRVEN and DRVEN* to the point where a
10-percent change in output voltage occurs.
Note 3: The driver load is an 18 cm 50Ω transmission line terminated with 1KΩ in parallel with 3 pF.
Note 4: ECL output conditions. Signal reaches 100% of programmed value.
Note 5: The output pulse width is measured at the 50-percent points. Output reaches 100% of programmed
value.
10 2000 Semtech Corp.
www.semtech.com
Page 11
EDGE HIGH-PERFORMANCE PRODUCTS
Ordering Information
rebmuNledoMegakcaP
JHA396ECCLPniP-82
JHA396MVEeludoMnoitaulavE396egdE
Edge693
)redaerpStaeHlanretnIhtiw(
Contact Information
2000 Semtech Corp.
Semtech Corporation
Edge High-Performance Division
10021 Willow Creek Rd., San Diego, CA 92131
Phone: (858)695-1808 FAX (858)695-2633
11
www.semtech.com
Loading...