Datasheet ES4428, ES4427 Datasheet (ESS)

ES4428/ES4427

Web/DVD Set-Top Box Solution

Product Brief

DESCRIPTION

The ES4428/ES4427 Web/DVD Internet set-top box chipset
seamlessly combines both Web browser technology and DVD
technology into a h igh ly i ntegrated, low-cost solution for th e nex t
generation of Internet set-top boxes for home use.

The ES4428, which is based on ESS’s Programmable
Multimedia Processor (PMP) device architecture, includes a
programmable internal RISC processor core that makes it
adaptable for use in embedded systems applications such as
set-top boxes. The ES4427 companion chip supplies proper
video sync capabilities and performs NTSC- and PAL-based
video encoding an d decoding as ne cessary to provide bro adcast
quality video to the television screen.

The ES4428 DVD processor integrates MPEG-based audio and
video data stream decoding for DVD/VCD/SuperVCD playback,
DVD system navigation and Dolby AC-3 decoding into a single
device. The ES4428 demuxes the incoming DVD audio and
video data streams from the DVD loader using its glueless 8/16­bit parallel interface, whic h is hardware-compati ble with many
DVD loaders. The ES4428 also supports both 8- and 16-bit
Flash/Read-Only Me mory (ROM) an d 8- and 16-bit Synchronous
DRAM (SDRAM) memory I/O operations.

The ES4428 controls data I/O transactions to and from the
ES4427 companion chip through its 8-bit Device Serial Connect
(DSC) parallel bus interface. The ES4428 also provides a 16-bit
wide hardware interface with V.90-compatible modem
subsystems incorporated into the set-top box design.

The ES4427 incorporates a multi-standard TV encoder that
supports both the NTSC and PAL formats and CCIR-601 non­square operations. Two microphone ADCs and PLL clock
synthesizers are incorporated in the ES4427 device architecture.
The ES4427 includes an I/O-mapped auxiliary expansion port
that interfaces with the ES4428. Four pins of the port can be
configured as edge-triggered interrupts, supporting critical
functions, such as handling remote control and modem interrupt
requests, DVD/V CD loa der res et s and mode m boa rd rese ts.

Command and register ac cesses are issued throu gh the
DSC interface from the ES4428 DVD processor to the
ES4427 through the devi ce serial communication (DSC)
interface for accessing the internal registers of the
ES4427. The DSC interface port is comprised of three
interface signals, the strobe (DSC_S), data (DSC_D), and
clock (DSC_C).

The DSC port is selected when the DSC strobe goes high
and latches the data at th e risi ng edge of the cloc k. E ach
16-bit DSC transfer is co mprised of an address fo llowed
by data.

The ES4428 is available in an industry-standard 208-pin Plastic
Quad Flat Pack (PQFP ) package, while the ES4427 is available
in an industry-standard 100-pin PQFP package.

ES4428 FEATURES

• On-chip hardware interface with V.90 data/fax/voice modem

subsystem implemented

• 640 x 480 NTSC and 640 x 576 PAL television video formats

supported

• Configurable for browser/DVD applications

• Hardware support for infrared remote control and/or wireless

keyboard

• On-chip MPEG audio/video decoder and system parser

• On-chip on-screen display (OSD) controller supports 4-bit

blending.

• On-chip subpicture unit (SPU) decoder supports karaoke lyric,

subtitle and closed captioning functions.

• VideoCD 1.1 and 2.0, Interactive 3.0, Super VCD and Audio CD

compatibility available with Video CD / Super VCD player
configuration

• VideoCD 1.1 and 2.0, Interactive 3.0, Super VCD, Audio CD

and MP3 compatibility available with Super VCD / DVD player
configuration

• DTS audio decoding supported

• Programmable multimedia processor architecture

• ISO/IEC 13818-2 MPEG-2 compliant

• ISO/IEC 11172 MPEG-1 compliant

ES4427 FEATURES

• 8-bit DSC parallel bus interface generates edge-triggered

interupts for data read/write interfacing with ES4428

• Dual microphone and vocal assist hardware support provided

• PLL clock synthesizer based on 27 MHz crystal input generates

required clocks for video encoder, video DACs and video
processor

SOFTWARE SUPPORT

• Software stack support for the POP3, SMTP and SNMP Internet

e-mail protocols defined by RFC 821, RFC 1157and RFC 2449

• Software stack support provided for the HTTP Web browsing

protocol defined by RFC 1945, RFC 2068 and RFC 2616

• Software stack support provided for the TCP/IP Internet

protocols defined by RFC 791 and RFC 793

• Software stack support provided for RTP payload format for

MPEG-1/2 and H.261 video streaming protocols defined by
RFC 2032, RFC 2038 and RFC 2250

• Software support for HTML 1.0, 2.0 and 3.2, *.aiff, *.au and

*.wav audio file formats and *.gif, *.jpg and *.xbm graphic file
formats, JavaScript 1.1, SSL 2.0 and SSL 3.0

• Character generation and software support for English,

Big 5/GB Chinese and Japanese fonts

• Software support for infrared remote control and wireless

keyboard

ESS Technology, Inc. SAM0358-052201 1

ES4428 PINOUT

Figure 1 shows the ES4428 device pinout.

NC

NC

VSS

VCC

NC

VPP
AUX0
AUX1
AUX2

VSS

VCC
AUX3
AUX4
AUX5
AUX6
AUX7
LOE#

VSS

VCC

LCS0#
LCS1#
LCS2#
LCS3#

VSS

LD0
LD1
LD2
LD3
LD4

VCC

VSS

LD5
LD6
LD7
LD8

LD9
LD10
LD11

VSS

VCC
LD12
LD13
LD14
LD15

LWRLL#

LWRHL#

VSS

VCC

NC

NC
LA0
LA1
LA2
LA3

VSS

NCNCNC

NC

153

154

155

156

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208

1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233343536373839404142434445464748495051

NC

152

151

150

149

VCC

148

VSS

147

NC

146

NCNCNCNCHD15

144

145

143

HD4

HD5

HD6

HD2

VSS

129

128

127

126

HD3

125

124

HD1

123

HD0

122

VCC

121

142

141

HD14

140

VCC

139

VSS

138

HD13

137

HD12

136

HD11

135

HD10

134

HD9

133

HD8

132

HD7

131

VCC

130

ES4428

208-Pin PQFP Package

VSS

120

HSYNC#

119

VSYNC#

118

PCLKQSCN

117

PCLK2XSCN

116

YUV7

115

ES4428/ES4427 PRODUCT BRIEF

YUV6

YUV5

VSS

VCC

YUV4

YUV3

YUV2

YUV1

YUV0

DCLK

105

106

107

108

109

110

111

112

113

114

104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

52

53

VCC
VSS
DSCK
DQM
DCS0#
VCC
VSS
DCS1#
DB15
DB14
DB13
DB12
VCC
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VCC
DRAS2#/DBANKSEL0
DRAS1#/DBANKSEL1
DRAS0#
DWE#
DOE#/DSCK_EN
DCAS#
VCC
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VCC
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0

NC

NC

NC

LA6

LA7

LA8

LA4

VCC

LA9

LA5

VSS

VCC

LA11

LA10

LA12

VSS

LA13

VCC

LA14

LA15

LA16

LA17

LA18

LA19

VSS

VCC

LA21

LA20

TDMDR

RESET#

TDMCLK

TDMDX/RSEL

VSS

TDMFS

VCC

TDMTSC#

TWS/SEL_PLL1

SEL_PLL2

TSD/SEL_PLL0

MCLK

NC

VSS

VCC

TBCK

XIN

RSD

RWS

RBCK

VSS

VCC

XOUT

APLLCAP

Figure 1 ES4428 Device Pinout

2 SAM0358-052201 ESS Technology, Inc.

ES4428 PIN DESCRIPTION

Table 1 lists the pin descriptions for the ES4428.

Table 1 ES4428 Pin Descriptions

Name Number I/O Definition

1, 9, 18, 27, 35, 44, 51,

59, 68, 75, 83, 92, 99,

VCC

VSS

LA[21:0] 23:19,16:10,7:2,207:204 O Device address output.
RESET# 24 I Reset.
TDMDX

RSEL

104, 1 11, 121, 130, 139,

148, 157, 164, 172, 183,

193, 201

8, 17, 26, 34, 43, 52, 6 0,

67, 76, 84, 91, 98, 103,
1 12, 1 20, 12 9, 138, 14 7,
156, 163, 171, 177, 184,

192, 200, 208

25

I

3.3V power supply.

I

Ground.

O TDM transmit data output.

I ROM Select.

RSEL Selection

0 16-bit ROM
1 8-bit ROM

ES4428/ES4427 PRODUCT BRIEF

TDMDR 28 I TDM rec eive data inpu t.
TDMCLK 29 I TDM clock input.
TDMFS 30 I TDM fram e sync.
TDMTSC# 31 O TDM output enable.
TWS

SEL_PLL1

TSD 33 O Audio transmit serial data output.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL1 pin 32.
SEL_PLL2 36 I Refer to the description and matrix for SEL_PLL1 pin 32.

NC

MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 I/O Audio transmit bit clock output.
RSD 45 I Audio receive serial data input.
RWS 46 I Audio receive frame sync input.
RBCK 47 I Audio receive bit clock input.
APLLCAP 48 I Analog PLL capacitor input.

37, 38, 41, 42, 146:142,

155:149, 158, 203:202

32

O Audio transmit frame sync output.

System and DSCK output clock frequency selection at reset time. The matrix
below lists the available clock frequencies and their respective PLL bit
settings..

SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Output

0 0 0 VCO doesn’t work.
00127 MHz
0 1 0 Bypass mode
01154 MHz
1 0 0 121.5 MHz
10181 MHz
1 1 0 94.5 MHz
1 1 1 108 MHz

—

No connect. Leave open.

3 SAM0358-052201 ESS Technology, Inc.

ES4428/ES4427 PRODUCT BRIEF

Table 1 ES4428 Pin Descriptions (Continued)

Name Number I/O Definition

XIN 49 I Crystal input.
XOUT 50 O Crystal output.
DMA[11:0] 66:61, 58:53 O DRAM address bus [11:0].
DCAS# 69 O DRAM column address strobe.
DOE# 70 O DRAM output enable.
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable.
DRAS0# 72 O DRAM row address strobe 0.
DRAS1# 73 O DRAM row address strobe 1 (active-low).
DBANKSEL1 O DRAM address bus select 1 output. Only active in 64Mb SDRAM mode.
DRAS2# 74 O DRAM row address strobe 2 output.
DBANKSEL0 O DRAM address bus select 0 output. Only active in 64Mb SDRAM mode.
DB[15:0] 96:93, 90:85, 82:77 I/O DRAM data bus [15:0].
DCS[1:0]# 97, 100 O SDRAM chip select [1:0].
DQM 101 O Data input/output mask.
DSCK 102 O Output clock to SDRAM.
DCLK 105 I 27 MHz clock input to PLL.
YUV[7:0] 115:113, 110:106 O 8-bit YUV output.
PCLK2XSCN 116 I/O 2X pixel clock.
PCLKQSCN 117 I/O Pixel clock.
VSYNC# 118 I/O Vertical sync.
HSYNC# 1 19 I/O Horizontal sy nc .
HD[15:0] 141:140, 137:131,

128:122
VPP 159 I 5.0V power supply.
AUX[7:0] 169:165,162:160 I/O Auxiliary ports.
LOE# 170 O EPROM device output enable.
LCS[3:0]# 176:173 O EPROM chip select [3:0].
LD[15:0] 197:194, 191:185,

182:178
LWRLL# 198 O Device write enable.
LWRHL# 199 O Device writ e enabl e (acti ve-l ow).

I/O Host data bus

I/O EPROM device data bus.

4 SAM0358-052201 ESS Technology, Inc.

ES4427 PINOUT

Figure 2 shows the ES4427 device pinout.

VCC

PCLK

2XPCLK

ES4428/ES4427 PRODUCT BRIEF

YDAC

VSSAV

VSSAV

VDAC

ACAP

VCC

AUX6

AUX5

AUX4

AUX3

XOUT

VSS

VCC

XIN

VSSNCVSS

VCCAV

VCCAV

COMP

VSSAV

VSSAV

CDAC

VSSAA

VREF

VREFM

RSET

80

DSC_D7
HSYN_B
DSC_D6
VSYN_B
DSC_D5

YUV7
YUV6
YUV5
YUV4

VCC
VSS

YUV3

DSC_D4

YUV2

DSC_D3

YUV1

DSC_D2

YUV0

DSC_D1

VSS

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

NC

VSS

ES4427 PIN DESCRIPTION

51

MIC1

50

MIC2

49

AOL+

48

AOL-

47

AOR-

46

AOR+

45

VCCAA

44

VREFP

43

VCM

42

VSSAA

ES4427

100-pin PQFP

NC

NC

VCC

AUX0

DSC_C

DSC_D0

AUX2

AUX1

DSC_S

DCLK/EXT_CLK

VCC

AUX7

MCLK

MUTE

RESET_B

TSD

AUX9

AUX8

TBCK

TWS/SPLL_OUT

VSS

VSS

RSTOUT_B

RWS/SEL_PLL1

41

AUX15/IR

40

AUX14

39

AUX13

38

RBCK/SER_IN

37

AUX12/C2PO

36

AUX11/IRQ

35

AUX10

34
33

RSD/SEL_PLL0

32

VCC

31

VSS

30

NC

NC

NC

NC

Figure 2 ES4427 Device Pinout

Table 2 lists the pin descriptions for the ES4427.

Table 2 ES4427 Pin Descriptions

Name Number I/O Definition

VSS

1, 25:26, 31, 72,

75, 77, 91, 100
NC 2:4, 27:30, 76 No connect.
VCC 5, 16, 32, 66, 73, 78, 90 I 5.0V power supply.
DSC_C 6 I Clock for programming to access internal registers.
AUX0 7 I/O General purpose I/O.

DSC_D[7:0]

8, 81, 83, 85,

93, 95, 97, 99
AUX1 9 I/O General purpose I/O.
DSC_S 10 I Strobe for programming to access internal registers.
AUX2 11 I/O General purpose I/O.
DCLK 12 O MPEG decoder output clock.
EXT_CLK I EXT_CLK is the external clock EXT_CLK is an input during bypass PLL mode.
RESET# 13 I Reset.
AUX7 14 I/O General purpose I/O.
MUTE 15 O Audio mute.
MCLK 17 I Audio master cloc k.

I Ground.

I/O Data for programming to access internal registers.

5 SAM0358-052201 ESS Technology, Inc.

ES4428/ES4427 PRODUCT BRIEF

Table 2 ES4427 Pin Descriptions (Continued)

Name Number I/O Definition

AUX8 18 I/O General purpose I/O.
TWS 19 I Transmit audio frame sync.
SPLL_OUT O SPLL_OUT is the select PLL output.
AUX9 20 I/O General purpose I/O.
TSD 21 I Transmit audio data input.
TBCK 22 I Transmit audio bit clock.
RWS

SEL_PLL1

RSTOUT# 24 O Reset output.
RSD
SEL_PLL0 I Refer to the description and matrix for SEL_PLL1 pin 23.
AUX10 34 I/O General purpose I/O.
AUX11 35 I/O Interrupt output to ES4428.
AUX12 36 I/O CD loader C2PO.
RBCK

SER_IN
AUX13 38 I/O General purpose I/O.

AUX14 39 I/O Interrupt input from Modem DSP.
AUX15 40 I/O IR interrupt Input.
VSSAA 41,51 I Audio analog ground.

VCM 42

VREFP
VCCAA 44 I 5.0V analog audio power supply.

AOR+,
AOR-

AOL-, AOL+ 47, 48 O Left channel output.
MIC2 49 I Microphone input 2.
MIC1 50 I Microphone input 1.

VREF 52

VREFM
RSET 54 I Full scale DAC current adjustment.

COMP 55 I Compensation pin.
VSSAV 56:57, 62:63 I Video analog ground
CDAC 58 O Modulated chrominance output.
VCCAV 59, 60 I Video VCC, 5 V

23

33

37

43 I DAC and ADC maximum reference. Bypass to VCMR with 10 µF in parallel with 0.1

45, 46 O

53 I DAC and ADC minimum reference. Bypass to VCMR with 10 µF in parallel

O Receive audio frame sync.

I System and DSCK output clock frequency selection at reset time. The matrix

below lists the available clock frequencies and their respective PLL bit settings..

SEL_PLL1 SEL_PLL0 DCLK

0 0 Bypass PLL (input mode)
0 1 27 MHz (output mode) Default
1 0 32.4 MHz (output mode)
1 1 40.5 MHz (output mode)

O Receive audio data input.

O Receive audio bit output clock.

I SER_IN is the serial input DSC mode. 1 = Serial DSC mode. 0 = Parallel DSC

mode.

I ADC Common Mo de Reference (CMR) buf fer outp ut. CMR is approxim ately 2.25

V. Bypass to analog ground with 47 µF electrolytic in parallel with 0.1 µF.

µF.

Right channel output.

I Internal resistor divider generates Common Mode Reference (CMR) voltage.

Bypass to analog ground with 0.1 µF.

with 0.1 µF.

6 SAM0358-052201 ESS Technology, Inc.

Table 2 ES4427 Pin Descriptions (Continued)

Name Number I/O Definition

YDAC 61 O Y luminance data bus for screen video port.
VDAC 64 O Composite video output.
ACAP 65 I Audio CAP
AUX6 67 I/O General purpose I/O.
AUX5 68 I/O General purpose I/O.
AUX4 69 I/O Modem DSP reset.
AUX3 70 I/O CD loader reset.
XOUT 71 O Crystal output.
XIN 74 I 27 MHz crystal input.
PCLK 79 I/O 13.5 MHz pixel clock.
2XPCLK 80 I/O 27 MHz doubled pixel clock.
HSYNC# 82 O Horizontal sync.
VSYNC# 84 O Vertical sync.
YUV[7:0] 86:89, 92, 94, 96, 98 I YUV data bus for screen video port.

SYSTEM BLOCK DIAGRAM

Figure 3 shows a sample system block diagram of an
ESS-based Web/DVD system.

ES4428/ES4427 PRODUCT BRIEF

Phone

Line

Remote

Control/

Wireless

Keyboard

ES2898

Modem DSP

ES2828

MC’97 AFE

Front Panel

Interface

SDRAM

ROM or

Flash ROM

ES4428

Web/DVD

Processor

DVD

Drive

Figure 3 ES4428/ES4427 System Block Diagram

Video

Encoder

Audio

DAC

ES4427

Companion Chip

Smart Card

(ISO 7816-3)

7 SAM0358-052201 ESS Technology, Inc.

MECHANICAL DIMENSIONS, ES4428

Figure 4 shows the mechanical dimensions of the ES4428.

D

D1

156

D3

ES4428/ES4427 PRODUCT BRIEF

105

Index
Pin 1

A

157

104

Note:

1. All dimensions are in inches (millimeters).

2. Actual package used has millimeter native

dimensions – take care with rounding from metric
to imperial.

Symbol Min Nom Max

A – – 0.165

EE1E3

A1 0.010 (0.25) – –
A2 0.130 (3.30) 0.134 (3.40) 0.138 (3.50)

B 0.007 (0.18) 0.009 (0.23) 0.011 (0.28)
C 0.005 (0.12) 0.006 (0.16) 0.008 (0.20)
D 1.195 (30.35) 1.205 (30.60) 1.215 (30.85)

D1 1.098 (27.90) 1.102 (28.00) 1.106 (28.10)

208

152

e

53

see detail

D3 1.004 (25.50) REF

e 0.0197 (0.50) BASIC

E 1.195 (30.35) 1.205 (30.60) 1.215 (30.85)

E1 1.098 (27.90) 1.102 (28.00) 1.106 (28.10)
E3 1.004 (25.50) REF

L 0.016 (0.40) 0.020 (0.50) 0.024 (0.60)

φ 0 i 2.5 i 5.0 i

A2

A1

B

φ

C

L

Figure 4 ES4428 Mechanical Dimensions

8 SAM0358-052201 ESS Technology, Inc.

ES4428/ES4427 PRODUCT BRIEF

MECHANICAL DIMENSIONS, ES4427

Figure 5 shows the mechanical dimensions of the ES4427.

D

D1

ES4427

E1E

100-Pin PQFP

1

A2 A1

e e1

L

b

L1

Symbol Description

Min Nom Max

Millimeters

D Lead to lead, X-axis 23.65 23.90 24.15

D1 Package’s outside, X-axis 19.90 20.00 20.10

E Lead to lead, Y-axis 17.65 17.90 18.15
E1 Package’s outside, Y-axis 13.90 14.00 14.10
A1 Board standoff 0.10 0.25 0.36
A2 Package thickness 2.57 2.71 2.87

b Lead width 0.20 0.30 0.40

e Lead pitch -0.65-

e1 Lead gap 0.24 - -

L Foot length 0.65 0.80 0.95
L1 Lead length 1.88 1.95 2.02

- Foot angle 0° - 7°

- Coplanarity - - 0.102

- Leads in X-axis -30-

- Leads in Y-axis -20-

- To tal leads -100-

- Package type -PQFP-

Figure 5 ES4427 Mechanical Dimensions

ESS Technology, Inc. SAM0358-052201 9

ORDERING INFORMATION

Part Number Description Package

ES4428 Web DVD Processor 208-pin PQFP
ES4427 Companion Chip 100-pin PQF P

ES4428/ES4427 PRODUCT BRIEF

No part of this publication may be reproduced, stored in a
retrieval system, transmitted, or translated in any form or
by any means, electronic, mechanical, ma nual, optical , or
otherwise, without the prior written permission of ESS
Technology, Inc.

ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.

All specifications are subject to change without prior
notice.

ESS Technology, Inc. assumes no responsibility for any
errors contained herein.

(P) U.S. Patent 4,214,125 and others, other patents
pending.

All other trademarks are owned by their respective
holders and are used for identification purposes only.

10 © 2000—2001 ESS Technology, Inc. All rights reserved. SAM0358-052201