Page 1
Swan ES4118
Super VCD Processor
Product Brief
DESCRIPTION
The Swan ES41 18 processor is a single-chip solution for Sup er
Video Compact Disk (SVCD) players that integrates MPEG
audio and video decoding, as well as system control software.
The fully programmable The ES4118 offers the best feature set
compared to existing SVCD chips and includes a glueless
interface to various peripheral components. The ES4118 is the
most cost-effective solution in its class, with levels of integration
and quality that establish new benchmarks.
The ES4118 processor is capable of decoding MPEG-2 audio
simultaneously with MPEG-1 or MPEG-2 video. For embedded
applications, the RISC processor core of the ES4118 can be
used in place of a microcontroller to provide a rich set of system
control features. On-chip, multitap fil ters provide arbi trary scaling
with state-of-the-art SmartScale™ technology that is useful for
video standards conversion. SmartStream™ provides video
error concealment and video postprocessing, ensuring the
highest playability and video quality.
The ES4118 connects directly with both 8- and 16-bit ROM and
with either 16-bit SDRAM ICs or with EDO DRAM ICs. An 8-bit
YUV video interface supports many TV encoders. Generalpurpose auxiliary pins are provided to control various peripheral
devices. A standard I
and ADCs. Figure 1 shows a block diagram of a typical
standalone system, using the ES4118 with the glueless SDRAM
interface.
The SVCD data system stream from a CD disc is passed to the
ES41 18 through the I2S interface. The ES4118 parses the sys tem
layer and demultiplexes the audio and video streams. Audio is
decoded and passed through the I
external audio DAC and then to the speakers. Video is decoded
and output as YUV pixels to an NTSC or PAL video encoder.
Onchip system con trol and h ousek eeping functi ons (ke yp ad and
remote control) are also provided.
2
S interface supports popular audio DACs
2
S audio serial bus to an
FEATURES
• Single-chip SVCD decoder in a 208-pin plastic quad flat
package (PQFP)
• Supports MPEG-1 system and MPEG-2 program streams
• Programmable multimedia processor architecture
• Compatible with Audio CD, Video CD 1.1, 2.0, Interactive VCD
3.0, and Super Video CD
Video
• Trick modes, including Slow, Fast Forward, Fast Reverse, Step,
and Goto
• 4-bit onscreen display (OSD) with 4-bit blending
• 8-bit YUV output
Audio
• Karaoke function
• Supports 256/384iframe sync audio system clock
• Bidirectional I
Smart Technology
• SmartScale™ for NTSC to PAL conversion and vice versa
• SmartStream™ for video error concealment
Peripheral
• Independent audio bit clock for transmit and receive port
• Direct servo/loader interface
• Supports up to 4 MB of SDRAM and/or 4 MB of EDO DRAM
• Eight general-purpose auxiliary ports
• Single 27-MHz clock input
• Power management
2
S audio interface
BLOCK DIAGRAM
Video
EPROM
Audio
CD loader
Swan™
ES4118
2 MB
SDRAM
Figure 1 Typical ES4118 System Block Diagram
ESS Technology, Inc. SAM0422-052901 1
NTSC/PAL
Encoder
Audio
Codec
Panel
Interface
TV
MIC
Speakers
Remote Control/
Keypad
Page 2
ES4118 PINOUT
Figure 2 shows the ES4118 device pinout.
NC
NC
VSS
VCC
NC
VPP
AUX0
AUX1
AUX2
VSS
VCC
AUX3
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
VCC
LCS0#
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VCC
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VCC
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VCC
NC
NC
LA0
LA1
LA2
LA3
VSS
NC
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233343536373839404142434445464748495051
NC
153
NC
152
NC
NC
VCC
VSS
NC
NC
145
146
147
148
149
150
151
HD4
HD5
HD6
NC
144
NCNCHD15
142
143
VSS
HD13
HD12
HD11
HD10
HD9
HD14
VCC
137
138
139
140
141
HD8
HD7
VCC
130
131
132
133
134
135
136
HD3
VSS
125
126
127
128
129
Swan ES4118F
208-Pin PQFP Package
HD2
124
HD1
123
HD0
122
ES4118 PRODUCT BRIEF
VCC
VSS
HSYNC#
PCLK2XSCN
YUV7
YUV6
PCLKQSCN
VSYNC#
118
119
120
121
YUV5
VSS
VCC
YUV4
YUV3
YUV2
YUV1
YUV0
DCLK
105
106
107
108
109
110
111
112
113
114
115
116
117
104
103
102
101
100
52
99
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
72
71
70
69
68
67
66
65
64
62
61
60
59
57
56
55
54
53
VCC
VSS
DSCK
DQM
DCS0#
98
97
96
73
63
58
VCC
VSS
DCS1#
DB15
DB14
DB13
DB12
VCC
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VCC
DRAS2#
DRAS1#
DRAS0#
DWE#
DOE#/DSCK_EN
DCAS#
VCC
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VCC
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
NC
NC
NC
VSS
VCC
TBCK
MCLK
XIN
RSD
RWS
RBCK
VSS
VCC
XOUT
APLLCAP
LA4
LA5
LA6
LA7
LA8
LA9
VCC
VSS
VCC
LA11
LA10
LA12
VSS
LA13
VCC
LA14
LA15
LA16
LA17
LA18
LA19
VSS
VCC
LA21
LA20
RESET#
TDMDX/RSEL
TDMFS
TDMDR
TDMCLK
TDMTSC#
TWS/SEL_PLL1
NC
VSS
VCC
SEL_PLL2
TSD/SEL_PLL0
Figure 2 ES4118 Device Pinout
2 SAM0422-052901 ESS Technology, Inc.
Page 3
ES4118 PIN DESCRIPTION
Table 1 lists the ES4118 pin descriptions.
Table 1 ES4118 Pin Descriptions List
Name Number I/O Definition
1, 9, 18, 27, 35, 44,
VCC
LA[21:0]
VSS
RESET# 24 I Reset input, active low.
TDMDX 25 O TDM transmit data.
RSEL
TDMDR 28 I TDM receive data.
TDMCLK 29 I TDM clock input.
TDMFS 30 I TDM frame sync.
TDMTSC# 31 O TDM output enable.
TWS 32 O Audio transmit frame sync.
TSD 33 O Audio transmit serial data port.
SEL_PLL0
51, 59, 68, 75, 83, 92,
99, 104, 111, 121, 130,
139, 148, 157, 164,
172, 183, 193, 201
7:2, 16:10, 23:19,
207:204
8, 17, 26, 34, 43, 52,
60, 67, 76, 84, 91, 98,
103, 112, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
I
3.3V power supply.
O
Device address output.
I
Ground.
I ROM Select.
RSEL Selection
016-bit ROM
1 8-bit ROM.
I Select PLL0:
SEL_PLL2 SEL_PLL1 SEL_PLL0 Notes
0 0 2.5 x DCLK
0 1 3 x DCLK
1 0 3.5 x DCLK
1 1 4 x DCLK.
ES4118 PRODUCT BRIEF
SEL_PLL2 36 I Select PLL2. (Refer to the definitions table in pin number 33.)
NC
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 I/O Audio transmit bit clock.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
APLLCAP 48 I Analog PLL capacitor.
XIN 49 I Crystal input.
XOUT 50 O Crystal output.
DMA[11:0] 53:58, 61:66 O DRAM address bus.
DCAS# 69 O DRAM column address strobe.
DOE#
DSCK_EN O DRAM clock enable
DWE# 71 O DRAM write enable.
DRAS[2:0]# 74:72 O DRAM row address strobe.
DB[15:0] 77:82, 85:90, 93:96 I/O DRAM data bus.
DCS[1:0]# 97, 100 O SDRAM chip select [1:0], active low.
DQM 101 O Data input/output mask.
DSCK 102 O Clock to SDRAM.
37, 38, 41, 42,
142:146, 149:155,
158, 202, 203
70
No connect.
O DRAM output enable.
3 SAM0422-052901 ESS Technology, Inc.
Page 4
Table 1 ES4118 Pin Descriptions List (Continued)
Name Number I/O Definition
DCLK 105 I Clock input (bypass/test mode).
YUV[7:0] 106:110, 113:115 O 8-bit YUV output.
PCLK2XSCN 116 I/O 27 MHz doubled pixel clock.
PCLKQSCN 117 I/O 13.5 MHz pixel clock.
VSYNC# 118 I/O Vertical sync.
HSYNC# 119 I/O Horizontal sync.
HD[15:0]
VPP 159 I 5V power supply.
AUX[7:0] 160:162, 165:169 I/O Auxiliary ports.
LOE# 170 O Device output enable.
LCS[3:0]# 173:176 O Chip select [3:0].
LD[15:0]
LWRLL# 198 O Device write enable.
LWRHL# 199 O Device write enable.
122:128, 131:137,
140:141
178:182, 185:191,
194:197
I/O
I/O
Host data bus.
Device data bus.
ORDERING INFORMATION
ES4118 PRODUCT BRIEF
Part Number Description Package
ES4118F Super VCD Processor 208-pin PQFP
No part of this publication may be reproduced, stored in a
retrieval system, transmitted, or translated in any form or
by any means, electronic, mechanical, ma nual, optical , or
otherwise, without the prior written permission of ESS
Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.
All specifications are subject to change without prior
notice.
ESS Technology, Inc. assumes no responsibility for any
errors contained herein.
(P) U.S. Patent 4,214,125 and others, other patents
pending.
VideoDrive® is a registered trademark of ESS Technology,
Inc.
All other trademarks are owned by their respective
holders and are used for identification purposes only.
4 © 2001 ESS Technology, Inc. All rights reserved. SAM0422-052901
Loading...