Datasheet EN29F040-90J, EN29F040-70T, EN29F040-70PI, EN29F040-70P, EN29F040-70JI Datasheet (EON)

EN29F040
4 Megabit (512K x 8-bit) Flash Memory

FEATURES

•

•

5.0V operation for read/write/erase
operations

•

Fast Read Access Time

- 45ns, 55ns, 70ns, and 90ns

•

Sector Architecture:

- 8 uniform sectors of 64Kbytes each

- Supports full chip erase

- Individual sector erase supported

- Sector protection:
Hardware locking of sectors to prevent

program or erase operations within
individual sectors

•

High performance program/erase speed

- Byte program time: 10µs typical

- Sector erase time: 500ms typical

- Chip erase time: 3.5s typical

•

Low Standby Current

- 1µA CMOS standby current-typical

- 1mA TTL standby current

JEDEC Standard program and erase
commands

•

JEDEC standard
bits feature

•

Single Sector and Chip Erase

•

Sector Unprotect Mode

•

Embedded Erase and Program Algorithms

•

Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode

•

0.35 µm double-metal double-poly

triple-well CMOS Flash Technology

•

Low Vcc write inhibit < 3.2V

•

100K endurance cycle

•

Package Options

- 32-pin PDIP

- 32-pin PLCC

EN29F040

polling and toggle

DATA

•

Low Power Active Current

- 30mA active read current

- 30mA program/erase current

- 32-pin TSOP (Type 1)

•

Commercial and Industrial Temperature

Ranges

GENERAL DESCRIPTION

The EN29F040 is a 4-Megabit, electrically erasable, read/write non-volatile flas h mem ory. Organized
into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of
64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F040 features 5.0V
voltage read and write operation, with access times as fast as 45ns to eliminate the need f or WAIT
states in high-performance microprocessor systems.

The EN29F040 has separate Output Enable (
controls, which eliminate bus contention issues. This device is designed to allow either single (or
multiple) Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.

), Chip Enable (CE), and Write Enable (

OE

WE

)

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

1

EN29F040

TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM

Pin Name Function

A0-A18 Addresses

DQ0-DQ7 Data Inputs/Outputs

CE
OE

WE

Vcc
Vss Ground

Chip Enable

Output Enable

Write Enable

Supply Voltage

(5V ± 10% )

18

CE
OE

WE

Vcc

8

EN29F040

Vss

TABLE 2. SECTOR ARCHITECTURE

DQ0 - DQ7 A0 - A18

Sector ADDRESSES

7 70000h - 7FFFFh 64 1 1 1

6 60000h - 6FFFFh 64 1 1 0

5 50000h – 5FFFFh 64 1 0 1

4 40000h – 4FFFFh 64 1 0 0

3 30000h – 3FFFFh 64 0 1 1

2 20000h - 2FFFFh 64 0 1 0

1 10000h - 1FFFFh 64 0 0 1

0 00000h - 0FFFFh 64 0 0 0

SIZE (Kbytes) A18 A17 A16

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

2

BLOCK DIAGRAM

Vcc
Vss

State

WE

CE
OE

Control

Command

Register

Block Protect Switches

Erase Voltage Generator

Program Voltage

Generator

STB

Chip Enable

Output Enable

Logic

Y-Decoder

Address Latch

EN29F040

DQ0-DQ7

Input/Output Buffers

STB

Data Latch

Y-Gating

A0-A18

Timer Vcc Detector

X-Decoder

Cell Matrix

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

3

EN29F040

FIGURE 2. PDIP

FIGURE 3. PLCC

FIGURE 4. TSOP

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

4

EN29F040

TABLE 3. OPERATING MODES

4M FLASH USER MODE TABLE

USER MODE

STANDBY H X X X X X X X X X HI-Z

READ L H L A9 A8 A6 A5 A1 A0 Ax/y DQ (0-7)

OUTPUT DISABLE L H H X X X X X X X HI-Z

READ

MANUFACTURE ID

READ DEVICE ID L H L VID L/H L X L H X DEVICE ID (T/B)
VERIFY SECTOR

PROTECTION

SECTOR

PROTECTION
VERIFY SECTOR
UNPROTECTION

SECTOR

UNPROTECTION

WRITE L L H A9 A8 A6 A5 A1 A0 Ax/y DIN (0-7)

CE

L H L VID L/H L X L L X MANUFACTURE

L H L VID X L X H L X CODE
L Pulse
L H L VID X H X H L X CODE

Pulse

L

WE OE

VID VID X L X X X X X

L

VID VID L X X H X X X X

A9 A8 A6 A5 A1 A0 Ax/y DQ(0-7)

ID

NOTES:

1) L = V

2) X = Don’t care, either V

3) Ax/y: Ax = Addr(x), Ay = Addr(y)

, H = VIH, VID = 11.0V ± 0.5V

IL

or VIL

IH

TABLE 4. DEVICE IDENTIFICTION

4M FLASH MANUFACTURER/DEVICE ID TABLE

READ

MANUFACTURER ID

READ

DEVICE ID

NOTES:

1) If a Manufacturing ID is read with A8 = L, the chip will output a configuration code 7Fh. A further
Manufacturing ID must be read with A8 = H.

2) If a Device ID is read with A8 = L, the chip will output a configuration code 7Fh. A further Device ID
must be read with A8 = H.

A8 A6 A1 A0

(1)

H

(2)

H

L L L
L L H

DQ(7-0)

HEX

MANUFACTURER ID

1C

DEVICE ID

04

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

5

CE

EN29F040

USER MODE DEFINITIONS

Standby Mode

The EN29F040 has a CMOS-com patible standby mode, which reduces the

It is placed in CMOS-compatible s tandby when the
TTL-com patible standby mode, which reduces the maximum V
TTL-com patible standby when the
high-impedance state independent of the

pin is at VIH. When in st andby m odes, the outputs are in a

CE

input.

OE

pin is at VCC ± 0.5. The device also has a

current to < 1mA. It is plac ed in

CC

Read Mode

The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is also ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.
The system can read array data using the standard read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5
goes high, or while in the autoselect mode. See “Reset Command” section.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more
information. The Read Operations table provides the read parameters, and Read Operation Timings
diagram shows the timing diagram.

Output Disable Mode

When the

pin is at a logic high level (VIH), the output from the EN29F040 is disabled. The

OE

output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipm ent to automatically match a device to be programmed with its corresponding
programming algorithm . However, the autoselect c odes can also be ac cessed in-s ystem through the
command register.

When using programming equipment, the autoselect mode requires V
address pin A9. Address pins A6, A1, and A0 m ust be as shown in Autoselect Codes (High Voltage
Method) table. In addition, when verifying sector protec tion, the sector address must appear on the
appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The
Command Definitions table shows the remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0.

To access the autoselect c odes in-system; the host system can issue the autoselec t command via
the command regis ter, as shown in the Command Definitions table. This m ethod does not require

ID. See “Command Definitions” for details on using the autoselect mode.

V

current to < 1µA (typical).

ID (10.5 V to 11.5 V) on

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

6

EN29F040

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are

don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading array data. Once erasure begins, however,
the device ignores reset commands until the operation is complete. The reset command may be
written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores reset commands until the operation is
complete.

The reset command may be written between the sequence cycles in an autoselect command
sequence. Once in the autoselect mode, the reset command must be written to return to reading
array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device
to reading array data (also applies during Erase Suspend).

Write Mode

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing
two unlock write cycles, followed by the program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program algorithm. The system is not required
to provide further controls or timings. The device automatically provides internally generated program
pulses and verifies the programmed cell margin. Table 5 (Command Definitions) shows the address
and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data
and addresses are no longer latched. The system can determine the status of the program operation
by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be

programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to

“1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a
succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

COMMAND DEFINITIONS

The operations of the EN29F040 are selec ted by one or more commands written into the command
register to perform Read/Reset Mem ory, Read ID, Read Sector Protection, Program , Sector Erase,
Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences
written at specific addresses via the c omm and register . The sequences f or the specified operation
are defined in the Command Table (Table 5). Incorrect addresses, incorrect data values or
improper sequences will reset the device to the read mode.

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

7

EN29F040

Table 5. EN29F040 Command Definitions

Command
Sequence

Read/Reset

Read/Reset

AutoSelect

Manufacturer ID

AutoSelect Device ID

AutoSelect Sector

Protect Verify
Byte Program

Chip Erase

Sector Erase
Sector Erase Suspend
Sector Erase Resume

Read

Reset

Write

Cycles

Req’d

1 RA RD
1 XXXh F0h
4 555h AAh 2AAh 55h 555h F0h RA RD

4 555h AAh 2AAh 55h 555h 90h

4 555h AAh 2AAh 55h 555h 90h
4 555h AAh 2AAh 55h 555h 90h

4 555h AAh 2AAh 55h 555h A0h PA PD
6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h BA 30h
1 xxxh B0h
1 xxxh 30h

st

1

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

nd

2

Write Cycle

rd

3

Write Cycle

th

4

Write Cycle

000h/

100h

001h/

101h
BA &

02h

7Fh/

1Ch

7Fh/

04h

00h/

01h

th

5

Write Cycle

6

Write Cycle

Notes:

RA = Read Address: address of the memory location to be read. This one is a read cycle.
RD = Read Data: data read from location RA during Read operation.

This one is a read cycle.

PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
BA = Sector Address: address of the Sector to be erased. Address bits A17-A13 uniquely select any Sector.

Byte Programming Command

Programming the EN29F040 is per formed on a byte-by-byte basis using a four bus- cycle operation
(two unlock write c ycles followed by the Program Setup command and Program Data W rite cycle).
When the program com mand is exec uted, no additional CPU controls or tim ings are necessar y. An
internal timer term inates the program operation automatically. Address is latched on the falling edge

of

CE

or

, whichever is last; data is latched on the rising edge of CE or

WE

, whichever is first.

WE

The program operation is completed when EN29F040 returns the equivalent data to the programmed
location.

Programming status may be checked by sampling data on DQ7 (

polling) or on DQ6 (toggle

DATA

bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is

exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.

not require

th

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

8

Any commands written to the chip during the Embedded Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in
“AC Characteristics” for parameters, and Chip/Sector Erase Operation Timings for timing waveforms.

EN29F040

Sector Erase Command

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the address of the sector to be erased, and the sector erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.

The device does
algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations.

not require the system to preprogram the memory prior to erase. The Embedded Erase

This device does not support multiple sector erase commands. Sector Erase operation will
commence immediately after the first 30h command is written. The first sector erase operation must
finish before another sector erase command can be given.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the
algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation
or Embedded Program algorithm. Addresses are “don’t-cares” when writing the Erase Suspend
command.

When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erase­suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information.

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

9

The system must write the Erase Resume command (address bits are “don’t care”) to exit the
erase suspend mode and continue the sector erase operation. Further writes of the Resume command
are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

EN29F040

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure re­quires a high voltage (V

an additional supplement on this feature.

ID) on address pin A9 and the control pins. Contact Eon Silicon Devices, Inc. for

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

10

A

EN29F040

WRITE OPERATION STATUS

DQ7

DAT

The EN29F040 provides
embedded operations. The

Erase, Chip Erase, and Erase Suspend. (See Table 6)
When the Byte Programming is in progress, an attempt to read the device will produce the

complement of the data last written to DQ7. Upon the completion of the Byte Programming, an
attempt to read the device will produc e the true data last written to DQ7. F or the Byte Programm ing,

DATA

When the em bedded Erase is in progress, an attempt to read the device will produce a “0” at the

DQ7 output. Upon the completion of the em bedded Eras e, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the

WE

rising edge of the sector erase

DATA

and not a protected sector. Otherwise,
used is in a protected sector.

Just prior to the com pletion of the embedded operations, DQ7 may change asynchronously when the
output enable (

instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid
data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for
diagram is shown in Figure 8.

DQ6
Toggle Bit I

The EN29F040 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, suc cessive attem pts to read data from the device
at any address (by toggling

the embedded Program or Erase operation is com plete, DQ6 will stop toggling and valid data will be
read on the next successive attem pts. During Byte Programming, the Toggle Bit is valid after the

rising edge of the fourth
after the rising edge of the sixth-cycle sequence. For Sector Erase, the T oggle Bit is valid after the
last rising edge of the Sector Eras e
time-out window.

Polling

Polling on DQ7 to indicate to the host system the status of the

DATA

Polling feature is active during the Byte Programm ing, Sector

DATA

polling is valid after the rising edge of the fourth WE or CEpulse in the four-cycle sequence.

polling is valid after the rising edge of the six th

DATA

or CE pulse in the six-c ycle sequence. For Sector Erase,

or

WE

Polling must be performed at any address within a sector that is being programmed or erased

) is low. This means that the device is driving status information on DQ7 at one

OE

Polling (DQ7) is shown on Flowchart 5. The

DATA

or CE) will result in DQ6 toggling between “zero” and “one”. Once

OE

pulse in the four-cycle sequence. For Chip Erase, the T oggle Bit is valid

WE

WE

pulse.

CE

polling may give an inaccurate result if the address

DATA

pulse. The Toggle Bit is also active dur ing the s ec tor eras e

polling is valid after the last

DATA

DATA

Polling (DQ7) timing

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

11

EN29F040

In Byte Programming, if the sector being written to is protected, DQ 6 will toggles for about 2 µs, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protec ted, DQ6 will toggle for about 100 µs. The chip will then return to the r ead
mode without changing data in all protected sectors.

Toggling either

or OE will cause DQ6 to toggle.

CE

The flowchart for the T oggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9

.

DQ5 Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1.” (

time to make sure that the DQ5 is not a “1” due to the device having returned to read mode.)

failure condition that indicates the program or erase cycle was not successfully completed.

The Toggle Bit (DQ6) should also be checked at this

This is a

.

DATA

Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still function under this condition. Setting
the

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return the device to reading
array data.

to VIH will partially power down the device under those conditions.

CE

DQ2 Erase Toggle Bit II

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when
the system reads at addresses within those sectors that have been selected for erasure. (The system may
use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and
DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See
also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing
diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

12

EN29F040

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read
cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Flowchart 6).

Table 6. Status Register Bits

DQ Name Logic Level Definition

Erase Complete or

erase Sector in Erase suspend

Program Complete or

Suspend

Program On-Going

Erase Complete

currently addressed

Erase Suspend read on

non Erase Suspend Sector

7

6

5 ERROR BIT

2

DATA

POLLING

TOGGLE

TOGGLE

‘-1-0-1-0-1-0-1-’ Erase or Program On-going

BIT

‘-1-1-1-1-1-1-1-‘

‘-1-0-1-0-1-0-1-’

BIT

‘1’
‘0’ Erase On-Going

DQ7

DQ7

DQ6 Read during Erase Suspend

‘1’ Program or Erase Error
‘0’ Program or Erase On-going

DQ2

data of non-erase Sector during Erase

Chip Erase, Erase or Erase suspend on

Sector. (When DQ5=1, Erase Error due to

currently addressed Sector. Program during

Erase Suspend on-going at current address

Notes:

DQ7
DQ5 for Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend i s acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Error Bit: set to “1” if failure in programming or erase

Polling: indicates the P/E C status check during Program or Erase, and on c ompletion before checki ng bi t s

DATA

DQ2 Toggle Bit: indicates the Erase status and allows identi fication of the erased Sec t or.

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

13

EN29F040

DATA PROTECTION

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and loc ks out write cycles. Even
with

WE

Low VCC Write Inhibit

During V
unintentional writes. If V
erase circuits are disabled. Under this condition, the device will reset to the READ mode. Subsequent
writes will be ignored until V

Write “Noise” Pulse Protection

Noise pulses less than 5ns on
command register.

= VIL, WE = VIL and OE = VIH, the device will not accept com mands on the rising edge of

CE

.

power-up or power-down, the EN20F040 locks out write cycles to protect against any

CC

CC

< V

> V

CC

, the command register is disabled and all internal program or

LOK

LKO.

OE, CE

or WE will neither initiate a write cycle nor change the

Logical Inhibit

=VIH or WE=VIH, writing is inhibited. To initiate a write cycle, CE and

If

CE

“zero”. If

CE

,

, and OE are all logical zero (not recommended usage), it will be cons idered a

WE

must be a logical

WE

write.

Sector Protect and Unprotect

The hardware sector protection feature disables both program and erase operations in any sector.
The hardware sector unprotec tion f eatur e re- enables both progr am and erase operation in previously
protected sectors.

Sector protection/unprotection m ust be implem ented using pr ogramm ing equipm ent. The proc edure
requires a high voltage (V
Inc. for an additional supplement on this feature.

) on address pin A9 and the control pins. Contact Eon Silicon Devic es,

ID

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

14

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

Increment

Address

No

START

Write Program

Command Sequence

(shown below)

Data Poll Device

Last

Address?

EN29F040

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

See the Command Definitions section for more information.

555H / AAH

2AAH / 55H

555H / A0H

PROGRAM ADDRESS / PROGRAM DATA

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

15

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

(shown below)

Data Polling Device or Toggle Bit

Successfully Com pleted

ERASE Done

EN29F040

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

16

Flowchart 4. Embedded Erase Command Sequence

See the Command Definitions section for more information.

Chip Erase Sector Erase

555H/AAH

2AAH/55H

555H/80H

555H/AAH

555H/AAH

2AAH/55H

555H/80H

555H/AAH

EN29F040

2AAH/55H

555H/10H

2AAH/55H

Sector Address/30H

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

17

Flowchart 5. DATAPolling Algorithm

Start

Read Data

Yes

No

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Data

EN29F040

DQ7 = Data?

No

Fail Pass

Yes

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

18

Flowchart 6. Toggle Bit Algorithm

Start

Read Data

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Data

EN29F040

DQ6 = Toggle?

Yes

Fail Pass

No

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

19

EN29F040

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

(Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V

V

CC

A9, OE# (Note 2) . . . . . . . . . . . . . . . –0.5 V to 11.5 V

All other pins (Note 1) . . . . . . . . . . . . –0.5 V to Vcc+0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot

V

SS to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left Figure below.

Maximum DC voltage on input and I/O pins is V

pins may overshoot to V

2. Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and OE# may

undershoot V

Figure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V for

periods up to 20 ns.

3. No more than one output shorted to ground at a time. Duration of the short circuit should not be

greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the operational sections of this specification is

not implied. Exposure of the device to absolute maximum rating conditions for extended periods may

affect device reliability.

SS to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left

CC + 2.0 V for periods up to 20 ns. See Right Figure below.

CC + 0.5 V. During voltage transitions, input and I/O

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T A ) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T A ). . . . . . . . . . -40°C to +85°C

V

Supply Voltages

CC

V

for ± 5% devices . . . . . . . . . . . . +4.75 V to +5.25 V

CC

for ± 10% devices . . . . . . . . . . . +4.50 V to +5.50 V

V

CC

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Maximum Negative Overshoot Maximum Positive Overshoot

Waveform Waveform

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

20

CE

EN29F040

Table 7. DC Characteristics

(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 5.0V ± 10%)

Symbol Parameter Test Conditions Min Max Unit

ILI

ILO

I

CC1

I

CC2

I

CC3

I

CC4

VIL

VIH

VOL

VOH

Output High Voltage CMOS

VID
I

LIT

V

LKO

Input Leakage Current

Output Leakage Current

Supply Current (read) TTL Byte

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Supply Current (Program or Erase)

Input Low Voltage -0.5 0.8 V

Input High Voltage 2

Output Low Voltage

Output High Voltage TTL

A9 Voltage (Electronic Signature) 10.5 11.5 V
A9 Current (Electronic Signature) A9 = VID 100 µA

Supply voltage (Erase and

Program lock-out)

0V≤ VIN ≤ Vcc

0V≤ V

= VIL; OE = VIH;

CE

Byte program, Sector or Chip

Erase in progress

IOL = 2 mA

IOH = -2.5 mA
IOH = -100 µA

≤ Vcc

OUT

f = 6MHz

= VIH

CE

= Vcc ± 0.3V

±5 µA
±5 µA

30 mA

1.0 MA

5.0 µA

0.45 V

2.4 V

Vcc -

0.4V

3.2 4.2 V

30

Vcc +

0.5

V

mA

V

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

21

CE

Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics

Parameter

Symbols

JEDEC Standard

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

EHQZ

t

GHQZ

t

AXQX

t
t
t

t
t

t

t

Read Cycle Time

RC

Address to Output Delay

ACC

Chip Enable To Output Delay

CE

Output Enable to Output Delay

OE

Chip Enable to Output High Z

DF

Output Enable to Output High Z

DF

OH

Description

Output Hold Time from

Addresses,

whichever occurs first

Test Setup

or OE,

CE

Min 45 55 70 90 ns

= V

IL

OE

OE

= VIL

= VIL

Max 25 30 30 35 ns

Max 10 15 20 20 ns

Max 10 15 20 20 ns

Min 0 0 0 0 ns

-45 -55 -70 -90 Unit

Max 45 55 70 90 ns

Max 45 55 70 90 ns

Notes:

For -45, -55 Vcc = 5.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V t o 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V

For all others: Vcc = 5.0V ± 10%
Input Rise and Fall Times: 20 ns

Input Pulse Levels: 0. 45 V to 2.4 V
Timing Measurement Reference Level, Input and Output: 0.8 V and 2. 0 V

Output Load: 1 TTL gate and 100 pF

EN29F040

Speed Options

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

22

Table 9. AC CHARACTERISTICS
Write (Erase/Program) Operations

Parameter

Symbols

JEDEC Standard

t

AVAV

t

AVWL

t

WLAX

t

DVWH

t

WHDX

t

GHWL

t

ELWL

t

WHEH

t

WLWH

t

WHDL

t

WHWH1

t

t

t

t

t

t

t

t
t

t

t

Write Cycle Time

WC

Address Setup Time

AS

Address Hold Time

AH

Data Setup Time

DS

Data Hold Time

DH

t

Output Enable Setup Time

OES

t

OEH

GHWL

CS
CH

WP

WPH

WHWH1

Output Enable

Hold Time

Read Recovery Time before

Write (

OE

Write Pulse Width

Write Pulse Width High

Programming Operation

Description

High to WE Low)
SetupTime

CE

Hold Time

CE

Read

Toggle and

DATA

Polling

EN29F040

Speed Options

Min 45 55 70 90 ns

Min 0 0 0 0 ns

Min 35 45 45 45 ns

Min 20 25 30 45 ns

Min 0 0 0 0 ns

Min 0 0 0 0 ns
MIn 0 0 0 0 ns
Min 10 10 10 10 ns

Min 0 0 0

Min 0 0 0
Min 0 0 0
Min 25 30 35
Min 20 20 20
Typ 7 7 7

Max 200 200 200

-45 -55 -70 -90 Unit

0 ns

0 ns

0 ns
45 ns
20 ns

7 µs

200 µs

t

WHWH2

t

WHWH3

t

t

WHWH2

WHWH3

t

VCS

t

VIDR

Typ 0.3 0.3 0.3

Sector Erase Operation

Chip Erase Operation

Vcc Setup Time

Rise Time to V

ID

Max 5 5 5

Typ 3 3 3

Max 35 35 35

Min 50 50 50
Min 500 500 500

0.3 s
5 s
3 s

35 s
50 µs

500 ns

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

23

Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations

Alternate CE Controlled Writes

Parameter

Symbols

JEDEC Standard

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

GHEL

t

WLEL

t
t
t

t

t

t

t

Write Cycle Time

WC

Address Setup Time

AS

Address Hold Time

AH

Data Setup Time

DS

Data Hold Tim e

DH

t

Output Enable Setup Time

OES

t

OEH

GHEL

WS

Output

Enable

Hold Time
Read Recovery Time before
Write (

WE

Description

High to CE Low)

OE

SetupTime

Read

Toggle and

Data Polling

EN29F040

Speed Options

Min 45 55 70 90 ns

Min 0 0 0 0 ns

Min 35 45 45 45 ns

Min 20 25 30 45 ns

Min 0 0 0 0 ns

Min 0 0 0 0 ns

0 0 0 0 0 ns

10 10 10 10 10 ns
Min 0 0 0
Min 0 0 0

-45 -55 -70 -90 Unit

0 ns
0 ns

t

EHWH

t

ELEH

t

EHEL

t

WHWH

1

t

WHWH

2

t

WHWH

3

t
t

t

t

WHWH1

t

WHWH2

t

WHWH3

WH

CPH

t

VCS

t

VIDR

CP

Write Pulse Width High

Programming Operation

Sector Erase Operation

Chip Erase Operation

Hold Time

WE

Write Pulse Width

Vcc Setup Time

Rise Time to V

ID

Min 0 0 0
Min 25 30 35
Min 20 20 20
Typ 7 7 7

Max 200 200 200

Typ 0.3 0.3 0.3

Max 5 5 5

Typ 3 3 3

Max 35 35 35

Min 50 50 50
Min 500 500 500

0 ns
45 ns
20 ns

7 µs

200 µs

0.3 s
5 s
3 s

35 s
50 µs

500 ns

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

24

EN29F040

Table 11. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Sector Erase Time 0.3 5 sec

Chip Erase Time 3 35 sec

Byte Programming Time 7 200 µs

Chip Programming Time 2 5 sec

Erase/Program Endurance 100K cycles

Limits

Typ Max Unit

Excludes 00H programming prior to

Excludes system level overhead

Minimum 100K cycles guaranteed

Comments

erasure

Table 12. LATCH UP CHARACTERISTICS

Parameter Description Min Max

Input voltage with respect to Vss on all pins except I/O pins
(including A9 and OE)

-1.0 V 12.0 V

Input voltage with respect to Vss on all I/O Pins -1.0 V Vcc + 1.0 V
Vcc Current -100 mA 100 mA

Note : These are latch up characteristics and the device should never be put under
these conditions. Refer to Absolute Maximum ratings fo r the actual operating limits.

Table 13. 32-PIN PLCC PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN

C

OUT

C

IN2

Input Capacitance

Output Capacitance

Control Pin Capacitance

VIN = 0

V

OUT

VIN = 0

= 0

4 6 pF
8 12 pF
8 12 pF

Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN

Input Capacitance

VIN = 0

6 7.5 pF

C

OUT

C

IN2

Output Capacitance

Control Pin Capacitance

V

OUT

VIN = 0

= 0

8.5 12 pF

7.5 9 pF

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

25

Table 15. DATA RETENTION

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time

EN29F040

150°C 10 Years
125°C 20 Years

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

26

SWITCHING WAVEFORMS

Figure 5. AC Waveforms for READ Operations

Figure 6. AC Waveforms for Chip/Sector Erase Operations

EN29F040

Notes:

1. SA is the Sector address for Sector erase.

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

27

SWITCHING WAVEFORMS (continued)

Figure 7. Program Operation Timings

EN29F040

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. /DQ7 is the output of the complement of the data written to the device.

4. D

5. Figure indicates last two bus cycles of four bus cycle sequence.

is the output of data written to the device.

OUT

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

28

EN29F040

Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations

Notes:

*DQ

= Valid Data (The device has completed the embedded operation).

7

Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations

Notes:
*DQ6 stops toggling (The device has completed the embedded operation).

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

29

SWITCHING WAVEFORMS (continued)

Figure 10. Alternate /CE Controlled Write Operation Timings

EN29F040

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. /DQ7 is the output of the complement of the data written to the device.

4. D

5. Figure indicates last two bus cycles of four bus cycle sequence.

is the output of data written to the device.

OUT

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

30

EN29F040

ORDERING INFORMATION

EN29F040 - 45 P I

TEMPERATURE RANGE
(Blank) = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)

PACKAGE
P = 32 Plastic DIP
J = 32 Plastic PLCC
T = 32 Plastic TSOP

SPEED
45 = 45ns
55 = 55ns
70 = 70ns
90 = 90ns

BASE PART NUMBER
EN = EON Silicon Devices
29F = FLASH, 5V
040 = 512K x 8

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

31

EN29F040

Revisions List

A,B:

Preliminary

C (2001.07.03):

Pg. 13 Logical Inhibit section now says that if

(not recommended usage), it will be considered a write.

VID is everywhere changed to be VID =11.5 ± 0.5V

D (2001.07.05):
“block” changed to “sector”

Deleted Sector Un/Protect flow charts (we have a supplement for that)

VID is everywhere changed to be VID =11.0 ± 0.5V
LACTHUP >= 200mA line removed from first page
Chip erase and Sector Erase command descriptions modified.
DQ7,DQ5,DQ3 status polling descriptions modified.
Table 12 Latchup characteristics modified

, WE, and OE are all logical zero

CE

4800 Great America Parkway, Suite 202 Tel: [phone]
Santa Clara, CA 95054 Fax: [phone]

Rev. D, Issue Date: 2001/07/05

32