Datasheet EN27LV020B150J, EN27LV020B120TI, EN27LV020B120T, EN27LV020B120PI, EN27LV020B120P Datasheet (EON)

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Preliminary

1

EN27LV020 / EN27LV020B

FEATURES

• Read Access Time:

-90ns, -120ns, -150ns, -200ns

• Single +3.3V P ower Supply

-Regulated power supply 3.0V - 3.6V

(EN27LV020)

-Unregulated power supply 2. 7V - 3.6V

(EN27LV020B for battery operated systems)

• Programming Voltage +12.75V

• QuikRite

TM

Programming Algor ithm

• Typical programming ti me 20µs

• Low Power CMOS Operation

• 1µA Standby (Typical)

• 15mA Operation (Max .)

• CMOS- and TTL-Compatibl e I/O

• High-Reliability CMOS Technology

• Latch-Up Immunit y to 100mA

from -1V to V

CC

+ 1V

• Two-Line Control (

OE & CE )

• Standard Product Identification Code

• JEDEC Standard Pinout

• 32-pin PDIP

• 32-pin PLCC

• 32-pin TSO P ( Type 1)

• Commer c ial and Industrial Temperature

Ranges

GENERAL DESCRIPTION

The EN27LV020 / EN27LV020B is a low-voltage, low-power 2-Megabit, 3.3V one-time­programmabl e (OTP) read-only memory (EPROM). Organized into 256K words with 8 bits per
word, it f eatur es Quik Rit e

TM

singl e-address locati on program mi ng, typi call y at 20µs per byte. Any

byte can be accessed in less than 90ns. The EN27LV020 / EN27LV020B has separate Output
Enable (

OE) and Chip Enable (CE) controls which eliminate bus contention issues. The
EN27LV020 has a Vcc tolerance range of 3.0V to 3.6 V, making it suitable f or use in systems
that have regulat ed power supplies. The EN27LV020B has a Vcc tolerance range of 2.7 V to

3.6V, m ak ing it an i deal dev ice for battery operated systems.

FIGURE 1. PDIP

Pin Name Function

A0-A17 Addresses
DQ0-DQ7 Outputs
CE Chip Enable
OE Output Enable
PGM Program Str obe

A17

EN27LV020 / EN27LV020B 2Megabit Low Voltage EPROM (256K x 8)

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EN27LV020 / EN27LV020B

FIGURE 2. TSOP

FIGURE 3. PLCC

TSO

P

EN 27LV020/

EN27L V020B

A1

7

PLCC Top V iew

A12 A16 Vcc A17

A15 Vpp PG M

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3

EN27LV020 / EN27LV020B

FIGURE 4. BLOCK DIAGRAM

FUNCTIONAL DESCRIPTION

THE QUIKRITETM PROGRAMMING OF THE EN27LV020 / EN27LV020B

When t he EN27LV020 / EN27LV020B i s deliv ered, the chi p has all 2M bi ts in the “ONE”, or
HIGH state. “ ZEROs” are l oaded into t he EN27LV020 / EN27LV 020B through t he procedure
of programming.

The programming m ode is entered when 12.75 ± 0.25V is applied to the V

PP

pin, OE is at

V

IH

, and CE and PG M are at VIL. For programmi ng, the data to be pr ogramm ed is appli ed

with 8 bits in par allel t o the data pins.
The QUIKRITE

TM

programming flowchart in Figure 5 shows Eon’s interactive programming
algorit hm. The i nteractive algor ithm r educ es programmi ng time by usi ng 20 µs to 100 µs
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program t he data. Af ter each pulse is applied to a given address, the data i n that
address is veri fied. If the data is not verified, additional pulses are given unt il it is ver ified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the E N27LV 020 / EN27LV020B. This part of t he pr ogr ammi ng
algorit hm is done at V

CC

= 6.25V to assure that eac h E P ROM bit i s programmed t o a

sufficiently high threshol d voltage. This ensures that all bits have suffici ent margi n. After the
final address is complet ed, the entir e E P ROM mem or y is read at V

CC

= V

PP

= 5.25 ± 0.25V t o
verify t he entire m emory. EN27LV020 / EN27LV020B can be programmed using the same
programming algorithm as the 5V Read E P ROM EN27C020.

CONTROL

LOGIC

INPUT/

OUTPUT

BUFFERS

Y-DECODER

X-DECODER

Y-SELECT

2M BIT

CELL

MATRIX

Vcc

Vpp

Vss

A0 - A17
ADDRESS
INPUTS

DQ0 - DQ7

8

1024

2048

CE
PGM
OE

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EN27LV020 / EN27LV020B

PROGRAM INHIBIT MODE

Programming of multiple EN27LV020 / E N27LV 020B in parall el with different data is also
easily accomplished by using t he P r ogr am Inhibit Mode. Except for

CE, all like inputs of the
parallel EN27LV020 / EN27LV020B may be common. A TT L low-level program pulse applied
to an EN27LV020 / EN27LV020B

CE input with VPP = 12.75 ± 0.25V, PGM LOW, and OE

HIGH will program that EN27LV020 / EN27LV020B. A hi gh- level

CE input inhibits the other

EN27LV020 / EN27LV020B from being programmed.

PROGRAM VERIFY MODE

Verificati on shoul d be per form ed on the programmed bits to deter mining that they were
correctl y pr ogr ammed. The ver ifi c ation should be performed with

OE and CE at VIL, PGM

at V

IH

, and VPP at its programming vol tage.

AUTO PRODUCT IDENTIFICATION

The Auto Product Identificat ion mode allows the reading out of a binary code from an EP ROM
that will identify i ts manufacturer and type. This mode is i ntended for use by programmi ng
equipment for the purpose of automat ically matchi ng the device to be programmed with i ts
corresponding programming algorithm. This mode is functional i n the 25°C ± 5°C ambient
temperat ur e r ange that is required when programmi ng the EN27LV020 / EN27LV020B.

To activate t his mode, the pr ogr ammi ng equipment must forc e 12.0 V ± 0.5V on address line A9
of the EN27LV 020 / EN27LV020B. Two ident ifier bytes may t hen be sequenced from the device

outputs by toggling address line A0 from V

IL

to VIH, when A1 = VIH. All other address lines must

be held at V

IL

during Auto Pr oduc t Identificat ion mode.

Byte 0 (A0 = V

IL

) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For
the EN27LV020 / EN27LV020B these two identifiers bytes are given in the Mode Select Table.
All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7)

defined as the par ity bit .

When A 1 = VIL, the EN27LV020 / E N27LV 020B will read out the bi nar y

code of 7F, continuation code, to signify t he unavai lability of manufacturer ID c odes.

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5

EN27LV020 / EN27LV020B

READ MODE

The EN27LV020 / EN27LV020B has two contr ol funct ions, both of whic h must be logic ally
satisfi ed in order to obtain data at the out puts. Chip Enable (

CE) is the power control and

should be used for device selection. Output Enable (

OE) is the output c ontrol and should be
used to gate data to the output pins, independent of device selec tion. Assuming that
addresses are stable, address access time (t

ACC

) is equal to t he delay from CE to output

(t

CE

). Data is avail able at the outputs (tOE) after the falling edge of OE, assuming the CE

has been LOW and addr esses hav e been stable for at least t

ACC

- tOE.

STANDBY MODE

The EN27LV020 / EN27LV020B has CMO S standby mode which reduces the m aximum V

CC

current to 10µA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The E N27LV 020
/ EN27LV020B also has a TTL- standby mode which reduces the m aximum V

CC

current to 0. 6

mA. I t is placed in TTL-standby when

CE is at VIH. When in standby mode, the outputs are

in a high-impedance state, independent of the

OE input.

TWO-LINE OUT PUT CONTROL FUNCTION

To accommodate multiple memor y c onnec tions, a two-line control functi on is provided to
allow for:

1. Low memory power dissipat ion,

2. Assurance that output bus contention will not occur.

It is recommended that

CE be decoded and used as the primary device-sel ec tion func tion,

while

OE be made a common connection to all devices in the array and c onnec ted to the
READ line from the system control bus. This assures that all desel ec ted mem or y devic es are in
their l ow-power standby m ode and that the output pins are only active when data is desired
from a particular memory dev ice.

SYSTEM CONSIDERATIONS

During the switch bet ween active and standby c onditions, t r ansi ent current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient cur r ent peaks
is dependent on the output c apac itance loading of the devic e. At a minimum, a 0.1µF ceramic
capacitor ( high frequency , low inherent inductance) should be used on each device bet ween
VCC and VSS to minimize t r ansi ent effects. In additi on, to overcome the voltage drop caused
by the induct ive eff ec ts of the pri nted circuit board traces on EPRO M ar r ay s, a 4.7µF bulk

electrolytic capac itor should be used between V

CC

and VSS for each eight dev ices. The loc ation

of the capac itor should be cl ose to where the power supply is connected to the ar r ay .

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6

EN27LV020 / EN27LV020B

MODE SELECT TABLE

Mode CE OE PGM A0 A1 A9 V

PP

Output

Read

V

IL

V

IL

X

(2)

XX X

V

CC

D

OUT

Output Disable

V

IL

V

IH

XXXX

V

CC

High Z

Standby (TTL)

V

IH

XX XXX

V

CC

High Z

Standby (CMOS)

V

CC

± 0.3V

XX XXX

V

CC

High Z

Program

(4)

V

IL

V

IH

V

IL

XX X

V

PP

D

IN

Program Ve r ify

V

IL

V

IL

V

IH

XX X

V

PP

D

OUT

Program I nhi bit

V

IH

XX XXX

V

PP

High Z

Manufactur er Code

(3)

V

IL

V

IL

X

V

IL

V

IH

VH

(1)

V

CC

1C

Device Code

(3)

V

IL

V

IL

X

V

IH

V

IH

VH

(1)

V

CC

02

NOTES:

1) VH = 12.0V ± 0.5V

2) X = Either VIH or V

IL

3) For Manufacturer Code and Device Code, A1 = V

IH

When A1 = V

IL

, both codes will read 7F

4) See DC Programming Characteristics f or V

PP

voltage during programming

EON’S STANDARD PRODUCT IDENTIFICATION CODE

Pins

Hex

Data

Code

A0 A1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Manufacturer

01000111001C

Device Type

110000001002

Continuation

00011111117F
10011111117F

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7

EN27LV020 / EN27LV020B

FIGURE 5. QUIKRITETM PROGRAMMING FLOW CHART

20

NOTE 1: E ither 100µs or 20µs pulse.

NOTE 1

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EN27LV020 / EN27LV020B

ABSOLUTE MAXIMUM RATINGS

Storage Temperatur e

-65ÝC to +125ÝC

Ambient Temperature

with Power Applied -40ÝC to +85ÝC

Voltage with Respect to V

SS

All pins except A9, VPP, V

CC

-0.6V to VCC + 0.5V

A9, V

PP

-0.6V to +13.5V

V

CC

-0.6V to +7.0V

OPERATING RANGES

Commercial (C)

Case Temperature(Tc) 0ÝC to +70ÝC

Industrial (I)

Case Temperature(Tc) -40ÝC to +85ÝC

Supply READ Voltages

(for battery operated systems)

+3.0V to +3.6V
+2.7V to +3.6V

(Functionalit y is guaranteed between these limits)

Stresses abov e t hos e s hown abov e may c ause permanent damage to the device. This is a s tr es s rat ing only and operat ion
above these specifications for extended periods may affect device reliability . Ope r ation outside the "O PERATING RANGES"
shown above voids any and all warranty provisions.

DC CHARACTERISTICS FOR READ OPERATION

Symbol Parameter Min. Max. Unit Conditions

V

OH

Output High Volt age 2.4 V IOH = -2.0mA

V

OL

Output Low Voltage 0.45 V IOL = 2.0mA

V

IH

Input High Voltage 2.0 VCC +0.5 V

V

IL

Input Low Voltage -0.3 0.8 V

I

LI

Input Leakage Current -5 5 µA VIN = 0 to 3.6V

I

LO

Output Leakage Current -10 10 µA V

OUT

= 0 to 3.6V

I

CC3

VCC Power -Down Current 10 µA CE = VCC ± 0.3V

I

CC2

VCC Standby Current 0.6 mA CE = V

IH

I

CC1

VCC Active Current 15 mA

CE = V

IL

, f=5MHz,

I

OUT

= 0mA

I

PP1

VPP Supply Current Read 100 µA

CE = OE = V

IL

,

V

PP

= 3.6V

CAPACITANCE

Symbol Param eter Typ. Max. Unit Condi tions

C

IN

Input Capacitance 8 12 pF VIN = 0V

C

OUT

Output Capacitance 8 12 pF V

OUT

= 0V

C

VPP

VPP Capacitance 18 25 pF VPP = 0V

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EN27LV020 / EN27LV020B

AC CHARACTERISTICS FOR READ OPERATION

EN27LV020 /
EN27LV020B

-90 -120

-120

-150

-150

-200

-200

Symbol Parameter Condition Min Max Min Max Min Max MinMax Unit

tACC (3) Address to

Output Delay

CE = OE =

V

IL

90 120 150 200

ns

tCE (2) CE to Output

Delay

OE = V

IL

90 120 150 200

ns

tOE (2, 3) OE to Output

Delay

OE = V

IL

45 45 50 50

ns

tDF (4, 5) OE or CE High to Output

Float, whichever occurred first

40 40 40 40

ns

tOH Output Hold from Address, CE

or OE , whichever occurred first

000 0

ns

Note: Please contact Marketing Department for othe r speed requirements.

FIGURE 6. AC WAVEFORMS FOR READ OPERATION

CE

ADDRESS ADDRESS VALID

OE

OUTPUT

OUTPUT

VALID

tCE

tACC

HIGH Z

tOE

tDF

tOH

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EN27LV020 / EN27LV020B

FIGURE 7: TEST WAVEFORMS AND MEASUREMENTS

DC PROGRAMMING CHARACTERISTICS

Test Limits

Symbol Parameter Conditions Min. Max Units

I

LI

Input Load Current V

IN = VIL, VIH

5.0

µA

V

IL

Input Low Level -0.5 0.8 V

V

IH

Input High Level 0.7 V

CC

V

CC

+ 0.5 V

V

OL

Output Low Voltage I

OL =

2.0 mA 0.45 V

V

OH

Output High Volt age I

OH = -

400 µA 2.4 V

I

ccp

VCC Supply Current 40 mA

I

PP2

V

PP

Supply Current CE = PGM = V

IL,

10 mA

V

ID

A9 Product Identificat i on Voltage 11.5 12.5 V

V

cc

Quikrit e Supply Volt age 6.0 6.5 V

V

pp

Quikrit e Programming Vol t age 12.5 13.0 V

Input Test Waveform and Measurement Level

Output Test Load

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Preliminary

11

EN27LV020 / EN27LV020B

FIGURE 8. PROGRAMMING WAVEFORMS

ADDRESS

VIH
VIL

ADDRESS STABLE

DATA IN

PROGRAM

READ

(VERIFY)

DATA

VIH
VIL

DATA OUT

VALID

V

CC

6.5V

5.0V

V

PP

13.0V

5.0V

CE

VIH
VIL

PGM

VIH
VIL

OE

VIH
VIL

tAS tOE

tPRT

tDS tDH

tVCS

tVPS

tPW

tOES

tCES

tAH

tDFP

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12

EN27LV020 / EN27LV020B

SWITCHING PROGRAMMING CHARACTERISTICS
(TΑ = + 25 ° C ± 5 ° C)

PARAMETER
SYMBOL
STANDARD PARAMETER DESCRIPTION

Min. Max Units

t

AS

Address Setup Time 2

µs

t

OES

OE Setup Time 2 µs

t

DS

Data Setup Time 2 µs

t

AH

Address Hold Time 0 µs

t

DH

Data Hold Time 2 µs

t

DFP

Output Enable to Output Float Delay 0 130 ns

t

VPS

VPP Setup Time 2 µs

t

PW

PGM Program Pulse Width 20 105

µs

t

VCS

V

cc

Setup Time 2

µs

t

CES

CE Setup Time 2

µs

t

OE

Data Valid from OE 150

ns

ORDERING INFORMATION

EN27LV020 / EN27LV020B 90 P I

TEMPERATURE RANGE

(Blank) = Commercial ( 0

Ý

C to +70ÝC)

I = Industrial ( - 40

Ý

C to +85ÝC)

PACKAGE

P = 32 Plastic DIP
J = 32 Plastic PLCC
T = 32 Plastic TSOP

SPEED

90 = 90ns
120 = 120ns
150 = 150ns
200 = 200ns

BASE PART NUMBER

EN = EON Silicon Devices
27 = EPROM
LV = Low Voltage CMO S
020 = 256K x 8 3. 0V to 3.6V Vcc

Tolerance

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Preliminary

13

EN27LV020 / EN27LV020B

020B = 256K x 8 2.7V to 3.6V Vc c

Tolerance