Datasheet EN27LV010B200P, EN27LV010B200JI, EN27LV010B200J, EN27LV010B150TI, EN27LV010B150T Datasheet (EON)

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Preliminary

1

EN27LV010 / EN27LV010B

FEATURES

•

Read Access Time

:

-90ns, -120ns, -150ns, -200ns

•

Single +3.3V Power Supply

-Regulated power supply 3.0V - 3.6V

(EN27LV010)

-Unregulated power supply 2.7V - 3.6V
(

EN27LV010B for battery operated systems)

•

Programming Voltage +12.75V

•

QuikRite

TM

Programming Algorithm

•

Typical programming time 20µs

•

Low Power CMOS Operation

• 1µ

A Standby (Typical)

•

15mA Operation (Max.)

•

CMOS- and TTL-Compatible I/O

•

High-Reliability CMOS Technology

•

Latch-Up Immunity to 100mA
from -1V to V

CC

+ 1V

•

Two-Line Control (

OE & CE)

•

Standard Product Identification Code

•

JEDEC Standard Pinout

•

32-pin PDIP

•

32-pin PLCC

•

32-pin TSOP (Type 1)

•

Commercial and Industrial Temperature
Ranges

GENERAL DESCRIPTION

The EN27LV010/EN27LV010B is a low-voltage, low-power 1-Megabit, 3.3V one-time­programmable (OTP) read-only memory (EPROM). Organized into 128K words with 8 bits per
word, it features QuikRite

TM

single-address location programming, typically at 20

µ

s per byte. Any
byte can be accessed in less than 90ns. The EN27LV010/EN27LV010B has separate Output
Enable (

OE) and Chip Enable (CE) controls which eliminate bus contention issues. The

EN27LV010 has a Vcc tolerance range of 3.0V to 3.6 V, making it suitable for us e in systems that
have regulated power supplies. The EN27LV010B has a Vcc tolerance range of 2.7 V to 3.6V,
making it an ideal device for battery operated systems.

FIGURE 1. PDIP

Pin Name Function

A0-A16 Addresses
DQ0-DQ7 Outputs
CE Chip Enable
OE Output Enable
PGM Program Strobe
NC No Connect

PDIP Top View

VPP

A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
VSS

VCC
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

EN27LV010/EN27LV010B 1Megabit Low Voltage EPROM (128K x 8)

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Preliminary

2

EN27LV010 / EN27LV010B

FIGURE 2. TSOP

EN27LV010/
EN27LV010B

FIGURE 3. PLCC

PLCC Top View

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

5
6
7
8
9
10
11
12
13

29
28
27
26
25
24
23
22
21

A14
A13
A8
A9
A11
OE
A10
CE
DQ7

4232

3131

30

14 16 18

15 17 19

20

DQ1 VSS DQ4

DQ2 DQ3 DQ5

DQ6

A12 A16 VCC

A15 VPP PGM

NC

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Preliminary

3

EN27LV010 / EN27LV010B

FIGURE 4. BLOCK DIAGRAM

CE
PGM
OE

A0-A16
ADDRESS
INPUTS

CONTROL

LOGIC

VCC

VSS

VPP

INPUT/

OUTPUT

BUFFERS

DQ0 - DQ7

8

8

1024

Y-DECODER Y-SELECT

X-DECODER

1M BIT

CELL

MATRIX

1024

FUNCTIONAL DESCRIPTION

THE QUIKRITETM PROGRAMMING OF THE EN27LV010/EN27LV010B

When the EN27LV010/EN27LV010B is delivered, the chip has all 1M bits in the “ONE”, or
HIGH state. “ZEROs” are loaded into the EN27LV010/EN27LV010B through the procedure of
programming.

The programm ing mode is entered when 12.75 ± 0.25V is applied to the V

PP

pin, OE is at V

IH

, and CE and PG M are at VIL. For programming, the data to be program m ed is applied with
8 bits in parallel to the data pins.

The QUIKRITE

TM

programming flowchart in Figure 5 shows Eon’s interactive programming
algorithm. The interactive algorithm reduces programming time by using 20 µs to 100 µs
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to a given address, the data in that
address is verified. If the data is not verified, additional pulses are given until it is verified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the EN27LV010/EN27LV010B. This part of the programming
algorithm is done at V

CC

= 6.25V to assure that each EPROM bit is programmed to a

sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the
final address is completed, the entire EPROM memory is read at V

CC

= V

PP

= 5.25 ± 0.25V to
verify the entire memory. EN27LV010 / EN27LV010B can be programmed using the same
programming algorithm as the 5V Read EPROM EN27C010.

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4

EN27LV010 / EN27LV010B

PROGRAM INHIBIT MODE

Programming of multiple EN27LV010/EN27LV010B in parallel with different data is also easily
accomplished by using the Program Inhibit Mode. Except for

CE, all like inputs of the parallel

EN27LV010/EN27LV010B may be common. A TTL low-level program pulse applied to an
EN27LV010/EN27LV010B

CE input with V

PP

= 12.75 ± 0.25V, PGM LOW, and OE HIGH

will program that EN27LV010/EN27LV010B. A high-level

CE input inhibits the other

EN27LV010/EN27LV010B from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed bits to determining that they were
correctly programmed. The verification should be performed with

OE and CE at V

IL

, PGM at

V

IH

, and VPP at its programming voltage.

AUTO PRODUCT IDENTIFICATION

The Auto Product Identification mode allows the reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode is intended for use by programming equipment
for the purpose of automatically matching the device to be programmed with its corresponding
programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range
that is required when programming the EN27LV010/EN27LV010B.

To activate this mode, the programming equipment must force 12.0 V ± 0.5V on address line A9
of the EN27LV010/EN27LV010B. Two identifier bytes may then be sequenced from the device

outputs by toggling address line A0 from V

IL

to VIH, when A1 = VIH. All other address lines must

be held at V

IL

during Auto Product Identification mode.

Byte 0 (A0 = V

IL

) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For
the EN27LV010/EN27LV010B, these two identifiers bytes are given in the Mode Select Table. All
identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined

as the parity bit.

When A1 = VIL, the EN27LV010/EN27LV010B will read out the binary code of

7F, continuation code, to signify the unavailability of manufacturer ID codes.

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Preliminary

5

EN27LV010 / EN27LV010B

READ MODE

The EN27LV010/EN27LV010B has two control functions, both of which must be logically
satisfied in order to obtain data at the outputs. Chip Enable (

CE) is the power control and

should be used for device selection. Output Enable (

OE) is the output control and should be

used to gate data to the output pins, independent of device selection. Assuming that
addresses are stable, address access time (t

ACC

) is equal to the delay from CE to output

(t

CE

). Data is available at the outputs (tOE) after the falling edge of OE , assuming the CE has

been LOW and addresses have been stable for at least t

ACC

- tOE.

STANDBY MODE

The EN27LV010/EN27LV010B has CMOS standby mode which reduces the maximum V

CC

current to 10µA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The
EN27LV010/EN27LV010B also has a TTL-standby mode which reduces the maximum V

CC

current to 0.6 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent of the

OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-line control function is provided to allow
for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not occur.

It is recommended that

CE be decoded and used as the primary device-selection function,

while

OE be made a common connection to all devices in the array and connected to the READ

line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are only active when data is desired from a
particular memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused
by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk

electrolytic capacitor should be used between V

CC

and VSS for each eight devices. The location

of the capacitor should be close to where the power supply is connected to the array.

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Preliminary

6

EN27LV010 / EN27LV010B

MODE SELECT TABLE

Mode CE OE PGM A0 A1 A9 V

PP

Output

Read

V

IL

V

IL

X

(2)

XX X

V

CC

D

OUT

Output Disable

V

IL

V

IH

XXXX

V

CC

High Z

Standby (TTL)

V

IH

XX XXX

V

CC

High Z

Standby (CMOS)

V

CC

± 0.3V

XX XXX

V

CC

High Z

Program

(4)

V

IL

V

IH

V

IL

XX X

V

PP

D

IN

Program Verify

V

IL

V

IL

V

IH

XX X

V

PP

D

OUT

Program Inhibit

V

IH

XX XXX

V

PP

High Z

Manufacturer Code

(3)

V

IL

V

IL

X

V

IL

V

IH

VH

(1)

V

CC

1C

Device Code

(3)

V

IL

V

IL

X

V

IH

V

IH

VH

(1)

V

CC

01

NOTES:

1) VH = 12.0V ± 0.5V

2) X = Either V

IH

or V

IL

3) For Manufacturer Code and Device Code, A1 = V

IH

When A1 = VIL, both codes will read 7F

4) See DC Programming Characteristics for V

PP

voltage during programming

EON’S STANDARD PRODUCT IDENTIFICATION CODE

Pins

Hex

Data

Code

A0 A1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Manufacturer

01000111001C

Device Type

110000000101

Continuation

00011111117F
10011111117F

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Preliminary

7

EN27LV010 / EN27LV010B

FIGURE 5. QUIKRITETM PROGRAMMING FLOW CHART

20

NOTE 1: Either 100µs or 20µs pulse.

NOTE 1

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EN27LV010 / EN27LV010B

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

-65àC to +125àC

Ambient Temperature

with Power Applied -40àC to +85àC

Voltage with Respect to V

SS

All pins except A9, VPP, V

CC

-0.6V to VCC + 0.5V

A9, V

PP

-0.6V to +13.5V

V

CC

-0.6V to +7.0V

OPERATING RANGES

Commercial (C)

Case Temperature(Tc) 0àC to +70àC

Industrial (I)

Case Temperature(Tc) -40àC to +85àC

Supply READ Voltages

(for battery operated systems)

+3.0V to +3.6V
+2.7V to +3.6V

(Functionality is guaranteed between these limits)

Stresses above those shown above may cause permanent damage to the device. This is a stress rating only and
operation above these specifications for extended periods may affect device reliability. Operation outside the

"OPERATING RANGES" shown above voids any and all warranty provisions.

DC CHARACTERISTICS FOR READ OPERATION

Symbol Parameter Min. Max. Unit Conditions

V

OH

Output High Voltage 2.4 V IOH = -2.0mA

V

OL

Output Low Voltage 0.45 V IOL = 2.0mA

V

IH

Input High Voltage 2.0 VCC +0.5 V

V

IL

Input Low Voltage -0.3 0.8 V

I

LI

Input Leakage Current -5 5 µA VIN = 0 to 3.6V

I

LO

Output Leakage Current -10 10 µA V

OUT

= 0 to 3.6V

I

CC3

VCC Power -Down Current 10 µA CE = VCC ± 0.3V

I

CC2

VCC Standby Current 0.6 mA CE = V

IH

I

CC1

VCC Active Current 15 mA

CE = VIL, f=5MHz,

I

OUT

= 0mA

I

PP1

VPP Supply Current Read 100 µA

CE = OE = VIL,

VPP = 3.6V

CAPACITANCE

Symbol Parameter Typ. Max. Unit Conditions

C

IN

Input Capacitance 8 12 pF VIN = 0V

C

OUT

Output Capacitance 8 12 pF V

OUT

= 0V

C

VPP

VPP Capacitance 18 25 pF VPP = 0V

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Preliminary

9

EN27LV010 / EN27LV010B

AC CHARACTERISTICS FOR READ OPERATION

EN27LV010
EN27LV010B

-90 -120

-120

-150

-150

-200

-200

Symbol Parameter Condition Min Max Min Max Min Max Min Max Unit

tACC (3) Address to

Output Delay

CE = OE =

V

IL

90 120 150 200

ns

tCE (2) CE to Output

Delay

OE = V

IL

90 120 150 200

ns

tOE (2, 3) OE to Output

Delay

OE = V

IL

45 45 50 50

ns

tDF (4, 5) OE or CE High to Output Float,

whichever occurred first

40 40 40 40

ns

tOH Output Hold from Address, CE

or

OE , whichever occurred first

000 0

ns

Note: Please contact Marketing Department for other speed requirements.

FIGURE 6. AC WAVEFORMS FOR READ OPERATION

CE

ADDRESS ADDRESS VALID

OE

OUTPUT

OUTPUT

VALID

tCE

tACC

HIGH Z

tOE

tDF

tOH

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Preliminary

10

EN27LV010 / EN27LV010B

FIGURE 7: TEST WAVEFORMS AND MEASUREMENTS

DC PROGRAMMING CHARACTERISTICS

Test Limits

Symbol Parameter Conditions Min. Max Units

I

LI

Input Load Current V

IN = VIL, VIH

5.0

µA

V

IL

Input Low Level -0.5 0.8 V

V

IH

Input High Level 0.7 V

CC

V

CC

+ 0.5 V

V

OL

Output Low Voltage I

OL =

2.0 mA 0.45 V

V

OH

Output High Voltage I

OH = -

400 µA 2.4 V

I

ccp

VCC Supply Current 40 mA

I

PP2

V

PP

Supply Current CE = PGM = V

IL,

10 mA

V

ID

A9 Product Identification Voltage 11.5 12.5 V

V

cc

Quikrite Supply Voltage 6.0 6.5 V

V

pp

Quikrite Programming Voltage 12.5 13.0 V

Input Test Waveform and Measurement Level

Output Test Load

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Preliminary

11

EN27LV010 / EN27LV010B

FIGURE 8. PROGRAMMING WAVEFORMS

ADDRESS

VIH
VIL

ADDRESS STABLE

DATA IN

PROGRAM

READ

(VERIFY)

DATA

VIH
VIL

DATA OUT

VALID

V

CC

6.5V

5.0V

V

PP

13.0V

5.0V

CE

VIH
VIL

PGM

VIH
VIL

OE

VIH
VIL

tAS tOE

tPRT

tDS tDH

tVCS

tVPS

tPW

tOES

tCES

tAH

tDFP

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12

EN27LV010 / EN27LV010B

SWITCHING PROGRAMMING CHARACTERISTICS
(TΑ = + 25 ° C ± 5 ° C)

PARAMETER
SYMBOL
STANDARD PARAMETER DESCRIPTION

Min. Max Units

t

AS

Address Setup Time 2

µs

t

OES

OE Setup Time 2 µs

t

DS

Data Setup Time 2 µs

t

AH

Address Hold Time 0 µs

t

DH

Data Hold Time 2 µs

t

DFP

Output Enable to Output Float Delay 0 130 ns

t

VPS

VPP Setup Time 2 µs

t

PW

PGM Program Pulse Width 20 105

µs

t

VCS

V

cc

Setup Time 2

µs

t

CES

CE Setup Time 2

µs

t

OE

Data Valid from OE 150

ns

ORDERING INFORMATION

EN27LV010 90 P I

TEMPERATURE RANGE

(Blank) = Commercial ( 0àC to +70àC)
I = Industrial ( -40àC to +85àC)

PACKAGE

P = 32 Plastic DIP
J = 32 Plastic PLCC
T = 32 Plastic TSOP

SPEED

90 = 90ns
120 = 120ns
150 = 150ns
200 = 200ns

BASE PART NUMBER

EN = EON Silicon Devices
27 = EPROM
LV = Low Voltage CMOS
010 = 128K x 8 3.0V to 3.6V Vcc Tolerance

010B = 128K x 8 2.7V to 3.6V Vcc Tolerance