The EN27C010 is a low-power 1-Megabit, 5V-only one-time-programmable (OTP) read-only
memory (EPROM). Organized into 128K words with 8 bits per word, it features QuikRite
address location programm ing, typically at 20µs per byte. Any byte can be accessed in less than
45ns, eliminating the need for W AIT states in high-performance microprocessor systems. The
EN27C010 has separate Output Enable (
OE ) and Chip Enable ( CE ) controls which eliminate
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Page 2
FIGURE 2. TSOP
TSOP
EN27C010
A11
A9
A8
A13
A14
NC
PGM
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EN27C010
FIGURE 3. PLCC
PLCC Top View
A12A16VCC
A15VPPPGM
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
4232
5
3131
6
7
8
9
10
11
12
13
151719
141618
30
20
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ2DQ3DQ5
DQ1VSSDQ4
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DQ6
Page 3
FIGURE 4. BLOCK DIAGRAM
EN27C010
CE
PGM
CONTROL
LOGIC
OE
Y-DECODERY-SELECT
A0-A16
ADDRESS
INPUTS
X-DECODER
VCC
VPP
VSS
FUNCTIONAL DESCRIPTION
1024
1024
INPUT/
OUTPUT
BUFFERS
8
1M BIT
CELL
MATRIX
8
DQ0 - DQ7
THE QUIKRITETM PROGRAMMING OF THE EN27C010
When the EN27C010 is delivered, the chip has all 1M bits in the “ONE”, or
HIGH state. “ZEROs” are loaded into the EN27C010 through the procedure of programming.
The programming mode is entered when 12.75 ± 0.25V is applied to the V
and
CE and PGM are at V
. For programming, the data to be pr ogramm ed is applied with 8
IL
bits in parallel to the data pins.
The QUIKRITE
TM
programming flowchart in Figure 5 shows Eon’s interactive programming
algorithm. The interactive algorithm reduces programming time by using 20 µs to 100 µs
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to a given address, the data in that
address is verified. If the data is not verified, additional pulses are given until it is verified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the EN27C010. This part of the programming algorithm is done at
V
= 6.25V to assure that each EPROM bit is programmed to a sufficiently high threshold
CC
voltage. This ensures that all bits have sufficient margin. After the final address is completed,
the entire EPROM memory is read at V
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CC
= V
= 5.25 ± 0.25V to verify the entire memory.
PP
3
pin, OE is at VIH,
PP
Page 4
EN27C010
PROGRAM INHIBIT MODE
Programming of multiple EN27C010 in parallel with different data is also easily accomplished
by using the Program Inhibit Mode. Except for
may be common. A TTL low-level program pulse applied to an EN27C010
V
= 12.75 ± 0.25V, PGM LOW, and OE HIGH will program that EN27C010. A high-level
PP
CE input inhibits the other EN27C010 from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determining that they were
correctly programmed. The verification should be performed with
V
, and VPP at it programming voltage.
IH
CE, all like inputs of the parallel EN27C010
CE input with
OE and CE at V
, PGM at
IL
AUTO PRODUCT IDENTIFICATION
The Auto Product Identification mode allows the reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode is intended for use by programming equipment
for the purpose of automatically matching the device to be programmed with its corresponding
programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range
that is required when programming the EN27C010.
To activate this mode, the programming equipment must force 12.0 V ± 0.5V on address line A9
of the EN27C010. Two identifier bytes may then be sequenced from the device outputs by
toggling address line A0 from V
V
during Auto Product Identification mode.
IL
Byte 0 (A0 = V
) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For
IL
the EN27C010, these two identifiers bytes are given in the Mode Select Table. All identifiers for
manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity
bit.
When A1 = VIL, the EN27C010 will read out the binary code of 7F, continuation code, to
signify the unavailability of manufacturer ID codes.
to VIH, when A1 = VIH. All other address lines must be held at
IL
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EN27C010
READ MODE
The EN27C010 has two control functions, both of which must be logically satisfied in order to
obtain data at the outputs. Chip Enable (
device selection. Output Enable (
the output pins, independent of device selection. Assuming that addresses are stable,
address access time (t
the outputs (t
addresses have been stable for at least t
) after the falling edge of OE , assuming the CE has been LOW and
OE
) is equal to the delay from CE to output (tCE) . Data is available at
ACC
STANDBY MODE
CE) is the power control and should be used for
OE) is the output control and should be used to gate data to
- tOE.
ACC
The EN27C010 has CMOS standby mode which reduces the maximum V
It is placed in CMOS standby when
standby mode which reduces the maximum V
standby when
state, independent of the
CE is at V
. When in standby mode, the outputs are in a high-impedance
IH
OE input.
CE is at V
± 0.3 V. The EN27C010 also has a TTL-
CC
current to 1.0 mA. It is placed in TTL-
CC
current to 20µA.
CC
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to allow
for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that
while
OE be made a common connection to all devices in the array and connected to the READ
line from the system control bus. This assures that all deselected memory devices are in their
low-power standby mode and that the output pins are only active when data is desired from a
particular memory device.
CE be decoded and used as the primary device-selection function,
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused
by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk
electrolytic capacitor should be used between VCC and VSS for each eight devices. The
location of the capacitor should be close to where the power supply is connected to the array.
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MODE SELECT TABLE
EN27C010
ModeCE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
(4)
Program Verify
Program Inhibit
Manufacturer Code
Device Code
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EN27C010
FIGURE 5. QUIKRITETM PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
VPP = 12.75V
X = 0
INTERACTIVE
SECTION
VERIFY
SECTION
INCREMENT ADDRESS
PROGRAM ONE 10µs PULSE
INCREMENT X
FAIL
NO
VERIFY BYTE?
LAST ADDRESS
VCC = VPP = 5.25V
VERIFY ALL BYTES?
20
X = 25?
NO
PASS
YES
YES
FAIL
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
NOTE 1: Either 100µs or 20µs pulse.
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ABSOLUTE MAXIMUM RATINGS
EN27C010
Storage Temperature
-65àC to +125àC
Ambient Temperature
with Power Applied-40àC to +85àC
Voltage with Respect to V
All pins except A9, VPP, V
A9, V
PP
V
CC
SS
CC
-0.6V to VCC + 0.5V
-0.6V to +13.5V
-0.6V to +7.0V
OPERATING RANGES
Commercial (C)
Case Temperature(Tc)0àC to +70àC
Industrial (I)
Case Temperature(Tc)-40àC to +85àC
Supply READ Voltages
+4.50V to +5.5V
(Functionality is guaranteed between these limits)
Stresses above those shown above may cause permanent damage to the device. This is a stress rating only and
operation above these specifications for extended periods may affect device reliability. Operation outside the
"OPERATING RANGES" shown above voids any and all warranty provisions.
DC CHARACTERISTICS FOR READ OPERATION
SymbolParameterMin.Max.UnitConditions
V
V
V
V
I
I
I
I
I
I
OH
OL
IH
IL
LI
LO
CC3
CC2
CC1
PP
Output High Voltage2.4VIOH = -0.4mA
Output Low Voltage0.45VIOL = 2.1mA
Input High Voltage2.0
+0.5
V
CC
V
Input Low Voltage-0.30.8V
Input Leakage Current-55
Output Leakage Current-1010
µA
µA
VIN = 0 to 5.5V
V
= 0 to 5.5V
OUT
VCC Power -Down Current10µACE = VCC ± 0.3V
VCC Standby Current1.0mACE = V
IH
VCC Active Current30mACE = VIL, f=5MHz,
I
= 0mA
OUT
VPP Supply Current Read100µACE = OE = VIL,
VPP = 5.5V
CAPACITANCE
SymbolParameterTyp.Max.UnitConditions
C
IN
C
OUT
C
VPP
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