Datasheet EM638165 Datasheet

EtronTech

EM638165

4Mega x 16 Synchronous DRAM (SDRAM)

Preliminary (Rev 0.6, 2/2001)

Features

Fast access time from clock: 5/6/6/6/7 ns

•

Fast clock rate: 166/143/133/125/100 MHz

•

Fully synchronous operation

•

Internal pipelined architecture

•

1M word x 16-bit x 4-bank

•

Programmable Mode registers

•

- CAS# Latency: 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst stop function
Auto Refresh and Self Refresh

•

4096 refresh cycles/64ms

•

CKE power down mode

•

Single +3.3V ± 0.3V power supply

•

Interface: LVTTL

•

54-pin 400 mil plastic TSOP II package

•

Overview

The EM638165 SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.

The EM638165 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.

By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.

Pin Assignment (Top View)

VDD

DQ0

VDDQ

DQ1
DQ2

VSSQ

DQ3
DQ4

VDDQ

DQ5
DQ6

VSSQ

DQ7

VDD

LDQM

WE#
CAS#
RAS#

CS#
BA0
BA1

A10/AP

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS

Key Specifications

EM638165

Clock Cycle time(min.)

t

CK3

Access time from CLK(max.)

t

AC3

Row Active time(max.)

t

RAS

Row Cycle time(min.)

t

RC

-

6/7/7.5/8/10

6/7/7.5/8/10 ns

5/5.4/5.4/6/7 ns
42/45/45/48/50 ns
60/63/68/70/80 ns

Ordering Information

Part Number Frequency

EM638165TS-6
EM638165TS-7
EM638165TS-7.5

166MHz TSOP II
143MHz TSOP II

133MHz TSOP II
EM638165TS-8 125MHz TSOP II
EM638165TS-10 100MHz TSOP II

Package

Etron Technology, Inc.

No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: [phone] FAX: [phone]

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

EtronTech

Block Diagram

CLOCK

CKE

CS#
RAS#
CAS#

WE#

UDQM

LDQM

COMMAND

CLOCK

CLOCL

BUFFER

BUFFER

DECODER

COLUMN

COUNTER

EM638165

1MX16

CELL ARRAY

Decoder

CONTROL

SIGNAL

GENERATOR

(BANK #A)

Column Decoder

Buffer

DQ0

|

DQ15

A0

~

A11
BA0
BA1

ADDRESS

BUFFER

REFRESH

COUNTER

MODE

REGISTER

1MX16

CELL ARRAY

Decoder

(BANK #B)

Column Decoder

1MX16

CELL ARRAY

Decoder

(BANK #C)

Column Decoder

1MX16

CELL ARRAY

Decoder

(BANK #D)

Preliminary

2

Column Decoder

Rev 0.6 Feb. 2001

EtronTech

CLK is driven by the system clock. All SDRAM input signals are

nal burst

CKE activates(HIGH) and deactivates(LOW) the CLK signal. If

up and hold time same as other

the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power

ter the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low

A11 are sampled during the BankActivate command (row

A7 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if

dress inputs also provide

CS# enables (sampled LOW) and disables (sampled HIGH) the

command decoder. All commands are masked when CS# is sampled HIGH.

lection on systems with multiple banks. It is

The RAS# signal defines the operation commands in

conjunction with the CAS# and WE# signals and is latched at the positive edges

RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the

ned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the

n commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command

EM638165

Pin Descriptions

Symbol Type Description

CLK Input

CKE Input

BA0,BA1 Input

Table 1. Pin Details of EM638165

Clock:

sampled on the positive edge of CLK. CLK also increments the inter
counter and controls the output registers.

Clock Enable:

CKE goes low synchronously with clock(set­inputs), the internal clock is suspended from

Down and Self Refresh modes. CKE is synchronous except af

standby power.

Bank Select:

BA0,BA1 input select the bank for operation.

BA1 BA0 Select Bank

0 0 BANK #A
0 1 BANK #B
1 0 BANK #C
1 1 BANK #D

A0-A11 Input

CS# Input

RAS# Input

CAS# Input

Address Inputs:

address A0-A11) and Read/Write command (column address A0-

all banks are to be precharged (A10 = HIGH). The ad
the op-code during a Mode Register Set command.

Chip Select:

CS# provides for external bank se
considered part of the command code.

Row Address Strobe:

of CLK. When

BankActivate command is selected and the bank designated by BS is tur

precharge operation.

Column Address Strobe:

A0-

The CAS# signal defines the operatio

Preliminary

3

is selected by asserting WE# "LOW" or "HIGH."

Rev 0.6 Feb. 2001

EtronTech

EM638165

The WE# signal defines the operation commands in conjunction

with the RAS# and CAS# signals and is latched at the positive edges of CLK.

mand and

15 input and output data are synchronized with the positive

WE# Input

LDQM,
UDQM

DQ0-DQ15

NC/RFU -

V

DDQ

V

SSQ

V

DD

V

SS

Input

Input /

Output

Supply

Supply

Supply
Supply

Write Enable:

The WE# input is used to select the BankActivate or Precharge com
Read or Write command.

Data Input/Output Mask:

Input data in write mode.

Data I/O:

edges of CLK. The I/Os are maskable during Reads and Writes.

No Connect:
DQ Power:

( 3.3V± 0.3V )

DQ Ground:

( 0 V )

Power Supply:
Ground

The DQ0-

These pins should be left unconnected.

Provide isolated power to DQs for improved noise immunity.

Provide isolated ground to DQs for improved noise immunity.

+3.3V ± 0.3V

Controls output buffers in read mode and masks

Preliminary

4

Rev 0.6 Feb. 2001

EtronTech

EM638165

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 2 shows the truth table for the operation commands.

Table 2. Truth Table (Note (1), (2) )

BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit

Clock Suspend Mode Entry
Power Down Mode Entry

Clock Suspend Mode Exit
Power Down Mode Exit

Data Write/Output Enable
Data Mask/Output Disable

Note:

1. V=Valid X=Don't Care L=Low level H=High level

2. CKEn signal is input level when commands are provided.

3. These are states of bank designated by BS signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.

Command State CKE

(3)

Idle

Any H X X V L X L L H L
Any H X X X H

(3)

Active

(3)

Active

(3)

Active

(3)

Active

Idle H X X OP code L L L L
Any H X X X X

(4)

Active

Any H X X X X
Idle H H X X X
Idle H L X X X
Idle L H X X X

(SelfRefresh)

Active

(5)

Any

Active

Any L H X X X

(PowerDown)

Active
Active

CKE

signal is input level one clock cycle before the commands are provided.

n-1

n-1

CKE

DQM BA

n

0,1

A

10

A

0-9,11

CS# RAS# CAS# WE#

H X X V Row address L L H H

X L L H L
H X X V L L H L L
H X X V H
H X X V L L H L H
H X X V H

Column
address

(A0 ~ A7)

Column
address

(A0 ~ A7)

L H L L

L H L H

X L H H H
H X X X X

X L H H L

X H

X X X
X L L L H
X L L L H

H L X X X
H L X X X

X H

X X
X H

X X X

L H H H

X X X

X X X

L H H H

L H X X X

H X L X X
H X H X X

X X
X H

X X
X X

X X X

X X X

L H H H

X X X

X X X

Preliminary

5

Rev 0.6 Feb. 2001

EtronTech

EM638165

Commands

1 BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)

The BankActivate command activates the idle bank designated by the BA0,1 signals. By

latching the row address on A0 to A11 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of t
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of the four banks. t
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.

(min.) specifies the minimum time required between activating

RRD

T0 T 1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6

RCD

(min.)

CLK

ADDRESS

COM M A ND

Bank A

Row Addr.

Bank A

Activate

RAS# - CAS# delay (tRCD)

: "H" or "L"

BankActivate Command Cycle

2 BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)

The BankPrecharge command precharges the bank disignated by BA signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
t

(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any

RAS

bank can be active is specified by t
in any active bank within t
state and is ready to be activated again.

3 PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0 -A9 and A11 = Don't care)

The PrechargeAll command precharges all banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.

NOP

..............

NOP

Bank A

Col Addr.

R/W A with

AutoPrecharge

RAS# Cycle time (tRC)

..............

..............

(Burst Length = n, CAS# Latency = 3)

(max.). Therefore, the precharge function must be performed

RAS

(max.). At the end of precharge, the precharged bank is still in the idle

RAS

Bank B

Row Addr.

Bank B

Activate

AutoPrecharge

Begin

RAS# - RAS# delay time (tRRD)

NOP

NOP

Row Addr.

Bank A

Bank A

Activate

4 Read command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A7 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data­out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).

Preliminary

6

(min.) before the Read command is

RCD

Rev 0.6 Feb. 2001

EtronTech

CLK

EM638165

T0 T 1 T2 T3 T4 T5 T6 T7 T8

COMMAND

CAS# latency=2
t

, DQ's

CK2

CAS # latency=3
t

, DQ's

CK3

(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write command to the same bank or the other active
bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).

CLK

COMMAND

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

READ A NOP

NOP NOP NOP NOP NOP NOP NOP

DOUT A

DOUT A

0

DOUT A0DOUT A

DOUT A2DOUT A

1

DOUT A2DOUT A

1

3

3

Burst Read Operation

(Burst Length = 4, CAS# Latency = 2, 3)

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier

T0 T 1 T2 T3 T4 T5 T6 T7 T8

READ A READ B NOP NOP NOP NOP NOP NOP NOP

DOUT A0DOUT B

DOUT A0DOUT B

DOUT B1DOUT B

0

DOUT B1DOUT B

0

DOUT B

2

3

DOUT B

2

3

from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following three figures). If the data output of the burst read occurs at
the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to
the Write command to avoid internal bus contention.

CLK

DQM

COM M AND

DQ's

: "H" or "L"

Read Interrupted by a Read

(Burst Length = 4, CAS# Latency = 2, 3)

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP

READ A NOP NOP NOP NOP WRIT E B NOP NOP

DOUT A

Read to Write Interval

0

Must be Hi-Z before
the Write Command

(Burst Length ≥ 4, CAS# Latency = 3)

DINB

0

DINB

DINB

1

2

Preliminary

7

Rev 0.6 Feb. 2001

EtronTech

EM638165

T0 T 1 T2 T3 T4 T5 T6 T7 T8

CLK

DQM

COMMAND

CAS# latency=2
t

, DQ's

CK2

: "H" or "L"

CLK

DQM

COMMAND

CAS# latency=2
t

, DQ's

CK2

: "H" or "L"

1 Clk Interval

NOP NOP NOP NOP NOP NOP

Read to Write Interval

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP

NOP

BANKA

ACTIVATE

READ A

(Burst Length ≥ 4, CAS# Latency = 2)

NOP WRITE B NOP NOP NOP

READ A

NOP

WRIT E A

DIN A

DIN B

DIN A

0

0

DIN B

1

1

DIN A

DIN B

DIN A

2

DIN B

2

3

3

Read to Write Interval

CLK

ADDRESS

COMMAND

CAS # latency=2
t

CK2

CAS # latency=3
t

CK3

A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.

T0 T 1 T2 T3 T4 T5 T6 T7 T8

Bank,

Col A

READ A

, DQ's

, DQ's

NOP

Read to Precharge

5 Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A7 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in
this command and the auto precharge function is ignored.

(Burst Length ≥ 4, CAS# Latency = 2)

Bank(s)

NOP Precharge

DOUT A

NOP

DOUT A

0

DOUT A

DOUT A

1

DOUT A

0

(CAS# Latency = 2, 3)

Bank,

tRP

NOP

DOUT A

2

DOUT A

1

NOP

3

DOUT A

2

Row

Activate

3

NOP

Preliminary

8

Rev 0.6 Feb. 2001

EtronTech

6 Write command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).

CLK

EM638165

(min.) before the Write command is

RCD

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

COM M A ND

DQ0 - DQ3

BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).

CLK

COM MAND

DQ's

issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.

NOP WRITE A

DIN A

0

The first data element and the write
are registered on the same clock edge.

NOP NOP

DIN A

Burst Write Operation

NOP

DIN A

1

DIN A

2

3

Extra data is masked.

NOP

don't care

(Burst Length = 4, CAS# Latency = 1, 2, 3)

NOP

NOP

NOP

A write burst without the auto precharge function may be interrupted by a subsequent Write,

T0 T 1 T2 T3 T4 T5 T6 T 7 T8

NOP WRITE A

1 Clk Interval

DIN A

WRITE B NOP

DIN B

0

NOP

DIN B

0

NOP

DIN B

1

DIN B

2

3

NOP

NOP

NOP

Write Interrupted by a Write

The Read command that interrupts a write burst without auto precharge function should be

(Burst Length = 4, CAS# Latency = 1, 2, 3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

NOP WRIT E A

Write Interrupted by a Read

Preliminary

9

READ B NOP

DIN A

DIN A

Input data for the write is masked.

don't care

0

don't care don't care

0

NOP

NOP

DOUT B

Input data must be removed from the DQ's at least one clock
cycle before the Read data appear s on the outputs to avoid
data contention.

DOUT B

0

DOUT B

NOP

DOUT B

DOUT B

2

1

1

0

(Burst Length = 4, CAS# Latency = 2, 3)

Rev 0.6 Feb. 2001

NOP

DOUT B

DOUT B

NOP

3

DOUT B

2

3

EtronTech

EM638165

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).

T0 T 1 T2 T3 T4 T5 T6

CLK

DQM

t

RP

COMMAND

WRITE

NOP

NOPPrecharge NOP NOP Activate

ADDRESS

DQ

BANK
COL n

DIN

n

DIN
n + 1

BANK (S)

t

WR

ROW

: don't care

Note:

The DQMs can remain low in this example if the length of the write burst is 1 or 2.

Write to Precharge

7 Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",

A0-A7 = Column Address)

CLK

COMMAND

CAS# latency=2
t

CK2

CAS# latency=3
t

CK3

The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.

T0 T 1 T2 T3 T4 T5 T6 T7 T8

, DQ's

, DQ's

Bank A

Activate

NOP NOP

NOP NOP

Write A

AutoPrecharge

DIN A

0

DIN A

0

DIN A

DIN A

NOP

tDAL

1

*

tDAL

1

*

NOP

NOP

DAL= tWR + tRP

t

Burst Write with Auto-Precharge

8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as all banks are in the idle
state.

Preliminary

10

Begin AutoPrecharge
Bank can be rea ctivated at completion of

*

DAL

t

(Burst Length = 2, CAS# Latency = 2, 3)

Rev 0.6 Feb. 2001

EtronTech

CLK

CKE

CS#

RAS#

CAS#

WE#

A 11

A 10

EM638165

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10

t

CK2

Clock min.

Address Key

A0-A9

DQM

tRP

Mode Register

Set Command

Any
Command

(CAS# Latency = 2, 3)

DQ

Hi-Z

PrechargeAll

Mode Register Set Cycle

The mode register is divided into various fields depending on functionality.

Address BS0,1 A11,10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU* RFU* WBL Test Mode

CAS Latency BT Burst Length

*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.

Burst Length Field (A2~A0)

•

This field specifies the data length of column access using the A2~A0 pins and selects the Burst
Length to be 2, 4, 8, or full page.

A2 A1 A0 Burst Length

0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page

Preliminary

11

Rev 0.6 Feb. 2001

EtronTech

EM638165

2 words:

Burst Type Field (A3)

•

The Burst Type can be one of two modes, Interleave Mode or Sequential Mode.

A3 Burst Type

0 Sequential
1 Interleave

--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which

is input to the device. The internal column address is varied by the Burst Length as shown in the
following table. When the value of column address, (n + m), in the table is larger than 255, only the
least significant 8 bits are effective.

Data n 0 1 2 3 4 5 6 7 - 255 256 257 -

Column Address

--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address

bits in the sequence shown in the following table.

Data n
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0#
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#

Burst Length 4 words:

n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -

8 words:

Full Page: Column address is repeated until terminated.

Column Address Burst Length

8 words

CAS# Latency Field (A6~A4)

•

This field specifies the number of clock cycles from the assertion of the Read command to the first
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The
minimum whole value satisfying the following formula must be programmed into this field.

t

(min) ≤ CAS# Latency X t

CAC

A6 A5 A4 CAS# Latency

0 0 0 Reserved
0 0 1 Reserved
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved

Preliminary

12

CK

Rev 0.6 Feb. 2001

EtronTech

EM638165

Test Mode field (A8~A7)

•

These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.

A8 A7 Test Mode

0 0 normal mode
0 1 Vendor Use Only
1 X Vendor Use Only

Write Burst Length (A9)

•

This bit is used to select the burst write length.

A9 Write Burst Length

0 Burst
1 Single Bit

9 No-Operation command

(RAS# = "H", CAS# = "H", WE# = "H")

The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS#

is Low). This prevents unwanted commands from being registered during idle or wait states.

10 Burst Stop command

(RAS# = "H", CAS# = "H", WE# = "L")

The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.

T0 T 1 T2 T3 T4 T5 T6 T7 T8

CLK

COMMAND

CAS# latency=2
t

, DQ's

CK2

CAS# latency=3
t

, DQ's

CK3

READ A

NOP

NOP Burst Stop

DOUT A

0

Termination of a Burst Read Operation

T0 T 1 T2 T3 T4 T5 T6 T7 T8

NOP

DOUT A1DOUT A

DOUT A

DOUT A

0

(Burst Length ¡Ö 4, CAS# Latency = 2, 3)

NOP

The burst ends after a delay equal to the CAS# latency.

DOUT A

2

DOUT A

1

NOP

3

DOUT A

2

NOP

3

NOP

CLK

COMMAND

CAS# latency= 2, 3
DQ's

NOP WRITE A

Termination of a Burst Write Operation

Preliminary

13

DIN A

NOP Burst Stop

DIN A

0

1

NOP

DIN A

don't care

2

Input data for the Write is masked.

NOP

NOP

NOP

NOP

(Burst Length = X, CAS# Latency = 1, 2, 3)

Rev 0.6 Feb. 2001

EtronTech

EM638165

11 Device Deselect command (CS# = "H")

12 AutoRefresh command

(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0 -A9 = Don't care)

13 SelfRefresh Entry command

(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)

The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.

The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.

The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited
by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).

14 SelfRefresh Exit command

15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")

16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")

17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")

This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.

When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.

When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. t
subsequent commands can be issued after one clock cycle from the end of this command.

During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system.

(min.) is required when the device exits from the PowerDown mode. Any

PDE

Preliminary

14

Rev 0.6 Feb. 2001

EtronTech

EM638165

Absolute Maximum Rating

Symbol Item Rating Unit Note

P

I

OUT

OPR
STG

D

OUT

DDQ

Input, Output Voltage - 1.0 ~ 4.6 V 1

Power Supply Voltage -1.0 ~ 4.6 V 1

Operating Temperature 0 ~ 70 °C 1

Storage Temperature - 55 ~ 125 °C 1

Soldering Temperature (10 second) 255 °C 1

Short Circuit Output Current 50 mA 1

VIN, V

VDD, V

T
T

T

SOLDER

Recommended D.C. Operating Conditions (Ta = -40~85°C)

Symbol

V

DD

V

DDQ

V

IH

V

IL

Power Supply Voltage(for I/O Buffer)

LVTTL Input High Voltage 2.0

LVTTL Input Low Voltage - 0.3

Parameter Min. Typ. Max. Unit Note

Power Supply Voltage 3.0 3.3 3.6 V 2

Power Dissipation 1 W 1

3.0 3.3 3.6 V 2

¡Ð
¡Ð

4.6 V 2

0.8 V 2

Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)

Symbol Parameter Min. Max. Unit

C

I

C

I/O

Input Capacitance 2
Input/Output Capacitance

4

5 pF

6.5 pF

Note: These parameters are periodically sampled and are not 100% tested.

Preliminary

15

Rev 0.6 Feb. 2001

EtronTech

EM638165

Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0~70°C)

- 6/7/7.5/8/10
Max.

85 3

20
15

2 3

1
30
25

100 3, 4
130 3

1

Description/Test condition Symbol

Operating Current

t

≥ tRC(min), Outputs Open

RC

Precharge Standby Current in non-power down mode

t

= 15ns, CS# ≥ VIH(min), CKE ≥ V

CK

Precharge Standby Current in non-power down mode

tCK = ∞, CLK ≤ VIL(max), CKE ≥ V

Precharge Standby Current in power down mode

IH

IH

tCK = 15ns, CKE ≤ VIL(max)
Precharge Standby Current in power down mode

tCK = ∞, CKE ≤ VIL(max)
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CS# ≥ VIH(min), tCK = 15ns
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Operating Current (Burst mode)
t

CK =tCK

(min), Outputs Open, Multi-bank interleave
Refresh Current
t

≥ tRC(min)

RC

Self Refresh Current
V

≥ V

- 0.2, 0V ≤ VIL ≤ 0.2V

IH

DD

Parameter

Description Min. Max. Unit Note

I

DD1

I

DD2N

I

DD2NS

I

DD2P

I

DD2PS

I

DD3N

I

DD3NS

I

DD4

I

DD5

I

DD6

Unit

mA

Note

3

I

IL

Input Leakage Current

- 1 1

A

µ

( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )

I

OL

V

OH

V

OL

Output Leakage Current

Output disable, 0V ≤ V

OUT

≤ V

DDQ

LVTTL Output "H" Level Voltage

( I

= -2mA )

OUT

LVTTL Output "L" Level Voltage

( I

= 2mA )

OUT

)

- 1 1

2.4

¡Ð

¡Ð

0.4 V

µ

V

A

Preliminary

16

Rev 0.6 Feb. 2001

EtronTech

EM638165

Electrical Characteristics and Recommended A.C. Operating Conditions

(VDD = 3.3V

¡Ó

0.3V, Ta = -40~85°C) (Note: 5, 6, 7, 8)

Symbol

t

RC

Row cycle time

A.C. Parameter

(same bank)

t

RCD

RAS# to CAS# delay

(same bank)

t

Precharge to refresh/row activate command

RP

(same bank)

t

RRD

Row activate to row activate delay

(different banks)

t

RAS

Row activate to precharge time

(same bank)

t

WR

t

CCD

t

CK2

t

CK3

t

CH

t

CL

t

AC2

t

AC3

t

OH

t

LZ

t

HZ

t

IS

t

IH

t

PDE

Write recovery time

CAS# to CAS# Delay time

Clock cycle time

Clock high time

Clock low time

Access time from CLK

(positive edge)

Data output hold time

Data output low impedance

Data output high impedance

Data/Address/Control Input set-up time

Data/Address/Control Input hold time

Power Down Exit set-up time

CL* = 2
CL* = 3

CL* = 2
CL* = 3

-

6/7/7.5/8/10

Min. Max. Unit Note

60/63/68/70/80

18/20/20/20/24

18/20/20/20/24

12/14/15/20/25

42/45/45/48/50

2

ns

CLK

1

- / - /10/10/13
6/7/7.5/8/10

2/2.5/2.5/3/3
2/2.5/2.5/3/3

- / - /6/6/7
5/5.4/5.4/6/7

ns

2.5/2.7/3/3/3 9
1

5/5.4/5.4/6/7

1/1.5/1.3/2/2.5

1/0.8/0.8/0.8/0.8

10
10

8

6/7/7.5/8/10

9

10
10
10

*

CL is CAS# Latency.

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.

2. All voltages are referenced to VSS.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.

4. These parameters depend on the output loading. Specified values are obtained with the output open.

5. Power-up sequence is described in Note 11.

Preliminary

17

Rev 0.6 Feb. 2001

EtronTech

6. A.C. Test Conditions

LVTTL Interface

Reference Level of Output Signals 1.4V / 1.4V

Output Load Reference to the Under Output Load (B)

Input Signal Levels 2.4V / 0.4V

EM638165

Transition Time (Rise and Fall) of Input Signals

3.3V

1.2k

870

Ω

Ω

Output

Z0=

50

Reference Level of Input Signals 1.4V

Output

30pF

LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B)

7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a
fixed slope (1 ns).

8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.

9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.

1ns

1. 4V

50Ω

Ω

30pF

10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns

should be added to the parameter.

11. Power up Sequence

Power up must be performed in the following sequence.

1) Power must be applied to VDD and V

and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.

2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQM

is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.

3) All banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of

the device.

Preliminary

18

(simultaneously) when all input signals are held "NOP" state

DDQ

Rev 0.6 Feb. 2001

EtronTech

EM638165

Timing Waveforms

Figure 1. AC Parameters for Write Timing

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCL

CKE

CS#

RAS#

CAS#

CH

t

tIS

tIS
tIH

tCK2

Begin AutoPrecharge

Bank A

(Burst Length=4, CAS# Latency=2)

Begin AutoPrecharge

Bank B

tIS

WE#

BA0,1

A 10

A0-A9,A11

DQM

DQ

Hi-Z

IH

t

RAx

IS

t

RBx

CAx

tRCD

Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3

Activate

Command

Bank A

Write with

AutoPrecharge

Command

Bank A

RBx

RBx

RC

t

Activate

Command

Bank B

CBx RAy

DAL

t

Write with

AutoPrecharge

Command

Bank B

RAy

Activate

Command

Bank A

t

IS

CAy

Write

Command

Bank A

tIH

WR

t

Precharge
Command

Bank A

RP

t

RAz

RAz

Activate

Command

Bank A

t

RRD

RBy

RBy

Activate

Command

Bank B

Preliminary

19

Rev 0.6 Feb. 2001

EtronTech

EM638165

Ban

k B

Figure 2. AC Parameters for Read Timing

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13

CLK

(Burst Length=2, CAS# Latency=2)

CKE

CS#

RAS#

CAS#

WE#

BA0 ,1

A10

A 0-A9,A11

DQM

DQ

Hi-Z

tCH

tIS

tI S

t

CK2

tI H

Begin AutoPrecharge

Bank B

tIH

t

CL

tIH

RAx

t

IS

RAx

CAx RBx

RBx

CBx

RAy

RAy

tRRD

tRAS

tRC

t

AC2

tRCD

tLZ

Ax0

tAC2

tHZ

Ax1

t

RP

Bx0 Bx1

Preliminary

20

Activate

Command

Bank A

Read

Command

Bank A

t

Activate

Command

Bank B

OH

Read with

Auto Precharge

Command

Precharge
Command

Bank A

tHZ

Activate

Command

Bank A

Rev 0.6 Feb. 2001

EtronTech

Bank A

Figure 3. Auto Refresh (CBR)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CA S#

EM638165

(Burst Length=4, CAS# Latency=2)

WE#

BA0,1

A 10

A0 -A9,A11

DQM

DQ

PrechargeAll

Command

tRP

AutoRefresh

Command

RAx

RAx CAx

RC

t

AutoRefresh

Command

RC

t

Activate

Command

Read

Command

Bank A

Ax0

Ax1

Ax2

Ax3

Preliminary

21

Rev 0.6 Feb. 2001

EtronTech

EM638165

sta

ble fo

r 200

µs

Figure 4. Power on Sequene and Auto Refresh (CBR)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T 18 T 19 T 20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CAS#

WE#

High level
is reauired

Minimum of 2 Refresh Cycl es are required

BA0,1

A10

A0-A9,A11

DQM

DQ

Hi-Z

Inputs must be

PrechargeA LL

Command

Address Key

tRP

1st AutoRefresh

Mode Register
Set Command

Command

2nd Auto Refresh

Command

tRC

Any

Command

Preliminary

22

Rev 0.6 Feb. 2001

EtronTech

EM638165

T0T1T2T3T4T5T6T7T8T9T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

Sel

f Refr

esh En

ter

Self

Refresh

Exit

Aut

oRef

resh

Figure 5. Self Refresh Entry & Exit Cycle

CLK

CKE

CS#

RAS#

C AS#

B A0,1

A 0-A9,A11

WE#

*Note 1

*Note 8

tIS

*Note 2

*Note 3

*Note 4

tRC(min) *Note 7

SRX

t

*Note 5

*Note 6

tPDE

*Note 8

DQM

DQ

Hi-Z

Hi-Z

Note: To Enter SelfRefresh Mode

1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in SelfRefresh mode as long as CKE stays "low".

Once the device enters SelfRefresh mode, minimum t

is required before exit from SelfRefresh.

RAS

To Exit SelfRefresh Mode

1. System clock restart and be stable before returning CKE high.

2. Enable CKE and CKE should be set high for minimum time of t

SRX

.

3. CS# starts from high.

4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.

5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the

system uses burst refresh.

Preliminary

23

Rev 0.6 Feb. 2001

EtronTech

EM638165

Figure 6.1. Clock Suspension During Burst Read (Using CKE)

CLK

CKE

CS#

RAS#

CAS#

WE#

(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22

CK1

t

BA0,1

A10

A0-A9 ,A11

DQM

DQ

Hi-Z

Note:

CKE to CLK disable/enable = 1 clock

RAx

RAx CAx

Activate

Command

Bank A

Command

Ax0 Ax1

Read

Bank A

Clock Suspend

1 Cycle

Ax2

Clock Suspend

2 Cycles

tHZ

Ax3

Clock Suspend

3 Cycles

Preliminary

24

Rev 0.6 Feb. 2001

EtronTech

EM638165

Figure 6.2. Clock Suspension During Burst Read (Using CKE)

CLK

CKE

CS#

RAS#

CAS#

(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK2

WE#

BA0,1

A10

A0-A9 ,A11

DQM

Hi-Z

DQ

Note:

CKE to CLK disable/enable = 1 clock

RAx

RAx

Activate

Command

Bank A

CAx

Read

Command

Bank A

Ax0 Ax1

Clock Suspend

1 Cycle

Ax2

Clock Suspend

2 Cycles

Ax3

Clock Suspend

3 Cycles

HZ

t

Preliminary

25

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Bank A

Figure 6.3. Clock Suspension During Burst Read (Using CKE)

(Burst Length=4, CAS# Latency=3)

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

A0-A9 ,A11

T0 T 1 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

RAx

RAx

T 2

tCK3

CAx

DQM

Hi-Z

DQ

Activate

Command

Note:

CKE to CLK disable/enable = 1 clock

Read

Command

Ax0 Ax1 Ax2

Clock Suspend

1 Cycle

Clock Suspend

2 Cycles

Ax3

Clock Suspend

3 Cycles

tHZ

Preliminary

26

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 7.1. Clock Suspension During Burst Write (Using CKE)

CLK

CKE

CS#

RAS#

CAS#

(Burst Length = 4, CAS# Latency = 1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK1

WE#

BA0,1

A10

A0-A9 ,A11

DQM

DQ

Hi-Z

Note:

CKE to CLK disable/enable = 1 clock

RAx

RAx CAx

Activate

Command

Bank A

Command

DAx0

Clock Suspend

Write

1 Cycle

DAx1

Clock Suspend

2 Cycles

DAx2 DAx3

Clock Suspend

3 Cycles

Preliminary

27

Rev 0.6 Feb. 2001

EtronTech

EM638165

Figure 7.2. Clock Suspension During Burst Write (Using CKE)

CLK

CKE

CS#

RAS#

CAS#

WE#

(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

tCK2

T2
2

BA0,1

A 10

A0-A9,A11

DQM

Hi-Z

DQ

Note:

CKE to CLK disable/enable = 1 clock

RAx

RAx CAx

Activate

Command

Bank A

DAx0

Write

Command

Bank A

Clock Suspend

1 Cycle

DAx1

Clock Suspend

2 Cycles

DAx2 DAx3

Clock Suspend

3 Cycles

Preliminary

28

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 7.3. Clock Suspension During Burst Write (Using CKE)

CLK

CKE

CS#

RAS#

CAS#

WE#

(Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK3

BA0,1

A10

A0-A9 ,A11

DQM

DQ

Hi-Z

Note:

CKE to CLK disable/enable = 1 clock

RAx

RAx

Activate

Command

Bank A

CAx

DAx0

Write

Command

DAx1

Clock Suspend

1 Cycle

Clock Suspend

2 Cycles

DAx2 DAx3

Clock Suspend

3 Cycles

Preliminary

29

Rev 0.6 Feb. 2001

EtronTech

EM638165

Mode

Entry

Figure 8. Power Down Mode and Clock Mask

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CA S#

tIS

(Burst Lenght=4, CAS# Latency=2)

t

PDE

Valid

WE#

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

Power Down

Mode Entry

ACTIVE

STANDBY

Command

Bank A

Power Down

Mode Exit

CAx

Read

Ax0

Clock Mask

Ax1

Start

Ax2

Clock Mask

End

t

HZ

Ax3

Precharge
Command

Bank A

Power Down

PRECHARGE

STANDBY

Power Down

Mode Exit

Any

Command

Preliminary

30

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 9.1. Random Column Read (Page within same Bank)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK1

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAw

RAw

Activate

Command

Bank A

Command

CAw

Aw0 Aw1 Aw2 Aw3Ax0 Ax1

Command

Read

CAx

Read

Bank A

CAy

Read

Command

Bank A

Ay0

Ay1Ay2 Ay3

Precharge
Command

Bank A

RAz

RAz

Activate

Command

Bank A

CAz

Read

Command

Bank A

Az0

Az1Az2 Az3

Preliminary

31

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Bank A

Bank A

Bank A

Bank A

Bank A

Bank A

Figure 9.2. Random Column Read (Page within same Bank)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK2

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAw

RAw

Activate

Command

CAw CAx

Aw0 Aw1 Aw2 Aw3 Ax0 Ax1

Read

Command

Read

Command

CAy

Read

Command

Ay0

Ay1 Ay2 Ay3

Precharge
Command

RAz

RAz

Activate

Command

CAz

Read

Command

Az0

Az1 Az2 Az3

Preliminary

32

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Bank A

Bank A

Bank A

Bank A

Bank A

Bank A

Figure 9.3. Random Column Read (Page within same Bank)

CLK

CKE

CS#

RAS#

CA S#

(Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK3

WE#

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAw

RAw

Activate

Command

CAw

Read

Command

CAx

Aw0 Aw1 Aw2 Aw3 Ax0 Ax1

Read

Command

CAy

Read

Command

Ay0

Ay1 Ay2 Ay3

Precharge
Command

RAz

RAz

Activate

Command

CAz

Read

Command

Az0

Preliminary

33

Rev 0.6 Feb. 2001

EtronTech

EM638165

Ban

k B

Ban

k B

Figure 10.1. Random Column Write (Page within same Bank)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK1

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RBw

CBw

RBw

DBw0DBw1DBw2 DBw3 DBx0 DBx1

Activate

Command

Bank A

Write

Command

CBx

Write

Command

Bank A

CBy

DBy0

Write

Command

Bank B

DBy1 DBy2 DBy3

Precharge
Command

Bank B

RBz

RBz

Activate

Command

CBz

DBz1 DBz2 DBz3

DBz0

Write

Command

Bank B

Preliminary

34

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Ban

k B

Ban

k B

Ban

k B

Ban

k B

Ban

k B

Ban

k B

Figure 10.2. Random Column Write (Page within same Bank)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK2

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RBw

RBw

Activate

Command

CBw

DBw0 DBw1DBw2 DBw3 DBx0 DBx1

Write

Command

CBx

Write

Command

CBy

DBy0

DBy1 DBy2 DBy3

Write

Command

Precharge
Command

RBz

RBz

Activate

Command

CBz

DBz0

Write

Command

DBz1

DBz2 DBz3

Preliminary

35

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Ban

k B

Ban

k B

Ban

k B

Ban

k B

Ban

k B

Ban

k B

Figure 10.3. Random Column Write (Page within same Bank)

CLK

CKE

CS#

RAS#

CA S#

(Burst Length=4, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK3

WE#

B A0 ,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RBw

RBw

Activate

Command

CBw

DBw0DBw1DBw2 DBw3 DBx0 DBx1

Write

Command

CBx

Write

Command

CBy

DBy0

Write

Command

DBy1 DBy2 DBy3

Precharge
Command

RBz

RBz

Activate

Command

CBz

DBz0

Write

Command

DBz1

DBz2

Preliminary

36

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 11.1. Random Row Read (Interleaving Banks)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=8, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK1

High

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RBx

RBx

t

RCD

Activate

Command

Bank B

CBx

t

AC1

Bx0 Bx1 Bx2 Bx3 Bx4 Bx5

Read

Command

Bank B

RAx

RAx

Bx6

Activate

Command

Bank A

CAx

Bx7

Precharge
Command

Read

Command

t

Ax0 Ax1

Bank B

RBy

RBy

RP

Ax2 Ax3 Ax4 Ax5 Ax6 Ax7

Activate

Command

Bank B

CBy

Read

Command

Bank B

By0 By1 By2

Precharge
Command

Bank A

Preliminary

37

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 11.2. Random Row Read (Interleaving Banks)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=8, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK2

High

BA0,1

A10

A0 ~A9,A11

DQM

DQ

Hi-Z

RBx

RBx

Activate

Command

Bank B

CBx

t

RCDtAC2

Read

Command

Bank B

RAx

RAx

Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7

Activate

Command

Bank A

CAx

Precharge
Command

Read

Command

Bank B

t

RP

Ax0

RBy

RBy

Ax1

Activate

Command

Bank B

Ax2 Ax3

Ax4 Ax5

CBy

Ax6 Ax7

Read

Command

Bank B

By0 By1

Preliminary

38

Rev 0.6 Feb. 2001

EtronTech

EM638165

Ban

k B

Figure 11.3. Random Row Read (Interleaving Banks)

CLK

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=8, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK3

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RBx

RBx

Activate

Command

Bank B

t

RCD

CBx

Read

Command

RAx

RAx

t

AC3

Bx0 Bx1 Bx2 Bx3 Bx4 Bx5

Activate

Command

Bank A

CAx

Read

Command

Bank A

Bx6

Bx7 Ax0 Ax1

Precharge
Command

Bank B

RBy

RBy

tRP

Ax2 Ax3 Ax4 Ax5 Ax6

Activate

Command

Bank B

CBy

Read

Command

Bank B

Ax7 By0

Precharge
Command

Bank A

Preliminary

39

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 12.1. Random Row Write (Interleaving Banks)

CLK

CKE

High

CS#

RAS#

CA S#

(Burst Length=8, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK1

WE#

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

CAx

t

RCD

DAx0 DAx1 DAx2DAx3 DAx4 DAx5

Activate

Command

Bank A

Write

Command

RBx

RBx

DAx6

DAx7 DBx0 DBx1

Activate

Command

Bank B

CBx

Write

Command

Bank B

RAy

RAy

t

RP

DBx2 DBx3DBx4 DBx5 DBx6

Precharge
Command

Bank A

Activate

Command

Bank A

DBx7

t

WR

Precharge
Command

Bank B

CAy

DAy0 DAy1 DAy2

Write

Command

Bank A

DAy3

Preliminary

40

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Ban

k B

Figure 12.2. Random Row Write (Interleaving Banks)

CLK

High

CKE

CS#

RAS#

CA S#

(Burst Length=8, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK2

WE#

BA0,1

A 10

A0 ~A9,A11

RAx

RAx

CAx CBx

tRCD

DQM

Hi-Z

DQ

Activate

Command

Bank A

DAx0 DAx1 DAx2 DAx3 DAx4DAx5

Write

Command

Bank A

* tWR > tWR(min.)

RBx

RBx

DAx6

Activate

Command

Bank B

RAy

RAy

tWR* tRP tWR*

DAx7 DBx0 DBx1

Write

Command

Bank B

DBx2 DBx3 DBx4DBx5 DBx6

Activate

Command

Precharge
Command

Bank A

CAy

DBx7

DAy0 DAy1DAy2 DAy4

Write

Command

Bank A

Precharge
Command

DAy3

Preliminary

41

Rev 0.6 Feb. 2001

EtronTech

EM638165

Ban

k B

Bank A

Ban

k B

Bank A

Ban

k B

Bank A

Figure 12.3. Random Row Write (Interleaving Banks)

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=8, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK3

High

BA0,1

A 10

A0 ~A9,A11

DQM

*

tWR > tWR(min.)

RAx

RAx RAy

Hi-Z

DQ

Activate

Command

Bank A

CAx CBx

t

RCD

DAx0DAx1

Write

Command

DAx2 DAx3DAx4 DAx5

RBx

Activate

Command

RBx

DAx6

DAx7 DBx0 DBx1

t

WR* t

Write

Command

RP

DBx2 DBx3 DBx4

Precharge
Command

RAy

DBx5 DBx6

Activate

Command

CAy

t

WR*

DAy0 DAy1 DAy2

DBx7

Write

Command

Bank A

Precharge
Command

DAy3

Preliminary

42

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 13.1. Read and Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK1

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=1)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx CAx

Activate

Command

Bank A

Ax0 Ax1 Ax2 Ax3 DAy0DAy1

Read

Command

CAy CAz

DAy3 Az0 Az1

The Write Data

Write

Bank A

is Masked with a

Zero Clock

Latency

Command

Read

Command

Bank A

The Read Data

is Masked with a

Two Clock

Latency

Az3

Precharge
Command

Bank B

Preliminary

43

Rev 0.6 Feb. 2001

EtronTech

EM638165

La

ten

cy

La

ten

cy

Figure 13.2. Read and Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=2)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx CAx

Activate

Command

Bank A

Read

Command

Bank A

CAy

Ax0 Ax1 Ax2 Ax3 DAy0 DAy1

Write

is Masked with a

Command

Bank A

DAy3 Az0 Az1

The Write Data

Zero Clock

Command

Bank A

CAz

Read

The Read Data

is Masked with a

Two Clock

Az3

Preliminary

44

Rev 0.6 Feb. 2001

EtronTech

EM638165

La

ten

cy

La

ten

cy

Figure 13.3. Read and Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK3

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=3)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

CAx

Read

Command

Bank A

CAy CAz

Ax0 Ax1 Ax2 Ax3 DAy0 DAy1

The Write Data

Write

Bank A

is Masked with a

Command

DAy3 Az0 Az1

Read

Zero Clock

Command

Bank A

The Read Data

is Masked with a

Two Clock

Az3

Preliminary

45

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 14.1. Interleaving Column Read Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK1

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=1)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

tRCD

Activate

Command

Bank A

RBw

RBw

RAx

CBw

CBx

CBy

CAy

tAC1

Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1

Activate

Command

Read

Command

Bank B

Bw0 Bw1 Bx0 Bx1 By1 Ay0

Read

Command

Bank B

Read

Command

Bank B

Read

Command

Bank B

Read

Command

Bank A

Command

CBz

Read

Bank B

Bz0

Precharge
Command

Bank A

Bz2 Bz3

Precharge
Command

Bank B

Preliminary

46

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 14.2. Interleaving Column Read Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=2)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

CAy

tRCD tAC2

Read

Command

Bank A

RAx

RAx

Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1

Activate

Command

Bank B

CBw

Read

Command

Bank B

CBx CBy CAy CBz

Bw0 Bw1 Bx0 Bx1 By1 Ay0

Read

Command

Bank B

Read

Command

Bank B

Read

Command

Bank A

Read

Command

Bank B

Precharge
Command

Bz0

Bz2 Bz3

Precharge
Command

Bank B

Preliminary

47

Rev 0.6 Feb. 2001

EtronTech

EM638165

Ban

k B

Figure 14.3. Interleaved Column Read Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=3)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

tRCD

CAx RBx

Read

Command

Bank A

Activate

Command

RBx

CBx

t

AC3

Ax0 Ax1 Ax2 Ax3 Bz0 Ay1 Ay3

Read

Command

Bank B

CBy

Read

Command

Bank B

CBz

Bx0 Bx1 By0 By1 Bz1 Ay0

Read

Command

Bank B

CAy

Read

Command

Bank A

Prechaerge

Command

Bank B

Precharge
Command

Bank A

Ay2

Preliminary

48

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 15.1. Interleaved Column Write Cycle

(Burst Length=4, CAS# Latency=1)

CLK

CKE

CS#

RAS#

CA S#

WE#

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

T0 T 1 T2 T3 T4 T5 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

t

CK1

RAx

RAx

t

RBw

CAx RBw

RCD

CBw

T6

CBx

CBy

CAy

CBz

t

RP

tWRt

RP

tRRD

Hi-Z

DAx0

DAx1 DAx2 DAx3 DBy0 DAy1 DBz0

DBw0DBw1 DBx0 DBx1 DBy1DAy0

DBz1

DBz2

DBz3

Preliminary

Activate

Command

Bank A

Command

Write

Command

Activate

Bank B

Write

Command

Bank B

Write

Command

Bank B

Write

Command

Bank B

Write

Command

Bank A

Precharge
Command

Bank A

Write

Command

Bank B

49

Precharge
Command

Bank B

Rev 0.6 Feb. 2001

EtronTech

Bank A

EM638165

Figure 15.2. Interleaved Column Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CA S#

WE#

BA0,1

(Burst Length=4, CAS# Latency=2)

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

t

RCD

RBw

CAx

RBw

CBw CBx CBy

tRRD

DAx0

DAx1 DAx2 DAx3 DBy0 DAy1 DBz0

Write

Command

Bank A

Activate

Command

Bank B

DBw0 DBw1 DBx0 DBx1 DBy1DAy0

Write

Command

Bank B

Write

Command

Bank B

Write

Command

Bank B

Command

Bank A

CAy

Write

CBz

Write

Command

Bank B

Precharge
Command

DBz1

RP

t

DBz2

DBz3

WR

t

Precharge
Command

Bank B

RP

t

Preliminary

50

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 15.3. Interleaved Column Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=3)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

CAx RBw

tRCD

t

RRD > tRRD(min)

DAx0

Write

Command

Bank A

RBw

CBw CBx CBy

DAx1 DAx2 DAx3 DBy0 DAy1 DBz0

Activate

Command

Bank B

DBw0 DBw1DBx0 DBx1 DBy1 DAy0

Write

Command

Bank B

Write

Command

Bank B

Write

Command

Bank B

CAy

Write

Command

Bank A

CBz

tWR

Write

Command

Bank B

Precharge
Command

DBz1

tRP

DBz2

DBz3

tWR(min)

Precharge
Command

Bank B

Preliminary

51

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Ban

k B

Figure 16.1. Auto Precharge after Read Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK1

CKE

CS#

RAS#

CA S#

WE#

High

(Burst Length=4, CAS# Latency=1)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Activate

Command

Bank A

RAx

RAx

CAx

Read

Command

Bank A

RBx

CBx

RBx

Ax1 Ax2 Ax3 Ay0 Ay3 By0

Ax0

Activate

Command

Bank B

Bx0 Bx1 Bx2 Bx3 Ay1 Ay2

Read with

Auto Precharge

Command

Bank B

RBy RBz

RBy CBy

CAy

Activate

Command

Bank B

Read with

Auto Precharge

Command

Read with

Auto Precharge

Command

Bank B

By1

By2

By3

Command

Activate

Bank B

RBz

CBz

Read with

Auto Precharge

Command

Bz0 Bz1

Bz2

Bz3

Preliminary

52

Rev 0.6 Feb. 2001

EtronTech

Ban

k B

Bank A

Ban

k B

Bank A

EM638165

Figure 16.2. Auto Precharge after Read Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

High

CKE

CS#

RAS#

CA S#

WE#

BA0,1

A 10

RAx

RBx

(Burst Length=4, CAS# Latency=2)

RBy

RAz

A0 ~A9,A11

DQM

DQ

Hi-Z

Command

RAx

Activate

Bank A

CAx

Read

Command

Bank A

RBx

Ax0

Activate

Command

Bank B

CBx

Ax1 Ax2 Ax3 Ay0 Ay3 By0

Read with

Auto Precharge

Command

Bx0 Bx1 Bx2 Bx3 Ay1 Ay2

RAy CBy

Read with

Auto Precharge

Command

RBy

Activate

Command

Bank B

Auto Precharge

Read with
Command

RAz

Activate

Command

Bank A

CAz

By1

By2

Read with

Auto Precharge

Command

By3

Az0 Az1

Az2

Preliminary

53

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 16.3. Auto Precharge after Read Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=3)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Activate

Command

Bank A

RAx

RAx

CAx

Read

Command

Bank A

RBx

RBx

Activate

Command

Bank B

RBy

CBx

Ax0

Ax1 Ax2 Ax3 Ay0 Ay3 By0

Read with

Auto Precharge

Command

Bank B

CAy

Bx0 Bx1 Bx2 Bx3 Ay1 Ay2

Read with

Auto Precharge

Command

RBy

Activate

Command

Bank B

CBy

Read with

Auto Precharge

Command

Bank B

By1

By2

By3

Preliminary

54

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 17.1. Auto Precharge after Write Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, CAS# Latency=1)

T 11

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Command

RAx

RAx

Activate

Bank A

RBx

CAx

DAx0

Write

Command

Bank A

RBx

DAx1 DAx2 DAx3 DAy0 DAy3 DBy0

Activate

Command

Bank B

CBx

DBx0 DBx1 DBx2 DBx3 DAy1DAy2

Write with

Auto Precharge

Command

Bank B

CAy

Write with

Auto Precharge

Command

Bank A

Activate

Command

Bank B

RBy

RBy

CBy

DBy1 DBy2 DBy3

Write with

Auto Precharge

Command

Bank B

RAz

RAz

CAz

DAz0 DAz0

Activate

Command

Bank A

Write with

Auto Precharge

Command

DAz0DAz0

Preliminary

55

Rev 0.6 Feb. 2001

EtronTech

Ban

k B

Bank A

Ban

k B

Bank A

EM638165

Figure 17.2. Auto Precharge after Write Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

High

CKE

CS#

RAS#

CA S#

WE#

BA0,1

A 10

RAx

RBx

(Burst Length=4, CAS# Latency=2)

RBy

RAz

A0 ~A9,A11

DQM

DQ

Hi-Z

Command

RAx

Activate

Bank A

CAx

DAx0

Write

Command

Bank A

RBx

DAx1 DAx2 DAx3 DAy0 DAy3 DBy0

Activate

Command

Bank B

CBx

DBx0 DBx1DBx2 DBx3 DAy1 DAy2

Write with

Auto Precharge

Command

CAy

Write with

Auto Precharge

Command

RBy

Activate

Command

Bank B

CBy

DBy1

Write with

Auto Precharge

Command

RAz

DBy2 DBy3

Activate

Command

Bank A

CAz

DAz0 DAz1

Write with

Auto Precharge

Command

DAz2 DAz3

Preliminary

56

Rev 0.6 Feb. 2001

EtronTech

Bank A

EM638165

Figure 17.3. Auto Precharge after Write Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

High

CKE

CS#

RAS#

CA S#

WE#

BA0,1

A9

RAx

RBx

(Burst Length=4, CAS# Latency=3)

`

RBy

A0 ~A9,A11

DQM

DQ

Hi-Z

Command

RAx

Activate

Bank A

RBx

DAx0

DAx1 DAx2 DAx3 DAy0 DAy3 DBy0

Activate

Command

Bank B

Write

Command

CBx

DBx0 DBx1 DBx2 DBx3 DAy1 DAy2

Write with

Auto Precharge

Command

Bank B

CAyCAx

Write with

Auto Precharge

Command

Bank A

RBy

Activate

Command

Bank B

CBy

Write with

Auto Precharge

Command

Bank B

DBy1 DBy2DBy3

Preliminary

57

Rev 0.6 Feb. 2001

EtronTech

EM638165

bu

rsting b

egi

nning wi

th

the star

tin

g addres

s.

Figure 18.1. Full Page Read Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=1)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

Command

Bank A

RBx

RBx RBy

CAx

CBx

tRRD

Bx+6 Bx+7

Burst Stop

Command

Read

Ax+1

Ax

Activate

Command

The burst counter wraps

Bank B

from the highest order
page address back to zero
during this time interval

Ax+2

Ax-2 Ax-1 Bx+2 Bx+5

Ax Ax+1 Bx

Read

Command

Bank B

Bx+1

Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues

Bx+3 Bx+4

Precharge
Command

Bank B

RBy

tRP

Activate

Command

Bank B

Preliminary

58

Rev 0.6 Feb. 2001

EtronTech

EM638165

Comma

nd

Figure 18.2. Full Page Read Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK2

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=2)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

RAx

RAx

Activate

Command

Bank A

Read

Command

Bank A

RBx

RBxCAx RBy

CBx

tRP

Ax

Ax+1

Activate

Command

Bank B

The burst counter wraps
from the highest order
page address back to zero
during this time interval

Ax+2Ax-2 Ax-1 Bx+2 Bx+5

Ax Ax+1 Bx Bx+1 Bx+3 Bx+4

Read

Full Page burst operation does not

Command

terminate when the burst length is satisfied;

Bank B

the burst counter increments and continues
bursting beginning with the starting address.

Burst Stop

Bx+6

Precharge
Command

Bank B

RBy

Activate

Command

Bank B

Preliminary

59

Rev 0.6 Feb. 2001

EtronTech

EM638165

du

ring

th

is t

ime

in

terv

al

Figure 18.3. Full Page Read Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK3

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=3)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Activate

Command

Bank A

RAx

RAx

Read

Command

Bank A

RBx

RBxCAx

Activate

Command

Bank B

Ax+1

Ax

Ax+2 Ax-2 Ax-1 Bx+2 Bx+5

The burst counter wraps
from the highest order
page address back to zero

CBx

Ax Ax+1 Bx Bx+1 Bx+3 Bx+4

Read

Full Page burst operation does not

Command

terminate when the burst length is

Bank B

satisfied; the burst counter
increments and continues
bursting beginning with the
starting address.

Burst Stop

Command

Precharge
Command

Bank B

tRP

RBy

RBy

Activate

Command

Bank B

Preliminary

60

Rev 0.6 Feb. 2001

EtronTech

be

gin

ning wit

h t

he

starting

ad

dre

ss.

EM638165

Figure 19.1. Full Page Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK1

High

CKE

CS#

RAS#

CA S#

WE#

BA0,1

(Burst Length=Full Page, CAS# Latency=1)

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Activate

Command

Bank A

RAx

RAx

Write

Command

Bank A

RBx

RBxCAx

DAx+1DAx

DAx+2 DAx+3 DAx-1 DAx

Activate

Command

Bank B

The burst counter wraps
from the highest order
page address back to zero
during this time interval

CBx

DBx DBx+ 1

DAx+1

Write

Command

Bank B

Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting

DBx+ 2

DBx+ 3

DBx+4 DBx+5 DBx+6 DBx+7

Data is ignored

Precharge
Command

Burst Stop

Command

Bank B

RBy

RBy

Activate

Command

Bank B

Preliminary

61

Rev 0.6 Feb. 2001

EtronTech

EM638165

be

gin

ning wit

h t

he

starting

ad

dre

ss.

Figure 19.2. Full Page Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK2

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=2)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Command

RAx

RAx

Activate

Bank A

CAx

Write

Command

Bank A

RBx

RBx

DAx+1DAx

DAx+2 DAx+3 DAx-1 DAx

Activate

Command

Bank B

The burst counter wraps
from the highest order
page address back to zero
during this time interval

CBx

DAx+1

DBx DBx+ 1

Write

Command

Bank B

Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting

DBx+2

DBx+3

DBx+4 DBx+5 DBx+6

Data is ignored

Precharge
Command

Burst Stop

Command

Bank B

RBy

RBy

Activate

Command

Bank B

Preliminary

62

Rev 0.6 Feb. 2001

EtronTech

EM638165

be

gin

ning wit

h t

he

starting

ad

dre

ss.

Figure 19.3. Full Page Write Cycle

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK3

High

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=3)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

Hi-Z

Command

RAx

RAx

Activate

Bank A

Write

Command

Bank A

RBx

RBxCAx

DAx+1DAx

DAx+2 DAx+3 DAx-1 DAx

Activate

Command

Bank B

The burst counter wraps
from the highest order
page address back to zero
during this time interval

CBx

DBx

Write

Command

Bank B

DBx+1

DBx+2

DBx+3

DAx+1

Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting

DBx+4 DBx+5

Precharge
Command

Burst Stop

Command

Data is ignored

Bank B

RBy

RBy

Activate

Command

Bank B

Preliminary

63

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 20. Byte Write Operation

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T 14 T15 T16 T 17 T18 T19 T20 T21 T22

CLK

tCK2

High

CKE

CS#

RAS#

CAS#

WE#

(Burst Length=4, CAS# Latency=2)

BA0,1

A10

A0~A9,A11

LDQM

UDQM

DQ0 - DQ7

DQ8 - DQ15

RAx

RAx

Activate

Command

Bank A

CAx

Read

Command

Bank A

Ax0 Ax1 Ax2

Upper 3 Bytes

are masked

Ax1 Ax2 Ax3

Lower Byte

is masked

CAy

DAy2

DAy1

DAy0 DAy1 DAy3

Write

Upper 3 Bytes

Command

Bank A

are masked

CAz

Read

Command

Az0

Lower Byte

is masked

Az1 Az2

Az1 Az2

Az3

Lower Byte

is masked

Preliminary

64

Rev 0.6 Feb. 2001

EtronTech

EM638165

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Precha

rge

Figure 21. Random Row Read (Interleaving Banks)

CLK

High

CKE

CS#

RAS#

CA S#

WE#

BA0,1

RBu

A 10

(Burst Length=2, CAS# Latency=1)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

tCK1

RAu

Begin Auto

Precharge

Bank B

RBv

Begin Auto

Precharge

Bank A

RAv

Begin Auto

Precharge

Bank B

RBw

Begin Auto

Precharge

Bank A

RAw

Begin Auto

Precharge

Bank B

RBx

Begin Auto
Precharge

Bank A

RAx

Begin Auto

Precharge

Bank B

RBy

Begin Auto

Precharge

Bank A

RAy

Begin Auto

Precharge

Bank B

RBz

Begin Auto

Precharge

Bank A

RAz

A0 ~A9,A11

DQM

DQ

RBu

Activate

Command

Bank B

CBu

RAu CAu

Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0

Activate

Command

Bank A

Read

Bank B

with Auto

Activate

Command

Read

Bank A

with Auto

RBv

t

RP

Bank B

CBv

t

RP

Activate

Command

Bank A

Read

Bank B

with Auto

RAv

CAv

Activate

Command

Bank B

Read

Bank A

with Auto

CBw

RAw

t

RP

Activate

Command

Bank A

CAw

Read

Bank A

with Auto

RBw

t

RP

Read

Bank B

with Auto

RBx

t

RP

Activate

Command

Bank B

CBx

t

RP

Activate

Command

Read

Bank B

with Auto

RAx CAx

Bank A

t

RP

Activate

Command

Read

Bank A

with Auto

RBy CBy

Bank B

t

Activate

Command

Bank A

Read

Bank B

with Auto

RAy CAy

RP

Activate

Command

Read

Bank A

with Auto

RBz CBz

t

RP

Bank B

with Auto

t

RP

Command

Read

Bank B

RAz

Activate

Bank A

Preliminary

65

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 22. Full Page Random Column Read

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK2

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=2)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

RAx

RAx

Activate

Command

Bank A

RBx

RBx CAx

tRRD tRCD

Activate

Command

Bank B

Command

CBx CAy CBy

Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2

Read

Command

Bank B

Read

Read

Command

Bank A

Read

Command

Bank B

CAz

Read

Command

Bank A

CBz

Read

Command

Bank B

tRP

Precharge

Command Bank B

(Precharge Temination)

RBw

RBw

Activate

Command

Bank B

Preliminary

66

Rev 0.6 Feb. 2001

EtronTech

EM638165

is

mask

ed

Figure 23. Full Page Random Column Write

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=2)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

RAx

RAx

Activate

Command

Bank A

t

RRD

RBx

RBx CAx

Activate

Command

Bank B

CBx CAy CBy

t

RCD

DAx0DBx0DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0DBz1

Command

Write

Command

Bank A

Write

Bank B

Write

Command

Bank A

Write

Command

Bank B

CAz

Write

Command

Bank A

CBz

Write

Command

Bank B

tRP

t

WR

DBz2

Precharge

Command Bank B

(Precharge Temination)

Write Data

RBw

RBw

Activate

Command

Bank B

Preliminary

67

Rev 0.6 Feb. 2001

EtronTech

EM638165

Bank A

Figure 24.1. Precharge Termination of a Burst

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

CK1

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=Full Page, CAS# Latency=1)

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

RAx

RAx

CAx RAy

DAx0 DAx1DAx2 DAx3 DAx4

Activate

Command

Bank A

Precharge Termination

of a Write Burst.

Write data is masked.

Write

Command

Bank A

tWR

Precharge
Command

Bank A

RAy

t

RP

Activate

Command

CAy

Read

Command

Bank A

Ay0 Ay1 Ay2

Precharge
Command

Bank A

RAz

RAz

t

RP

Activate

Command

Bank A

CAz

Precharge

Termination of

a Read Burst.

DAz3DAz2DAz0

DAz1 DAz4 DAz5

Write

Command

Bank A

DAz6 DAz7

Preliminary

68

Rev 0.6 Feb. 2001

EtronTech

EM638165

Figure 24.2. Precharge Termination of a Burst

(Burst Length=8 or Full Page, CAS# Latency=2)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

tCK2

High

CKE

CS#

RAS#

CA S#

WE#

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

RAx

RAx

Activate

Command

Bank A

CAx

DAx0 DAx1DAx2 DAx3

Write

Command

Bank A

Precharge Termination

of a Write Burst.

Write data is masked.

tWR

Precharge
Command

Bank A

tRP

Command

RAy

RAy CAy

Activate

Bank A

Command

Read

Bank A

Precharge
Command

Bank A

t

RP

Ay2Ay0 Ay1

RAz

RAz

Activate

Command

Bank A

CAz

Read

Command

Bank A

Precharge Termination
of a Read Burst

RP

t

Az0 Az1 Az2

Precharge
Command

Bank A

Preliminary

69

Rev 0.6 Feb. 2001

EtronTech

EM638165

Figure 24.3. Precharge Termination of a Burst

CLK

CKE

CS#

RAS#

CA S#

WE#

(Burst Length=4, 8 or Full Page, CAS# Latency=3)

T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CK3

t

High

BA0,1

A 10

A0 ~A9,A11

DQM

DQ

RAx

RAx

Activate

Command

Bank A

CAx

DAx0

Write

Command

Bank A

Write Data

is masked

WR

t

DAx1

Precharge
Command

Bank A

Precharge Termination

of a Write Burst

RP

t

RAy

RAy

Activate

Command

Bank A

CAy

Read

Command

Bank A

Ay0 Ay1 Ay2

Precharge
Command

Bank A

t

RP

RAz

RAz

Activate

Command

Bank A

Precharge Termination

of a Read Burst

Preliminary

70

Rev 0.6 Feb. 2001

EtronTech

EM638165

54 Pin TSOP II Package Outline Drawing Information

5 4

28

0.254

E

E

H

θ°

L

1

L

1

D

S

B e

y

27

Symbol Dimension in inch Dimension in mm

Min Normal Max Min Normal Max

0.047

-

0.0059 0.05 0.1 0.150

0.0411

-

5° 0°

A -

A1

0.002 0.00395

A2 -

B
c
D
E
e

HE

L

0.012 0.015 0.016 0.3 0.35 0.40

0.0047 0.0065 0.0083 0.120 1.165 0.210

0.872 0.8755 0.879 22.149 22.238 22.327

0.3960 0.400 0.4040 10.058 10.16 10.262

0.462 0.466 0.470 11.735 11.8365

0.016 0.020 0.0235 0.406 0.50 0.597

L1

S
y

θ

- 0.0315 - - 0.80 -

- 0.033 - - 0.84 -

- 0.035 - - 0.88 -

- - 0.004 - - 0.10

0°

-

-

-

Notes:

1. Dimension D&E do not include interiead flash.

2. Dimension B does not include dambar protrusion/intrusion.

3. Dimension S includes end flash.

4. Controlling dimension : mm

A

A2

L

A1

-

-

1.194

1.044

L

C

1

11.938

-

5°

Preliminary

71

Rev 0.6 Feb. 2001