Datasheet EL7563CRE-T7, EL7563CRE-T13, EL7563CM-T13, EL7563CM Datasheet (ELANT)

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

Features

• Integrated synchronous MOSFETs
and current mode controller

• 4A continuous output current

• Up to 95% efficiency

• Internal patented current sense

• Cycle-by-cycle current limit

• 3V to 3.6V input voltage

• Adjustable output voltage 1V to

2.5V

• Precision reference

• ±0.5% load and line regulation

• Adjustable switching frequency to
1MHz

• Oscillator synchronization
possible

• Internal soft-start

• Over-voltage protection

• Junction temperature indicator

• Over-temperature protection

• Under-voltage lockout

• Multiple supply start-up tracking

• Power-good indicator

• 20-pin SO (0.300”) package

• 28-pin HTSSOP package

Applications

• DSP, CPU Core, and I/O Supplies

• Logic/Bus supplies

• Portable equipment

• DC:DC converter modules

• GTL + Bus power supply

Ordering Information

Part No Package

EL7563CM 20-Pin SO (0.300”) - MDP0027

EL7563CM-T13 20-Pin SO (0.300”) 13” MDP0027

EL7563CRE-T7 28-Pin HTSSOP 7” MDP0048

EL7563CRE-T13 28-Pin HTSSOP 13” MDP0048

Tape &

Reel Outline #

General Description

The EL7563C is an integrated, full-featured synchronous step-down
regulator with output voltage adjustable from 1.0V to 2.5V. It is capa­ble of delivering 4A continuous current at up to 95% efficiency. The
EL7563C operates at a constant frequency pulse width modulation
(PWM) mode, making external synchronization possible. Patented on­chip resistorless current sensing enables current mode control, which
provides cycle-by-cycle current limiting, over-current protection, and
excellent step load response. The EL7563C features power tracking,
which makes the start-up sequencing of multiple converters possible.
A junction temperature indicator conveniently monitors the silicon die
temperature, saving the designer time on the tedious thermal charac­terization. The minimal external components and full functionality
make this EL7563C ideal for desktop and portable applications.

The EL7563C is specified for operation over the full -40°C to +85°C
temperature range.

Typical Application Diagram (EL7563CM)

C5

1

CREF

0.1µF
2

SGND

C4

3

COSC

R4

22Ω

0.22µF

330µF

V

IN

3.3V

Typical Application Diagrams continued on page 3
Manufactured Under U.S. Patent No. 5,7323,974

390pF

4

C2

2.2nF

VS

5

PSHR

6

PGND

7

PGND

8

VIN

9

STP

10

STN

EL7563CM

C3

C1

VDRV

VHI

PGNDP

PGND

PGND

20

EN

19

FB

18

PG

17

16

15

LX

14

LX

13

12

11

D1

C6 C9

0.22µF

L1

4.7µH

C7 R1
330µF

D4

D2

C8

0.22µF

D3

0.1µF
V

OUT

R2

1.54kΩ

1kΩ

2.5V
4A

C10

2.2nF

October 5, 2001

Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these

specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.

© 2001 Elantec Semiconductor, Inc.

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

Absolute Maximum Ratings (T

Supply Voltage between VIN or VDD and GND +4.5V

VLX Voltage VIN +0.3V

Input Voltage GND -0.3V, VDD +0.3V

VHI Voltage GND -0.3V, V

= 25°C)

A

LX

Storage Temperature -65°C to +150°C

Operating Ambient Temperature -40°C to +85°C

Operating Junction Temperature +135°C

+6V

Important Note:

All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: TJ = TC = TA.

DC Characteristics

V

= V

= 3.3V, TA = TJ = 25°C, C

DD

IN

Parameter Description Conditions Min Typ Max Unit

V

REF

V

REFTC

V

REFLOAD

V

RAMP

I

OSC_CHG

I

OSC_DIS

I

VDD+VDRVVDD+VDRV

I

VDD_OFF

V

DD_OFF

V

DD_ON

T

OT

T

HYS

I

LEAK

I

LMAX

R

DSON

R

DSONTC

I

STP

I

STN

V

PGP

V

PGN

V

PG_HI

V

PG_LO

V

OVP

V

FB

V

FB_LINE

V

FB_LOAD

V

FB_TC

I

FB

V

EN_HI

V

EN_LO

I

EN

Reference Accuracy 1.24 1.26 1.28 V

Reference Temperature Coefficient 50 ppm/°C

Reference Load Regulation 0<I

Oscillator Ramp Amplitude 1.15 V

Oscillator Charge Current 0.1V<V

Oscillator Discharge Current 0.1V<V

Supply Current VEN = 4V, F

V

Standby Current EN = 0 1 1.5 mA

DD

VDD for Shutdown 2.4 2.65 V

VDD for Startup 2.6 2.95 V

Over Temperature Threshold 135 °C

Over Temperature Hysteresis 20 °C

Internal FET Leakage Current EN = 0, LX = 3.3V (low FET), LX = 0V

Peak Current Limit 5 A
FET On Resistance Wafer level test only 30 60 mΩ

R

Tempco 0.2 mΩ/°C

DSON

Auxilliary Supply Tracking Positive Input Pull
Down Current

Auxilliary Supply Tracking Negative Input Pull
Up Current

Positive Power Good Threshold With respect to target output voltage 8 16 %

Negative Power Good Threshold With respect to target output voltage -16 -8 %

Power Good Drive High I

Power Good Drive Low IPG = -1mA 0.5 V

Over Voltage Protection 10 %

Output Initial Accuracy I

Output Line Regulation V

Output Load Regulation 0.5A< I

Output Temperature Stability -40°C < TA<85°C, I

Feedback Input Pull Up Current V

EN Input High Level 2.7 V

EN Input Low Level 1 V

Enable Pull Up Current VEN = 0 -4 -2.5 µA

= 1.2nF, unless otherwise specified.

OSC

(high FET)

V

V

PG

LOAD

<50µA -1 %

REF

<1.25V 200 µA

OSC

<1.25V 8 mA

OSC

= 120kHz 2 3.5 5 mA

OSC

10 µA

= VIN/2 -4 2.5 µA

STP

= VIN/2 2.5 4 µA

STN

= 1mA 2.7 V

= 0A 0.977 0.992 1.007 V

= 3.3V, ∆V

IN

= 0V 100 200 nA

FB

= 10%, I

IN

<4A 0.5 %

LOAD

LOAD

= 0A 0.5 %

LOAD

= 2A ±1 %

2

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

Closed Loop AC Electrical Characteristics

VS = V

= 3.3V, TA = TJ = 25°C, C

IN

Parameter Description Conditions Min Typ Max Unit

F

OSC

t

SYNC

M

t

BRM

t

LEB

D

SS

MAX

Oscillator Initial Accuracy 100 115 125 kHz

Minimum Oscillator Sync Width 25 ns

Soft Start Slope 0.5 V/ms

FET Break Before Make Delay 15 ns

High Side FET Minimum On Time 150 ns

Maximum Duty Cycle 95 %

Typical Application Diagrams (Continued)

V

IN

3.3V

= 1.2nF, unless otherwise specified.

OSC

C5

0.1µF

C4

R4

22Ω

0.22µF

C1

330µF

390pF

C3

C2

2.2nF

1

CREF

2

SGND

3

COSC

4

VS

5

PSHR

6

PGND

7

PGND

8

PGND

9

PGND

10

VIN

VDRV

VHI

28

EN

27

FB

26

PG

25

24

23

LX

22

LX

4.7µH

21

LX

20

LX

19

LX

D1

C6 C9

0.22µF

L1

C7 R1
330µF

D4

D2

C8

0.22µF

D3

0.1µF
V

OUT

R2

1.54kΩ

1kΩ

2.5V
4A

C10

2.2nF

EL7563C

11

VIN

12

NC

13

STP

STN

EL7563CRE

For the package information, please refer to the Elantec website at http://www.elantec.com/pages/package_outline.html

PGND

PGND

18

LX

17

NC

16

1514

3

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

Pin Descriptions

Pin Number Pin Name Pin Function

1 VREF Bandgap reference bypass capacitor; typically 0.1µF to SGND

2 SGND Control circuit negative supply or signal ground

3 COSC Oscillator timing capacitor (see performance curves)

4 VDD Control circuit positive supply; normally connected to VIN through an RC filter

5 VTJ Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND

6 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

7 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

8 VIN Power supply input of the regulator; connected to the drain of the high-side NMOS power FET

9 STP Auxilliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open for

10 STN Auxilliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for stand

11 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

12 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

13 PGND Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

14 LX Inductor drive pin; high current output whose average voltage equals the regulator output voltage

15 LX Inductor drive pin; high current output whose average voltage equals the regulator output voltage

16 VHI Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF capacitor

17 VDRV Positive supply of low-side driver and input voltage for high side boot strap

18 PG Power good window comparator output; logic 1 when regulator output is within ±10% of target output voltage

19 FB Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces

20 EN Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open; a capacitor can be added at

stand alone operation; 2µA internal pull down current

alone operation; 2µA internal pull up current

VOUT to SGND in the event that FB is floating

this pin to delay the start of converter

4

Monolithic 4 Amp DC:DC Step-down Regulator

Typical Performance Curves (20-Pin SO Package)

*Note: The 28-Pin HTSSOP Package Offers Improved Performance

EL7563C

EL7563C

*Efficiency vs I
VIN=3.3V

100

95
90
85
80
75

Efficiency (%)

70
65

Measured with SO20 package Measured with SO20 package

60

0 1 2 2.5 3 3.5 4

*Converter Total Power Loss vs I
VIN=3.3V

1.8

1.6

1.4

1.2
1

0.8

0.6

Power Loss (W)

0.4

0.2
0

0 0.5 1.5 2.5 3 3.5 4

O

VO=2.5V VO=1.8V

VO=1.2V

0.5 1.5
Load Current IO (A)

Measured with SO20 package

1 2

Output Current IO (A)

VO=1V

O

VO=1.8V

VO=1.2V

VO=1V

VO=2.5V

*Efficiency vs I
VO=2.5V

100

95
90
85
80
75

Efficiency (%)

70
65
60

0 1 2 2.5 3 3.5 4

Load Regulation
VO=2.5V

2.505

2.5

2.495

2.49

2.485

2.48

Output Voltage (V)

2.475

2.47

2.465

0.5 1 2 2.5 3 3.5 4

O

VIN=3V

VIN=3.3V

VIN=3.6V

0.5 1.5
Load Current IO (A)

VIN=3.6V

VIN=3.3V

VIN=3V

1.5
Load Current IO (A)

Line Regulation
VO=3.5V

2.505

2.5

2.495

2.49

2.485

(V)

O

V

2.48

2.475

2.47

2.465

IO=0.5A

IO=2A

IO=4A

3 3.1 3.2 3.3 3.4 3.5 3.6

VIN (V)

V

vs Junction Temperature

REF

1.27

1.268

1.266

1.264

(V)

REF

1.262

V

1.26

1.258

1.256

-50 150-10 30 70 110
Junction Temperature (°C)

5

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

Typical Performance Curves

*Note: The 28-Pin HTSSOP Package Offers Improved Performance

Switching Frequency vs C

1000

900
800
700
600

(KHz)

S

500

F

400
300
200
100

100 1000200 400 600 800

*θJA vs Copper Area
SO20 Package

50

46

42

38

Thermal Resistance (°C/W)

34

Test Condition:
Chip in the center of copper area

30

1 41.5 2.5 3.5

PCB Copper Heat-Sinking Area (in2)

Transient Response
VIN=3.3V, VO=1.8V, IO=0.2A-4A

OSC

C

(pF)

OSC

with 100 LFPM airflow

2 3

with no airflow

1 oz. copper PCB used

VTJ vs Junction Temperature

1.5

1.3

PSHR

V

1.1

900300 500 700

0.9
0 15025

Switching Waveforms
VIN=3.3V, VO=1.8V, IO=4A

∆VIN

V

LX

i

L

∆V

O

Power-Up
VIN=3.3V, VO=1.8V, IO=0.2A

12550 75 100

Junction Temperature (°C)

I

O

∆V

O

6

Typical Performance Curves

EL7563C

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

Power-Down
VIN=3.3V, VO=1.8V, IO=4A

V

IN

V

O

Disable
VIN=3.3V, VO=1.8V at 4A

EN

V

O

Enable
VIN=3.3V, VO=1.8V at 4A

EN

V

O

Short-Circuit Protection
VIN=3.3V, VO=1.8V, IO=4A to short

I

O

V

O

7

EL7563C

(2.5V,

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

Block Diagram

390pF0.1µF

3.3V

STP

STN

VREF COSC

Power

Tracking

SGND

Temperature

Controller

Supply

Junction

FB

VTJ VDRV

2.2nF

22Ω

VDD

0.22µF

EN

Voltage

Reference

PWM

Controller

VREF

Current

Sense

-

+

Oscillator

Drivers

Power

FET

Power

FET

VHI

VIN

0.22µF

4.7µH V

PGND

PG

D

1

330µF

D

D

2

4

0.22µF

D

3

0.1µF

OUT

2.2nF

4A)

1.58kΩ

1kΩ

8

Applications Information

EL7563C

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

Circuit Description

General

The EL7563C is a fixed frequency, current mode con­trolled DC:DC converter with integrated N-channel
power MOSFETs and a high precision reference. The
device incorporates all the active circuitry required to
implement a cost effective, user-programmable 4A syn­chronous step-down regulator suitable for use in DSP
core power supplies. By combining fused-lead packag­ing technology with an efficient synchronous switching
architecture, high power output (10W) can be realized
without the use of discrete external heat sinks.

Theory of Operation

The EL7563C is composed of 7 major blocks:

1. PWM Controller

2. NMOS Power FETs and Drive Circuitry

3. Bandgap Reference

4. Oscillator

5. Temperature Sensor

6. Power Good and Power On Reset

7. Auxiliary Supply Tracking

PWM Controller

The EL7563C regulates output voltage through the use
of current-mode controlled pulse width modulation. The
three main elements in a PWM controller are the feed­back loop and reference, a pulse width modulator whose
duty cycle is controlled by the feedback error signal, and
a filter which averages the logic level modulator output.
In a step-down (buck) converter, the feedback loop
forces the time-averaged output of the modulator to
equal the desired output voltage. Unlike pure voltage­mode control systems, current-mode control utilizes
dual feedback loops to provide both output voltage and
inductor current information to the controller. The volt­age loop minimizes DC and transient errors in the output
voltage by adjusting the PWM duty-cycle in response to
changes in line or load conditions. Since the output volt­age is equal to the time-averaged of the modulator

output, the relatively large LC time constant found in
power supply applications generally results in low band­width and poor transient response. By directly
monitoring changes in inductor current via a series sense
resistor the controller's response time is not entirely lim­ited by the output LC filter and can react more quickly to
changes in line and load conditions. This feed-forward
characteristic also simplifies AC loop compensation
since it adds a zero to the overall loop response. Through
proper selection of the current-feedback to voltage-feed­back ratio the overall loop response will approach a one­pole system. The resulting system offers several advan­tages over traditional voltage control systems, including
simpler loop compensation, pulse by pulse current limit­ing, rapid response to line variation and good load step
response.

The heart of the controller is an input direct summing
comparator which sum voltage feedback, current feed­back, slope compensation ramp and power tracking
signals together. Slope compensation is required to pre­vent system instability that occurs in current-mode
topologies operating at duty-cycles greater than 50%
and is also used to define the open-loop gain of the over­all system. The slope compensation is fixed internally
and optimized for 500mA inductor ripple current. The
power tracking will not contribute any input to the com­parator steady-state operation. Current feedback is
measured by the patented sensing scheme that senses the
inductor current flowing through the high-side switch
whenever it is conducting. At the beginning of each
oscillator period the high-side NMOS switch is turned
on. The comparator inputs are gated off for a minimum
period of time of about 150ns (LEB) after the high-side
switch is turned on to allow the system to settle. The
Leading Edge Blanking (LEB) period prevents the
detection of erroneous voltages at the comparator inputs
due to switching noise. If the inductor current exceeds
the maximum current limit (ILMAX) a secondary over­current comparator will terminate the high-side switch
on time. If ILMAX has not been reached, the feedback
voltage FB derived from the regulator output voltage
VOUT is then compared to the internal feedback refer­ence voltage. The resultant error voltage is summed with
the current feedback and slope compensation ramp. The

9

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

high-side switch remains on until all four comparator
inputs have summed to zero, at which time the high-side
switch is turned off and the low-side switch is turned on.
However, the maximum on-duty ratio of the high-side
switch is limited to 95%. In order to eliminate cross-con­duction of the high-side and low-side switches a 15ns
break-before-make delay is incorporated in the switch
drive circuitry. The output enable (EN) input allows the
regulator output to be disabled by an external logic con­trol signal.

Output Voltage Setting

In general:

R



2

V

OUT

0.992V 1

------

+

×=



R



1

However, due to the relatively low open loop gain of the
system, gain errors will occur as the output voltage and
loop-gain is changed. This is shown in the performance
curves. A 100nA pull-up current from FB to VDD forces
VOUT to GND in the event that FB is floating.

NMOS Power FETs and Drive Circuitry

The EL7563C integrates low on-resistance (30mΩ)

NMOS FETs to achieve high efficiency at 4A. In order
to use an NMOS switch for the high-side drive it is nec­essary to drive the gate voltage above the source voltage
(LX). This is accomplished by bootstrapping the VHI
pin above the LX voltage with an external capacitor
CVHI and internal switch and diode. When the low-side
switch is turned on and the LX voltage is close to GND
potential, capacitor CVHI is charged through internal
switch to VDRV, typically 6V with external charge­pump. At the beginning of the next cycle the high-side
switch turns on and the LX pins begin to rise from GND
to VIN potential. As the LX pin rises the positive plate
of capacitor CVHI follows and eventually reaches a
value of VDRV+VIN, typically 9V, for VIN=3.3V. This
voltage is then level shifted and used to drive the gate of
the high-side FET, via the VHI pin. A value of 0.22µF
for CVHI is recommended.

Reference

A 1.5% temperature compensated bandgap reference is
integrated in the EL7563C. The external VREF capaci-

tor acts as the dominant pole of the amplifier and can be
increased in size to maximize transient noise rejection.
A value of 0.1µF is recommended.

Oscillator

The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately
95%. Operating frequency can be adjusted through the
COSC pin or can be driven by an external source. If the
oscillator is driven by an external source care must be
taken in selecting the ramp amplitude. Since CSLOPE
value is derived from the COSC ramp, changes to COSC
ramp will change the CSLOPE compensation ramp
which determine the open-loop gain of the system.

When external synchronization is required, always
choose C

such that the free-running frequency is at

OSC

least 20% lower than that of sync source to accommo­date component and temperature variations. Figure 1
shows a typical connection.

1 20

External

Oscillator

BAT54S100pF

390pF

2

3

5

6

EL7563C

7

8

9

10

19

18

16

15

14

13

12

11

Figure 1. Oscillator Synchronization

Junction Temperature Sensor

An internal temperature sensor continuously monitors
die temperature. In the event that die temperature
exceeds the thermal trip-point, the system is in fault state
and will be shut down. The upper and low trip-points are
set to 135°C and 115°C respectively.

The VTJ pin is an accurate indication of the internal sili­con junction temperature (see performance curve.) The

10

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

junction temperature TJ (°C) can be deducted from the
following relation:

1.2 VTJ–

TJ75

------------------------

+=

0.00384

Where VTJ is the voltage at VTJ pin in volts.

Power Good and Power On Reset

During power up the output regulator will be disabled
until VIN reaches a value of approximately 2.9V. About
300mV hysteresis is present to eliminate noise-induced
oscillations.

Under-voltage and over-voltage conditions on the regu­lator output are detected through an internal window

1

2

6

7

EL7563C

8

9

+

-

20

19

15

14

13

12

1110

comparator. A logic high on the PG output indicates that
the regulated output voltage is within about +10% of the
nominal selected output voltage.

Power Tracking

The power tracking pins STP and STN are the inputs to
a comparator, whose HI output forces the PWM control­ler to skip switching cycle.

1. Linear Tracking

In this application, it is always the case that the lower
voltage supply VC tracks the higher output supply VP.
Please see Figure 2 below.

V

C

V

P

V

OUT

V

C

1

2

6

7

EL7563C

8

9

+

-

20

19

15

14

13

12

1110

V

P

TIME

Figure 2. Linear Power Tracking

11

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

2. Offset Tracking

The intended start-up sequence is shown in Figure 3a. In
this configuration, VC will not start until VP reaches a
preset value of:

R

B

V

×

--------------------

RARB+

1

2

6

V

IN

R

A

7

8

9

STP

STN

IN

R

B

EL7563C

+

-

20

19

15

14

13

12

1110

However, due to the superimpose of VC and VIN, the
choice of RA and RB are restricted by the following
relationship:

VP0.5

R

B

--------------------

RARB+

R

A

--------------------

V

+× VC×<+

IN

RARB+

Where 0.5 is for noise immunity. See Figure 3 below.

V

C

V

P

V

OUT

TIME

V

C

1

2

6

7

EL7563C

8

STP

9

+

-

STN

20

19

15

14

13

12

1110

V

P

Figure 3. Offset Power Tracking

12

The second way of offset tracking is to use the EN and
Power Good pins, as shown in Figure 4. In this configu­ration, VP does not have to be larger than VC.

EL7563C

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

1 20

2

3

5

6

7

8

9

10

1 20

2

3

5

6

7

8

EN

PG

EL7563C

EN

PG

EL7563C

19

18

16

15

14

13

12

11

19

18

16

15

14

13

V

C

V

P

V

C

TIME

V

P

9

10

12

11

Figure 4. Offset Tracking

13

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

3. External Soft Start

An external soft start can be combined with auxilliary
supply tracking to provide desired soft start other than
internally preset soft start (Figure 5). The appropriate
start-up time is:

tsRC

V

O

---------××=

V

IN

1

2

V

IN

R

C

6

7

EL7563C

8

STP

9

+

-

STN

Figure 5. External Soft Start

20

19

15

14

13

12

1110

V

OUT

14

4. Start-up Delay

A capacitor can be added to the EN pin to delay the con­verter start-up (Figure 6) by utilizing the pull-up current.
The delay time is approximately:

t

ms() 1200 C µF()×=

d

EL7563C

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

1

2

6

7

EL7563C

8

STP

9

+

-

STN

20

19

15

14

13

12

1110

C

V

OUT

V

IN

V

t

d

O

TIME

Figure 6. Start-up Delay

15

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

Thermal Management

The EL7563C utilizes “fused lead” packaging technol­ogy in conjunction with the system board layout to
achieve a lower thermal resistance than typically found
in standard SO20 packages. By fusing (or connecting)
multiple external leads to the die substrate within the
package, a very conductive heat path is created to the
outside of the package. This conductive heat path MUST
then be connected to a heat sinking area on the PCB in
order to dissipate heat out and away from the device.
The conductive paths for the EL7563CM package are
the fused leads: # 6, 7, 11, 12, and 13. If a sufficient
amount of PCB metal area is connected to the fused
package leads, a junction-to-ambient resistance of
43°C/W can be achieved (compared to 85°C/W for a
standard SO20 package). The general relationship
between PCB heat-sinking metal area and the thermal
resistance for this package is shown in the Performance
Curves section of this data sheet. It can be readily seen
that the thermal resistance for this package approaches
an asymptotic value of approximately 43°C/W without
any airflow, and 33°C/W with 100 LFPM airflow. Addi­tional information can be found in Application Note #8
(Measuring the Thermal Resistance of Power Surface­Mount Packages). For a thermal shutdown die junction
temperature of 135°C, and power dissipation of 1.5W,
the ambient temperature can be as high as 70°C without
airflow. With 100 LFPM airflow, the ambient tempera­ture can be extended to 85°C.

The EL7563CRE utilizes the 28-pin HTSSOP package.
The majority if heat is dissipated through the heat pad
exposed at the bottom of the package. Therefore, the
heat pad needs to be soldered to the PCB. The thermal
resistance for this package is better than that of the
SO20. Actual test results are available from Elantec
Applications staff. The actual junction temperature can
be measured at VTJ pin.

Since the thermal performance of the IC is heavily
dependent on the board layout, the system designer
should exercise care during the design phase to ensure
that the IC will operate under the worst-case environ­mental conditions.

Layout Considerations

The layout is very important for the converter to func­tion properly. Power Ground ( ) and Signal Ground (---)
should be separated to ensure that the high pulse current
in the Power Ground never interferes with the sensitive
signals connected to Signal Ground. They should only
be connected at one point (normally at the negative side
of either the input or output capacitor.)

The trace connected to the FB pin is the most sensitive
trace. It needs to be as short as possible and in a “quiet”
place, preferably between PGND or SGND traces.

In addition, the bypass capacitor connected to the VDD
pin needs to be as close to the pin as possible.

The heat of the chip is mainly dissipated through the
PGND pins. Maximizing the copper area around these
pins is preferable. In addition, a solid ground plane is
always helpful for the EMI performance.

The demo board is a good example of layout based on
these principles. Please refer to the EL7563C Applica­tion Brief for the layout.

16

Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. For the latest revision, please refer to the Elan-

EL7563C

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

tec website at http://www.elantec.com/pages/package_outline.html

17

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

EL7563C

General Disclaimer

Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir­cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.

WARNING - Life Support Policy

Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-

Elantec Semiconductor, Inc.

675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: [phone]

(888) ELANTEC
Fax: [phone]
European Office: [phone]
Japan Technical Center: [phone]

port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con­templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan­tec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.

October 5, 2001

18

Printed in U.S.A.