Datasheet EL5285CS-T7, EL5285CS Datasheet (ELANT)

Page 1
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
EL5285C - Preliminary
Features
• 4ns typ. propagation delay
• 5V to 12V input supply
• +2.7V to +5V output supply
• True-to-ground input
• Rail-to-rail outputs
• Separate analog and digital supplies
• Active low latch
• Single available (EL5185C)
• Quad available (EL5485C & EL5486C)
• Pin-compatible 6ns family available (EL5x81C, EL5283C & EL5482C)
Applications
• Threshold detection
• High speed sampling circuits
• High speed triggers
• Line receivers
• PWM circuits
• High speed V/F converters
General Description
The EL5285C comparator is designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground sensing applications.
The output side of the comparators can be supplied from a single sup­ply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5285C can be used to hold the comparator output value by applying a low logic level to the pin. The EL5285C features two separate comparators
The EL5285C is available in the 14-pin SO package and is specified for operation over the full -40°C to +85°C temperature range. Also available are a single (EL5185C) and quad versions (EL5485C and EL5486C.)
Pin Configurations
Ordering Information
Part No. Package Tape & Reel Outline #
EL5285CS 14-Pin SOIC - MDP0027
EL5285CS-T7 14-Pin SOIC 7” MDP0027
EL5285CS-T13 14-Pin SOIC 13” MDP0027
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2001 Elantec Semiconductor, Inc.
VS+
INA+
INA-
INB-
INB+
VS-
1
2
+
-
3
4
NC
5
+
6
-
7
EL5285C
(14-Pin SO)
14
13
12
11
10
9
8
VSD
OUTA
LATCHA
NC
LATCHB
OUTB
GND
September 7, 2001
Page 2
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Absolute Maximum Ratings (T
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Analog Supply Voltage (VS+ to VS-) +12V
EL5285C - Preliminary
Digital Supply Voltage (VSD to GND) +7V
Differential Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V]
= 25°C)
A
Latch Input Voltage -0.2V to [VSD+0.2V]
Storage Temperature Range -65°C to +150°C
Ambient operating Temperature -40°C to +85°C
Operating Junction Temperature 125°C
Power Dissipation TBDmW
ESD Voltage 2kV
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VS = ±5V, VSD = 5V, R
Parameter Description Condition Min Typ Max Unit
V
OS
I
B
C
IN
I
OS
V
CM
A
VO
CMRR Common-mode Rejection Ratio -5V < V
PSRR Power Supply Rejection Ratio 60 dB
V
OH
V
OL
V
LH
V
LL
I
LH
I
LL
IS+ Positive Analog Supply Current (per comparator) 10.5 mA
IS- Negative Analog Supply Current (per comparator) 7.5 mA
I
DD
td+ Positive Going Delay Time V
td- Negative Going Delay Time V
tpd+ Latch Disable to High Delay 6 ns
tpd- Latch Disable to Low Delay 8 ns
t
s
t
h
tpw(D) Minimum Latch Disable Pulse
= 2.3k, C
L
Input Offset Voltage V
= 15pF, TA = 25°C, unless otherwise specified.
L
= 0V, VO = 2.5V 2 4 mV
CM
Input Bias Current 8 15 µA
Input Capacitance 5 pF
Input Offset Current V
= 0V, VO = 2.5V 100 500 nA
CM
Input Voltage Range (VS-) - 0.1 (VS+) - 2V V
Large Signal Voltage Gain 5000 V/V
< +2.75V, VO = 2.5V 80 dB
CM
Output High Voltage V
Output Low Voltage V
> 250mV VSD - 0.5V VSD - 0.4V V
IN
> 250mV GND + 0.4V GND + 0.5V V
IN
Latch Input Voltage High 2.0 V
Latch Input Voltage Low 0.8 V
Latch Input Current High V
Latch Input Current Low V
= 3V 1 20 µA
LH
= 0.3V 40 80 µA
LL
Digital Supply Current (per comparator) 6 mA
= 5mV, CL = 15pF, I O= 2mA 4 6 ns
OD
= 5mV, CL = 15pF, IO = 2mA 4 6 ns
OD
Minimum Setup Time 2 ns
Minimum Hold Time 1 ns
Width
5 ns
2
Page 3
Typical Performance Curves
EL5285C - Preliminary
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Supply Current vs Supply Voltage (per comparator)
10
VIN=50mV RL=2.2k
8
6
(mA)
S
I
4
2
0
0 1 2 3 4 5 6
Offset Voltage vs Temperature
3
2.5
2
(mV)
1.5
OS
V
1
0.5
0
-50 -30 10 30 50 70 90
IS+
IS-
±VS (V)
-10
Temperature (°C)
Output High Voltage vs Temperature
4.832
4.83
4.828
4.826
(V)
OH
V
4.824
4.822
4.82
4.818
-50 -30 10 30 50 70 90
Input Bias Current vs Temperature
8
7
6
5
4
IB (µA)
3
2
1
0
-50 -30 30 50 90
-10
Temperature (°C)
-10
10 70
Temperature (°C)
Output Low Voltage vs Temperature
0.285
0.275
0.265
(V)
OL
V
0.255
0.245
0.235
-50 -30 10 30 50 70 90
-10
Temperature (°C)
Supply Current vs Temperature (per comparator)
12
11
10
9
8
Supply Current (mA)
7
6
-50 10 70 90
IS+
IS-
-30
Temperature (°C)
50
30-10
3
Page 4
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Typical Performance Curves
Propagation Delay vs Overdrive VIN=5V
EL5285C - Preliminary
Delay Time (ns)
Delay Time (ns)
STEP
7.8
7.6
7.4
7.2
7
6.8
6.6
6.4
6.8
6.6
6.4
6.2
6
5.8
5.6
TPD-
TPD+
0.2 0.6 1 1.4 1.8 2.2 2.6
VOD (V)
Propagation Delay vs Supply Voltage
TPD-
TPD+
4 4.2 4.8 5.2 5.4 5.6 6
4.4
54.6 5.8
±VS (V)
VS=±5V VSD=5V RL=2.2k
VSD=VS+ VOD=50mV RL=2.2k
Propagation Delay vs Source Resistance VIN=1V
STEP
15
VS=±5V VSD=5V VOD=50mV
13
RL=2.2k
11
9
Delay Time (ns)
7
5
0 1.6 2
Digital Supply Current vs Switching Frequency (per comparator)
25
VS=±5V TA=25°C
20
15
(mA)
SD
I
10
5
0
0 20 40 50
TPD-
0.4 1.20.8
Source Resistance (kΩ)
VSD=5V
10
Frequency (MHz)
TPD+
VSD=3V
30
Propagation Delay vs Overdrive VIN=1V
STEP
6.1
6
5.9
5.8
5.7
5.6
Delay Time (ns)
5.5
5.4
5.3
5.2
50 100 250 300 400 500 600
150
TPD-
TPD+
350 450 550200
VOD (mV)
VS=±5V VSD=5V RL=2.2k
Propagation Delay vs Overdrive VIN=3V
STEP
8
7.5
7
6.5
Delay Time (ns)
6
5.5
5
0.2 0.6 0.8 1.2 1.6 2
TPD-
TPD+
1 1.4 1.80.4
VOD (mV)
VS=±5V VSD=5V RL=2.2k
4
Page 5
Typical Performance Curves
EL5285C - Preliminary
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Propagation Delay vs Load Capacitance VIN=1V
STEP
9
VS=±5V
8.5
VSD=5V VOD=50mV
8
RL=2.2k
7.5
7
6.5
Delay Time (ns)
6
5.5
5
0 10 30 40 50 80 100
Output with 50MHz Input VIN=1V
P-P
Output
(5ns/div,
2V/div)
Input
(5ns/div,
0.5V/div)
TPD-
TPD+
20
60 9070
C
(pF)
LOAD
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board
0.9
0.8
833mW
0.7
0.6
0.5
0.4
0.3
Power Dissipation (W)
0.2
0.1
0
0 100755025
Output with 50MHz Input VIN=3V
Output
(5ns/div,
2V/div)
Input
(5ns/div,
2V/div)
P-P
S
O
1
1
4
2
0
°
C
/
W
Ambient Temperature (°C)
85
125
5
Page 6
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Pin Descriptions
Pin Number Pin Name Function Equivalent Circuit
EL5285C - Preliminary
1 VS+ Positive supply current
2 INA+ Positive input, channel A
VS+
IN+IN-
3 INA- Negative input, channel A (Reference Circuit 1)
4, 11 NC Not connected
5 INB+ Negative input, channel B (Reference Circuit 1)
6 INB- Positive input, channel B (Reference Circuit 1)
7 VS- Negative supply voltage
8 GND Ground
9 OUTB Output, channel B
10 LATCHB Latch input, channel B
LATCH
12 LATCHA Latch input, channel A (Reference Circuit 3)
13 OUTA Output, channel A (Reference Circuit 2)
14 VSD Digital supply voltage
Circuit 1
V
SD
VS+
VS-
Circuit 2
VS+
VS-
Circuit 3
V
SD
VS-
OUT
6
Page 7
Timing Diagram
EL5285C - Preliminary
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Latch
Enable
Input
Latch
Differential
Input
Voltage
Comparator
Output
Compare
Latch Latch
t
t
h
s
V
IN
V
OD
tpd-
Compare
tpw(D)
1.4V
V
OS
td+
2.4V
Definition of Terms
Term Definition
V
OS
V
IN
V
OD
tpd+ Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
tpd- Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
td+ Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
td- Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
t
s
t
h
tpw (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
logic threshold of an output low to high transition
logic threshold of an output high to low transition
transition to the point of the output crossing CMOS threshold in a low to high transition
transition to the point of the output crossing CMOS threshold in a high to low transition
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output
change
7
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EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
Applications Information
Power Supplies and Circuit Layout
The EL5285C comparator operates with single and dual
EL5285C - Preliminary
supply with 5V to 12V between VS+ and VS-. The out­put side of the comparator is supplied by a single supply from 2.7V to 5V. The rail to rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recom­mends a 4.7µF tantalum in parallel with a 0.1µF ceramic. These should be placed as close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also mini­mize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance sta­bility of the comparators.
Input Voltage Considerations
The EL5285C’s input range is specified from 0.1V below VS- to 2.25V below VS+. The criterion for the input limit is that the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propa­gation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredict­able. Large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage.
imum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hyster­esis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5285C, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate.
Latch Pin Dynamics
The EL5285C contains a “transparent” latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is con­nected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch’s high­to-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 6ns (latch propagation delay).
Hysteresis
Hysteresis can be added externally. The following two methods can be used to add hysteresis.
Inverting comparator with hysteresis:
V
REF
R
2
R
1
R
3
+
-
V
IN
Input Slew Rate
Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain min-
R3 adds a portion of the output to the threshold set by R and R2. The calculation of the resistor values are as follows:
8
1
Page 9
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
EL5285C - Preliminary
Select the threshold voltage VTH and calculate R1 and R2. The current through R1/R2 bias string must be many times greater than the input bias current of the comparator:
R
REF
-------------------×= R1R2+
1
VTHV
Let the hysteresis be VH, and calculate R3:
V
O
-------­V
×=
H
||
R
( R2)
1
R
3
where:
VO=VSD-0.8V (swing of the output)
Recalculate R2 to maintain the same value of VTH:
R21V
( VTH)
REF
÷
  
----------­R
TH
-------------------------------------
+=
1
 
R
3
V
VTH0.5VSD–
Non inverting comparator with hysteresis:
R
3
R
1
V
IN
+
-
V
REF
R3 adds a portion of the output to the positive input. Note that the current through R3 should be much greater than the input bias current in order to minimize errors. The calculation of the resistor values as follows:
Pick the value of R1. R
should be small (less than 1kΩ)
1
in order to minimize the propagation delay time.
Choose the hysteresis VH and calculate R3:
R
R
3V(SD
0.8)
1
--------×= V
H
Check the current through R3 and make sure that it is much greater than the input bias current as follows:
0.5VSDV
----------------------------------------
I
=
REF
R
3
The above two methods will generate hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to affect the bias string and adjustment of R1 may be required.
Power Dissipation
When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below T
(125°C).
JMAX
An approximate equation for the device power dissipa­tion is as follows. Assume the power dissipation in the load is very small:
P
DISSVSISVSDISD
)×+×(=
where:
VS is the analog supply voltage from VS+ to VS-
IS is the analog quiescent supply current per comparator
VSD is the digital supply voltage from VSD to ground
I
is the digital supply current per comparator
SD
ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipa­tion, the maximum junction temperature can be determined as follows:
T
JMAXTMAXΘJAPDISS
×+=
where:
T
is the maximum ambient temperature
MAX
θ
is the thermal resistance of the package
JA
Threshold Detector
The inverting input is connected to a reference voltage and the non-inverting input is connected to the input. As the input passes the V
threshold, the comparator's
REF
9
Page 10
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
output changes state. The non-inverting and inverting inputs may be reversed.
EL5285C - Preliminary
V
V
REF
+
IN
-
V
OUT
Crystal Oscillator
A simple crystal oscillator using one comparator of an EL5285C is shown below. The resistors R1 and R2 set the bias point at the comparator's non-inverting input. Resistors R3, R4, and C1 set the inverting input node at an appropriate DC average voltage based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the EL5285C will give the correct logic output when an input is out­side the common mode range, additional delays may occur when it is so operated. Therefore, the DC bias voltages at the inputs are set about 500mV below the
center of the common mode range and the 200 resistor
attenuates the feedback to the non-inverting input. The circuit will operate with most AT-cut crystal from 1MHz to 8MHz over a 2V to 7V supply range. The output duty cycle for this circuit is roughly 50% at 5V VCC, but it is affected by the tolerances of the resistors. The duty cycle can be adjusted by changing VCC value.
5V
5k
R
1
1.5k
R
2
C
1
0.01µF
200
+
-
2k
1MHz to
8MHz
V
OUT
R
3
R
4
2k
10
Page 11
EL5285C - Preliminary
Dual and Window 4ns High-Speed Comparators
EL5285C - Preliminary
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir­cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to sup-
Elantec Semiconductor, Inc.
675 Trade Zone Blvd. Milpitas, CA 95035 Telephone: (408) 945-1323
(888) ELANTEC Fax: (408) 945-9305 European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
port or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users con­templating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elan­tec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
September 7, 2001
11
Printed in U.S.A.
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