Datasheet EL5281CS-T7, EL5281CS-T13, EL5281CS Datasheet (ELANT)

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

Features

• 8ns Typ. Propagation Delay

• 5V to 12V Input Supply

• +2.7V to +5V Output Supply

• True-to-ground Input

• Rail-to-rail Outputs

• Active Low Latch

• Single Available (EL5181C)

• Quad Available (EL5481C &
EL5482C)

• Pin-compatible 4ns Family
Available (EL5x85C, EL5287C &
EL5486C)

Applications

• Threshold Detection

• High Speed Sampling Circuits

• High Speed Triggers

• Line Receivers

• PWM Circuits

• High Speed V/F Converters

Ordering Information

Part No. Package Tape & Reel Outline #

EL5281CS 14-Pin SO - MDP0027
EL5281CS-T7 14-Pin SO 7” MDP0027
EL5281CS-T13 14-Pin SO 13” MDP0027

General Description

The EL5281C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between VS+ and VS-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground-sensing applications.

The output side of the comparator can be supplied from a single sup­ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.

The latch input of the EL5281C can be used to hold the comparator
output value by applying a low logic level to the pin. The EL5281C
features two separate comparators.

The EL5281C is available in the 14-pin SO package and is specified
for operation over the full -40°C to +85°C temperature range. Also
available are a single (EL5181C) and quad versions (EL5481C and
EL5482C).

Pin Configuration

VS+

1

14

VSD

2

INA+

INA-

NC

INB+

INB-

VS-

Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.

© 2001 Elantec Semiconductor, Inc.

+

-

3

4

5

+

6

-

7

EL5281C

14-Pin SO

13

12

11

10

9

8

OUTA

LATCHA

NC

LATCHB

OUTB

GND

June 14, 2001

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

Absolute Maximum Ratings (T

Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied.

Analog Supply Voltage (VS+ to VS-) +12.6V
Digital Supply Voltage (VSD to GND) +7V
Differential Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V]

= 25°C)

A

Common-mode Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage -0.2V to [(VSD) +0.2V]
Storage Temperature Range -65°C to +150°C
Ambient Operating Temperature -40°C to +85°C
Operating Junction Temperature 125°C
Power Dissipation See Curves

Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the

specified temperature and are pulsed tests, therefore: TJ = TC = TA.

Electrical Characteristics

VS = ±5V, VSD = 5V, RL = 2.3kΩ, CL = 15pF, TA = 25°C, unless otherwise specified.

Parameter Description Condition Min Typ Max Unit

Input

V

OS

I

B

C

IN

I

OS

V

CM

CMRR Common-mode Rejection Ratio -5.1V < V

Output

V

OH

V

OL

Dynamic Performance

tpd+ Positive Going Delay Time VIN = 1V
tpd- Negative Going Delay Time VIN = 1V

Supply

IS+ Positive Analog Supply Current 7 8.2 mA
IS- Negative Analog Supply Current 5 6.5 mA
I

SD

PSRR Power Supply Rejection Ratio 60 80 dB

Latch

V

LH

V

LL

I

LH

I

LL

td+ Latch Disable to High Delay 6 ns
td- Latch Disable to Low Delay 6 ns
t

s

t

h

tpw(D) Minimum Latch Disable Pulse Width 10 ns

Input Offset Voltage V

= 0V, VO = 2.5V 1 4 mV

CM

Input Bias Current -6 -3.5 µA
Input Capacitance 5 pF
Input Offset Current V

= 0V, VO = 2.5V -2.5 0.5 2.5 µA

CM

Input Voltage Range (VS-) - 0.1 (VS+) - 2.25 V

< +2.75V 65 90 dB

CM

Output High Voltage V
Output Low Voltage V

> 250mV VSD - 0.6 VSD - 0.4 V

IN

> 250mV GND + 0.25 GND + 0.5 V

IN

, VOD = 50mV 8 12 ns

P-P

, VOD = 50mV 8 12 ns

P-P

Digital Supply Current Output high 4 5 mA

Output low 0.75 1 mA

Latch Input Voltage High 2.0 V
Latch Input Voltage Low 0.8 V
Latch Input Current High V
Latch Input Current Low V

= 3.0V -30 -18 µA

LH

= 0.3V -30 -24 µA

LL

Minimum Setup Time 2 ns
Minimum Hold Time 1 ns

2

Typical Performance Curves

EL5281C

EL5281C

Dual 8ns High-Speed Comparator

Positive Supply Current vs Temperature

7.15

7.1

7.05
7

6.95

+ (mA)

6.9

S

I

6.85

6.8

6.75

6.7

-50 -30 -10 10 30 50 70 90
Temperature (°C)

Positive Supply Current vs Supply Voltage

7

VS-=-5V
VSD=5V

6

VIN=50mV
TA=25°C

5

4

+ (mA)

S

3

I

2

1

0

0 71 2 3 4 5 6

VS+ (V)

Input Bias Current vs Temperature

6

5

4

3

IB (µA)

2

1

0

-50 -30 -10 10 30 50 70 90
Temperature (°C)

Negative Supply Current vs Temperature

-4.4

-4.5

-4.6

-4.7

-4.8

- (mA)

S

I

-4.9

-5

-5.1

-5.2

-50 -30 -10 10 30 50 70 90
Temperature (°C)

Negative Supply Current vs Negative Supply
Voltage

5.5
VS+=5V
VSD=5V
VIN=50mV

5

TA=25°C

4.5

- (mA)

S

I

4

3.5

3

0 71 2 3 4 5 6

VS- (V)

Offset Voltage vs Temperature

0.7

0.6

0.5

0.4

0.3

(mV)

0.2

OS

V

0.1

0

-0.1

-0.2

-0.3

-50 -30 -10 10 30 50 70 90
Temperature (°C)

3

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

Typical Performance Curves

Propagation Delay vs Overdrive

10

VS=±5V

9.5

VSD=5V
VIN=1V Step

9

RL=2.2kΩ

8.5
8

7.5
7

Delay Time (ns)

6.5
6

5.5
5

0 100 200 300 400 500 600

Propagation Delay vs Supply Voltage

10

VSD=VS+

9.5

VIN=1V Step
VOD=50mV

9

RL=2.2kΩ

8.5
8

7.5
7

Delay Time (ns)

6.5
6

5.5
5

4 4.5 5 5.5 6

Tpd+

Tpd-

VOD (mV)

Tpd+

Tpd-

±VS (V)

Propagation Delay vs Load Capacitance

12

VS=±5V
VSD=5V

11

RL=2.2kΩ
VIN=1V Step
VOD=50mV

10

9

Delay Time (ns)

8

7

6

0 20 40 60 80 100 120

Propagation Delay vs Overdrive

10

9.5
9

8.5
8

7.5

Delay Time (ns)

VS=±5V

7

VSD=5V
VIN=3V Step

6.5

RL=2.2kΩ

6

0 0.2 0.6 1 1.2 1.6 2

0.4 0.8 1.4 1.8

Tpd+

Tpd-

C

LOAD

VOD (V)

(pF)

Tpd+

Tpd-

Propagation Delay vs Overdrive

11

VS=±5V

10.5

VSD=5V
RL=2.2kΩ

10

VIN=5V Step

9.5
9

8.5

Delay Time (ns)

8

7.5
7

0 0.5 1 2 3

Tpd+

Tpd-

1.5 2.5

VOD (V)

Propagation Delay vs Source Resistance

20

VS=±5V

18

VSD=5V
RL=2.2kΩ

16

VIN=1V Step
VOD=50mV

14
12
10

Delay Time (ns)

8
6
4

0 0.2 0.4 1 1.6

Tpd+

Tpd-

0.6 1.41.20.8

Source Resistance (kΩ)

4

Typical Performance Curves

EL5281C

EL5281C

Dual 8ns High-Speed Comparator

Output Low Voltage vs Load Current

0.31

0.27

TA=25°C

0.23

Output Low Voltage (V)

0.19

0.15
0 102 4 6

Digital Supply Current vs Input Switching
Frequency

30

VS=±5V

25

20

15

(mA)

SD

I

10

5

0

0 453525155

TA=85°C

TA=-40°C

Load Current (mA)

VSD=5V

Frequency (MHz)

VSD=3V

VS=±5V
VSD=5V
VIN=-50mV

8

Output High Voltage vs Load Current

4.75

4.7

4.65

4.6

4.55

4.5

4.45

Output High Voltage (V)

4.4

4.35

4.3
0 102 4 6

Package Power Dissipation vs Ambient Temp.

JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board

0.9

0.8

833mW

0.7

0.6

0.5

0.4

0.3

Power Dissipation (W)

0.2

0.1

0

5040302010

0 100755025

TA=-40°C

TA=85°C

Load Current (mA)

S

O

1

1

4

2

0

°

C

/

W

Ambient Temperature (°C)

TA=25°C

85

VS=±5V
VSD=5V
VIN=50mV

8

125

Output with 30MHz Input
VIN=1V

P-P

V

O

V

IN

1V 20ns

Output with 30MHz Input
VIN=3V

P-P

VIN=1V
FIN=30MHz

2V

VS=±5V

P-P

VSD=5V

V

O

V

IN

2V 2V 20ns

VIN=3V

P-P

FIN=30MHz

VS=±5V
VSD=5V

5

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

Timing Diagram

Latch

Enable

Input

Latch

Differential

Input

Voltage

Comparator

Output

Compare

Latch Latch

t

t

h

s

V

IN

V

OD

tpd-

Compare

tpw(D)

1.4V

V

OS

td+

2.4V

Definition of Terms

Terms Definition

V

OS

V

IN

V

OD

tpd+ Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS

tpd- Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS

td+ Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high

td- Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high

t

s

t

h

tpw (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal

Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications

logic threshold of an output low to high transition

logic threshold of an output high to low transition

transition to the point of the output crossing CMOS threshold in a low to high transition

transition to the point of the output crossing CMOS threshold in a high to low transition
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in

order to be acquired and held at the outputs
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in

order to be acquired and held at the output

change

6

Dual 8ns High-Speed Comparator

Pin Descriptions - EL5281C (14-Pin SO)

Pin Number Pin Name Function Equivalent Circuit

1 VS+ Positive supply current
2 INA+ Positive input, channel A

Circuit 1

3 INA- Negative input, channel A (Reference Circuit 1)

4, 11 NC Not connected

5 INB+ Negative input, channel B (Reference Circuit 1)
6 INB- Positive input, channel B (Reference Circuit 1)
7 VS- Negative supply voltage
8 GND Ground
9 OUTB Output, channel B

V

SD

VS+

EL5281C

EL5281C

VS+

IN+IN-

VS-

10 LATCHB Latch input, channel B

LATCH

12 LATCHA Latch input, channel A (Reference Circuit 3)
13 OUTA Output, channel A (Reference Circuit 2)
14 VSD Digital supply voltage

7

VS+

VS-

VS-

Circuit 2

Circuit 3

OUT

V

SD

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

Applications Information

Power Supplies and Circuit Layout

The EL5281C comparator operates with single and dual
supply with 5V to 12V between VS+ and VS-. The out­put side of the comparator is supplied by a single supply
from 2.7V to 5V. The rail-to-rail output swing enables
direct connection of the comparator to both CMOS and
TTL logic circuits. As with many high speed devices,
the supplies must be well bypassed. Elantec recom­mends a 4.7µF tantalum in parallel with a 0.1µF
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also mini­mize unwanted parasitic feedback around the
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance sta­bility of the comparator.

Input Voltage Considerations

The EL5281C input range is specified from 0.1V below
VS- to 2.25V below VS+. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the cor­rect logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differ­ential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage. Inputs of
unused channels should not be left floating. They should
be driven to a known state. For example, one input can
be tied to ground and the other input can be connected to
some voltage reference (like ±100mV) to avoid oscilla­tion in the output due to unwanted output to input
feedback.

Input Slew Rate

Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain min­imum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hyster­esis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5281C, the propagation delay increases when the
input slew rate increases for low overdrive voltages.
With high overdrive voltages, the propagation delay
does not change much with the input slew rate.

Latch Pin Dynamics

The EL5281C contains a “transparent” latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is con­nected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
remains latched to its value just before the latch’s high­to-low transition. To guarantee data retention, the input
signal must remain the same state at least 1ns (hold time)
after the latch goes low and at least 2ns (setup time)
before the latch goes low. When the latch goes high, the
new data will appear at the output in approximately 6ns
(latch propagation delay).

Hysteresis

Hysteresis can be added externally. The following two
methods can be used to add hysteresis.

Inverting comparator with hysteresis:

V

REF

R

2

R

1

R

3

+

-

V

IN

8

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

R3 adds a portion of the output to the threshold set by R
and R2. The calculation of the resistor values are as
follows:

Select the threshold voltage VTH and calculate R1 and
R2. The current through R1/R2 bias string must be many
times greater than the input bias current of the
comparator:

R

REF

-------------------×=
R1R2+

1

VTHV

Let the hysteresis be VH, and calculate R3:

V

O

R

3

||

--------R1( R2)

×=

V

H

where:

VO=VSD-0.8V (swing of the output)

Recalculate R2 to maintain the same value of VTH:

R21V

( VTH)

REF

÷–





----------­R

TH

-------------------------------------

+=

1




R



3

V

VTH0.5VSD–

Non inverting comparator with hysteresis:

R

3

R

1

V

IN

+

-

V

REF

R3 adds a portion of the output to the positive input.
Note that the current through R3 should be much greater
than the input bias current in order to minimize errors.
The calculation of the resistor values as follows:

Pick the value of R1. R1 should be small (less than 1kΩ)
in order to minimize the propagation delay time.

Choose the hysteresis VH and calculate R3:

R

R3V(

SD

0.8)

1

--------×–=
V

H

Check the current through R3 and make sure that it is

1

much greater than the input bias current as follows:

0.5VSDV

–

I

----------------------------------------=

REF

R

3

The above two methods will generate hysteresis of up to
a few hundred millivolts. Beyond that, the impedance of
R3 is low enough to affect the bias string and adjustment
of R1 may be required.

Power Dissipation

When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
T

(125°C).

JMAX

An approximate equation for the device power dissipa­tion is as follows. Assume the power dissipation in the
load is very small:

P

DISSVSISVSDISD

where:

VS is the analog supply voltage from VS+ to VS­IS is the analog quiescent supply current per comparator
VSD is the digital supply voltage from VSD to ground
I

is the digital supply current per comparator

SD

N is the number of comparators in the package

ISD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipa­tion, the maximum junction temperature can be
determined as follows:

T

JMAXTMAXΘJAPDISS

where:

T

is the maximum ambient temperature

MAX

θJA is the thermal resistance of the package

) N××+×(=

×+=

9

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

Threshold Detector

The inverting input is connected to a reference voltage
and the non-inverting input is connected to the input. As
the input passes the V
output changes state. The non-inverting and inverting
inputs may be reversed.

V

V

REF

Crystal Oscillator

A simple crystal oscillator using one comparator of an
EL5281C is shown below. The resistors R1 and R2 set
the bias point at the comparator's non-inverting input.
Resistors R3, R4, and C1 set the inverting input node at
an appropriate DC average voltage based on the output.
The crystal's path provides resonant positive feedback
and stable oscillation occurs. Although the EL5281C
will give the correct logic output when an input is out­side the common mode range, additional delays may
occur when it is so operated. Therefore, the DC bias
voltages at the inputs are set about 500mV below the
center of the common mode range and the 200Ω resistor
attenuates the feedback to the non-inverting input. The
circuit will operate with most AT-cut crystal from 1MHz
to 8MHz over a 2V to 7V supply range. The output duty
cycle for this circuit is roughly 50% at 5V VCC, but it is
affected by the tolerances of the resistors. The duty cycle
can be adjusted by changing VCC value.

threshold, the comparator's

REF

+

IN

-

V

OUT

5V

5kΩ

R

1

1.5kΩ

R

2

C

1

0.01µF

200Ω

+

-

2kΩ

1MHz to

8MHz

V

OUT

R

3

R

4

2kΩ

10

EL5281C

Dual 8ns High-Speed Comparator

EL5281C

General Disclaimer

Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir­cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.

WARNING - Life Support Policy

Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-

Elantec Semiconductor, Inc.

675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: [phone]

(888) ELANTEC
Fax: [phone]
European Office: [phone]
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port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con­templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan­tec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.

June 14, 2001

11

Printed in U.S.A.