Page 1
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Features
• 12MHz -3dB bandwidth
• Unity gain buffer
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) =
500µA
• High slew rate = 10V/µs
• Rail-to-rail operation
Applications
• TFT-LCD drive circuits
• Electronics notebooks
• Electronics games
• Personal communication devices
• Personal Digital Assistants (PDA)
• Portable instrumentation
• Wireless LANs
• Office automation
• Active filters
• ADC/DAC buffer
Ordering Information
Part No. Package Tape & Re el Outline #
EL5221CW-T7 SOT23-6 7” MDP0038
EL5221CW-T13 SOT23-6 13” MDP0038
EL5221CY-T7 MSOP-8 7” MDP0043
EL5221CY-T13 MSOP-8 13” MDP0043
General Description
The EL5221C is a dual, low power, high voltage rail-to-rail input-output buffer. Operating on supplies ranging from 5V to 15V, while
consuming only 500µA per channel, the EL5221C has a bandwidth of
12MHz (-3dB). The EL5221C also provides rail-to-rail input and output ability, giving the maximum dynamic range at any supply voltage.
The EL5221C also features fast slewing and settling times, as well as
a high output drive capability of 30mA (sink and source). These features make the EL5221C ideal for use as voltage reference buffers in
Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other
applications include battery power, portable devices, and anywhere
low power consumption is important.
The EL5221C is available in space-saving SOT23-6 and MSOP-8
packages and operates over a temperature range of -40°C to +85°C.
Connection Diagrams
VINA
VS-
VINB
1
2
3
6
5
4
VOUTA
VS+
VOUTB
SOT23-6
1
VOUTA
2
NC
3
VINA
4
MSOP-8
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2000 Elantec Semiconductor, Inc.
8
7
6
5
VS+
VOUTB
NC
VINBVS-
November 7, 2000
Page 2
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Absolute Maximum Ratings (T
Values beyond absolute maximum ratings can cause the device to be prematurely damaged. Absolute maximum ratings are stress ratings only and
functional device operation is not implied
Supply Voltage between V
Input Voltage V
Maximum Continuous Output Current 30mA
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: T
+ and VS- +18V
S
= 25°C)
A
- - 0.5V, VS+ +0.5V
S
= TC = T
J
A
Maximum Die Temperature +125°C
Storage Temperature -65°C to +150°C
Operating Temperature -40°C to +85°C
Power Dissipation See Curves
ESD Voltage 2kV
Electrical Characteristics
VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = 25°C unless otherwise specified.
Parameter Description Condition Min Typ Max Unit
Input Characteristics
V
OS
TCV
I
B
R
IN
C
IN
A
V
Output Characteristics
V
OL
V
OH
I
SC
Power Supply Performance
PSRR Power Supply Rejection Ratio V
I
S
Dynamic Performance
SR Slew Rate
t
S
BW -3dB Bandwidth R
CS Channel Separation f = 5MHz 75 dB
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
Input Offset Voltage V
Average Offset Voltage Drift
OS
Input Bias Current V
Input Impedance 1GΩ
Input Capacitance 1.35 pF Voltage Gain -4.5V ≤ V
Output Swing Low IL = -5mA -4.92 -4.85 V
Output Swing High IL = 5mA 4.85 4.92 V
Short Circuit Current Short to GND ±120 mA
Supply Current (Per Buffer) No Load 500 750 µA
[2]
Settling to +0.1% VO=2V Step 500 ns
= 0V 2 12 mV
CM
[1]
= 0V 2 50 nA
CM
≤ 4.5V 0.995 1.005 V/V
OUT
is moved from ±2.25V to ±7.75V 60 80 dB
S
-4.0V ≤ V
= 10kΩ, CL = 10pF 12 MHz
L
≤ 4.0V, 20% to 80% 7 10 V/µs
OUT
5µV/°C
2
Page 3
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Electrical Characteristics
VS+ = +5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = 25°C unless otherwise specified.
Parameter Description Condition Min Typ Max Unit
Input Characteristics
V
OS
TCV
OS
I
B
R
IN
C
IN
A
V
Output Characteristics
V
OL
V
OH
I
SC
Power Supply Performance
PSRR Power Supply Rejection Ratio V
I
S
Dynamic Performance
SR Slew Rate
t
S
BW -3dB Bandwidth R
CS Channel Separation f = 5MHz 75 dB
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
Input Offset Voltage V
Average Offset Voltage Drift
Input Bias Current V
Input Impedance 1GΩ
Input Capacitance 1.35 pF Voltage Gain 0.5 ≤ V
Output Swing Low IL = -5mA 80 150 mV
Output Swing High IL = 5mA 4.85 4.92 V
Short Circuit Current Short to GND ±120 mA
Supply Current (Per Buffer) No Load 500 750 µ A
[2]
Settling to +0.1% VO = 2V Step 500 ns
= 2.5V 2 10 mV
CM
[1]
= 2.5V 2 50 nA
CM
≤ 4.5V 0.995 1.005 V/V
OUT
is moved from 4.5V to 15.5V 60 80 dB
S
1V ≤ V
≤4V, 20% to 80% 7 10 V/µs
OUT
= 10 kΩ, CL = 10pF 12 MHz
L
5µV/°C
EL5221C
3
Page 4
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Electrical Characteristics
VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = 25°C unless otherwise specified.
Parameter Description Condition Min Typ Max Unit
Input Characteristics
V
OS
TCV
OS
I
B
R
IN
C
IN
A
V
Output Characteristics
V
OL
V
OH
I
SC
Power Supply Performance
PSRR Power Supply Rejection Ratio V
I
S
Dynamic Performance
SR Slew Rate
t
S
BW -3dB Bandwidth R
CS Channel Separation f = 5MHz 75 dB
1. Measured over the operating temperature range
2. Slew rate is measured on rising and falling edges
Input Offset Voltage V
Average Offset Voltage Drift
Input Bias Current V
Input Impedance 1GΩ
Input Capacitance 1.35 pF Voltage Gain 0.5 ≤ V
Output Swing Low IL = -5mA 80 150 mV
Output Swing High IL = 5mA 14.85 14.92 V
Short Circuit Current Short to GND ±120 mA
Supply Current (Per Buffer) No Load 500 750 µ A
[2]
Settling to +0.1% VO = 2V Step 500 ns
= 7.5V 2 14 mV
CM
[1]
= 7.5V 2 50 nA
CM
≤ 14.5V 0.995 1.005 V/V
OUT
is moved from 4.5V to 15.5V 60 80 dB
S
1V ≤ V
≤14V, 20% to 80% 7 10 V/µ s
OUT
= 10 kΩ, CL = 10pF 12 MHz
L
5µV/°C
4
Page 5
Typical Performance Curves
EL5221C
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Input Offset Voltage Distribution
2000
VS=±5V
=25°C
T
A
1600
1200
800
Quantity (Buffers)
400
0
10
5
0
Input Offset Voltage (mV)
-5
-10
-8-6-4
-12
-10
Input Offset Voltage (mV)
Input Offset Voltage vs Temperature
0150
Temperature (°C)
024
-2
50-50 100
Typical
Production
Distribution
6
VS=±5V
Input Offset Voltage Drift
35
VS=±5V
30
=25°C
T
A
25
20
15
Quantity (Buf fers)
10
5
0
1
3
5
7
8
10
12
Input Bias Current vs Temperature
4
2
0
Input Bias Current (nA)
-2
-4
Input Offset Voltage, TCVOS (µV/°C)
VS=±5V
9
0 15050-50 100
Temperature (°C)
Typical
Production
Distribution
11
13
15
17
19
Output High Voltage vs Temperature
4.97
4.96
4.95
Output High Voltage (V)
4.94
4.93
-50 0 50 100 150
Temperature (°C)
VS=±5V
I
=5mA
OUT
Output Low Voltage vs Temperature
-4.91
-4.92
-4.93
-4.94
-4.95
Output Low Voltage (V)
-4.96
-4.97
VS=±5V
I
=-5mA
OUT
0 15050-50 100
Temperature (°C)
5
Page 6
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Typical Performance Curves
Voltage Gain vs Temperature
1.001
1.0005
1.0000
Voltage Gain (V/V)
0.9995
0.999
-50 0 50 100 150
Supply Current per Channel vs Temperature
0.55
0.5
0.45
Supply Current (mA)
0.4
Temperature (°C)
0 150
Temperature (°C)
VS=±5V
VS=±5V
50-50 100
Slew Rate vs Temperature
13
12.5
12
11.5
11
Slew Rate (V/µ S)
10.5
10
Supply Current per Channel vs Supply Voltage
650
550
450
Supply Current (µA)
350
250
0 150
TA=25°C
520
50-50 100
Temperature (°C)
100
Supply Voltage (V)
VS=±5V
15
Frequency Response for Various R
5
0
CL=10pF
-5
VS=±5V
-10
Magnitude (Normalized) (dB)
-15
100k
1M 100M
Frequency (Hz)
10M
L
10kΩ
1kΩ
560Ω
150Ω
Frequency Response for Various C
20
RL=10kΩ
VS=±5V
10
0
-10
Magnitude (Normalized) (dB)
-20
-30
1M
1000pF
Frequency (Hz)
L
12pF
50pF
100pF
10M100k
100M
6
Page 7
Typical Performance Curves
EL5221C
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
Output Impedance vs Frequency
200
VS=±5V
160
TA=25°C
120
80
Output Impedance (Ω)
40
0
10k 100k
PSRR vs Frequency
80
PSRR+
PSRR-
60
40
PSRR (dB)
VS=±5V
20
TA=25°C
0
100
1k
Frequency (Hz)
10k
Frequency (Hz)
100k
Maximum Output Swing vs Frequency
12
10
)
P-P
8
VS=±5V
TA=25°C
6
RL=10kΩ
CL=12pF
4
Distortion <1%
Maximum Output Swing (V
2
0
1M
10M
1M
10M
10k 100k
Input Voltage Noise Spectral Density vs Frequency
600
100
10
Voltage Noise (nV√Hz)
1
100 100k 100M
Frequency (Hz)
Frequency (Hz)
1M
10M
10M1k 10k 1M
Total Harmonic Distortion + Noise vs Frequency
0.010
0.009
0.008
0.007
0.006
0.005
THD+ N (%)
VS=±5V
0.004
RL=10kΩ
VIN=1V
0.003
0.002
0.001
RMS
1k 10k 100k
Frequency (Hz)
Channel Separation vs Frequency Response
-60
Dual measured Channel A to B
Quad measured Channel A to D or B to C
Other combinations yield improved rejection.
-80
VS=±5V
RL=10kΩ
VIN=220mV
-100
X-Talk (dB)
-120
-140
1k
RMS
1M 6M10k 100k
Frequency (Hz)
7
Page 8
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Typical Performance Curves
Small-Signal Overshoot vs Load Capacitance
100
VS=±5V
80
=10kΩ
R
L
VIN=±50mV
T
=25°C
A
60
40
Overshoot (%)
20
10 100 1000
Large Signal Transient Response
Load Capacitance (pF)
1µS1V
VS=±5V
=25°C
T
A
RL=10kΩ
C
=12pF
L
Settling Time vs Step Size
5
VS=±5V
4
R
=10kΩ
L
3
CL=12pF
=25°C
T
A
2
1
0
-1
Step Size (V)
-2
-3
-4
-50
Small Signal Transient Response
200 400
Settling Time (nS)
200ns50mV
6000
VS=±5V
TA=25°C
R
C
0.1%
0.1%
=10kΩ
L
=12pF
L
800
8
Page 9
Pin Descriptions
SOT23-6 MSOP-8
13V
Name Function Equivalent Circuit
Pin
INA
Buffer A Input
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
V
S+
V
S-
Circuit 1
EL5221C
24V
35V
47V
58V
61V
- Negative Supply Voltage
S
Buffer B Input (Reference Circuit 1)
INB
Buffer B Output
OUTB
+ Positive Supply Voltage
S
Buffer A Output (Reference Circuit 2)
OUTA
GND
Circuit 2
V
S+
V
S-
9
Page 10
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Applications Information
Product Description
The EL5221C unity gain buffer is fabricated using a
high voltage CMOS process. It exhibits rail-to-rail input
and output capability and has low power consumption
(500µA per buffer). These features make the EL5221C
ideal for a wide range of general-purpose applications.
When driving a load of 10kΩ and 12pF, the EL5221C
has a -3dB bandwidth of 12MHz and exhibits 10V/µ S
slew rate.
Operating Voltage, Input, and Output
The EL5221C is specified with a single nominal supply
voltage from 5V to 15V or a split supply with its total
range from 5V to 15V. Correct operation is guaranteed
for a supply range of 4.5V to 16.5V. Most EL5221C
specifications are stable over both the full supply range
and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature
are shown in the typical performance curves.
The output swings of the EL5221C typically extend to
within 80mV of positive and negative supply rails with
load currents of 5mA. Decreasing load currents will
extend the output voltage range even closer to the supply
rails. Figure 1 shows the input and output waveforms for
the device. Operation is from ±5V supply with a 10kΩ
load connected to GND. The input is a 10V
The output voltage is approximately 9.985V
5V
10µS
sinusoid.
P-P
.
P-P
Short Circuit Current Limit
The EL5221C will limit the short circuit current to
±120mA if the output is directly shorted to the positive
or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never
exceeds ±30mA. This limit is set by the design of the
internal metal interconnects.
Output Phase Reversal
The EL5221C is immune to phase reversal as long as the
input voltage is limited from V
Figure 2 shows a photo of the output of the device with
the input voltage driven beyond the supply rails.
Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V,
electrostatic protection diodes placed in the input stage
of the device begin to conduct and overvoltage damage
could occur.
1V
- -0.5V to VS+ +0.5V.
S
10µS
VS=±2.5V
=25°C
T
A
VIN=6V
P-P
VS=±5V
TA=25°C
VIN=10V
P-P
5V
Output Input
Figure 1. Operation with Rail-to-Rail Input and
Output
1V
Figure 2. Operation with Beyond-the-Rails
Input
Power Dissipation
With the high-output drive capability of the EL5221C
buffer, it is possible to exceed the 125°C 'absolute-maximum junction temperature' under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
10
Page 11
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
determine if load conditions need to be modified for the
buffer to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T
–
P
DMAX
JMAXTAMAX
---------------------------------------------=
Θ
JA
where:
= Maximum Junction Temperature
T
JMAX
T
= Maximum Ambient Temperature
AMAX
= Thermal Resistance of the Package
Θ
JA
P
= Maximum Power Dissipation in the
DMAX
Package
The maximum power dissipation actually produced by
an IC is the total quiescent supply current times the total
power supply voltage, plus the power in the IC due to the
loads, or:
P
DMAX
ΣiV[SI
SMAXVS
+( V
OUT
i ) I
LOAD
i ]×–+×=
when sourcing, and
P
DMAX
ΣiV[SI
SMAXV(OUTiVS
- ) I
LOAD
i×–+×]=
when sinking.
where:
i = 1 to 2 for Dual Buffer
= Total Supply Voltage
V
S
I
= Maximum Supply Current Per Channel
SMAX
V
i = Maximum Output Voltage of the
OUT
Application
I
i = Load Current
LOAD
If we set the two P
we can solve for R
equations equal to each other,
DMAX
i to avoid device overheat. Fig-
LOAD
ure 3 and Figure 4 provide a convenient way to see if the
device will overheat. The maximum safe power dissipation can be found graphically, based on the package type
and the ambient temperature. By using the previous
equation, it is a simple matter to see if P
DMAX
exceeds
the device’s power derating curves. To ensure proper
operation, it is important to observe the recommended
derating curves shown in Figure 3 and Figure 4.
Package Mounted on a JEDEC JESD51-7 High
Effective Thermal Conductivity Test Board
1
870mW
0.8
M
S
0.6
435mW
0.4
Power Dissipation (W)
0.2
0
O
P
-
8
1
1
5
°
C
/
S
W
O
T
2
3
-
6
2
3
0
°
C
/
W
50 150100012525 75 85
Ambient Temperature (°C)
MAX TJ=125°C
Figure 3. Package Power Dissipation vs
Ambient Temperature
Package Mounted on a JEDEC JESD51-3 Low
Effective Thermal Conductivity Test Board
0.6
486mW
0.5
391mW
0.4
0.3
0.2
Power Dissipation (W)
0.1
0
M
S
O
P
-
8
2
S
0
O
T
2
3
-
6
2
5
6
°
C
/
W
50 150100012525 75 85
Ambient T emperatu re (°C)
MAX TJ=125°C
6
°
C
/
W
Figure 4. Package Power Dissipation vs
Ambient Temperature
Unused Buffers
It is recommended that any unused buffer have the input
tied to the ground plane.
11
Page 12
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
Driving Capacitive Loads
The EL5221C can drive a wide range of capacitive
loads. As load capacitance increases, however, the -3dB
bandwidth of the device will decrease and the peaking
increase. The buffers drive 10pF loads in parallel with
10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB
of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and
50Ω) can be placed in series with the output. However,
this will obviously reduce the gain slightly. Another
method of reducing peaking is to add a "snubber" circuit
at the output. A snubber is a shunt load consisting of a
resistor in series with a capacitor. Values of 150Ω and
10nF are typical. The advantage of a snubber is that it
does not draw any DC load current or reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5221C can provide gain at high frequency. As
with any high frequency device, good printed circuit
board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible, and the power
supply pins must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, where
- pin is connected to ground, a 0.1µF ceramic
the V
S
capacitor should be placed from V
4.7µF tantalum capacitor should then be connected in
parallel, placed in the region of the buffer. One 4.7µF
capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply
pin to ground if split supplies are to be used.
+ to pin to VS- pin. A
S
12
Page 13
EL5221C
Dual 12MHz Rail-to-Rail Input-Output Buffer
EL5221C
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
Fax: (408) 945-9305
European Office: +44-118-977-6080
Japan Technical Center: +81-45-682-5820
November 7, 2000
(888) ELANTEC
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
13
Printed in U.S.A.
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