Datasheet EE-299 Datasheet (ANALOG DEVICES)

Engineer-to-Engineer Note EE-299

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Estimating Power Dissipation for ADSP-21368 SHARC® Processors

Contributed by Chris C. and John C. Rev 3 – June 22, 2009

Introduction

This EE-Note discusses power consumption of
ADSP-21367, ADSP-21368, and ADSP-21369
SHARC® processors (hereafter referred to as
ADSP-21368 processors) based on
characterization data measured over power
supply voltage, core frequency (CCLK), and
junction temperature (TJ). The intent of this
document is to assist board designers in
estimating their power budget for power supply
design and thermal relief designs using ADSP­21368 processors.

ADSP-21368 processors are members of the
SIMD SHARC family of processors, featuring
Analog Devices Super Harvard Architecture.
Like other SHARC processors, the ADSP-21368
is a 32-bit processor optimized for high-precision
signal processing applications.

drivers (i.e., the I/O). The following sections
detail how to derive both of these components
for estimating total power consumption based on
different dynamic activity levels, I/O activity,
power supply settings, core frequencies, and
environmental conditions.

Estimating Internal Power Consumption

The total power consumption due to internal
circuitry (on the V
static power component and dynamic power
component of the processor’s core logic. The
dynamic portion of the internal power is
dependent on the instruction execution sequence,
the data operands involved, and the instruction
rate. The static portion of the internal power is a
function of temperature and voltage; it is not
related to processor activity.

supply) is the sum of the

DDINT

ADSP-21368 processors are offered in the
commercial and industrial temperature ranges at
core clock frequencies of 266-333 and 400 MHz.
The 266-333 MHz processors operate at a core
voltage of 1.2 V (V

), and the 400 MHz

DDINT

processors operate at a core voltage of 1.3 V
(V
operates at 3.3 V (V

). The I/O of all ADSP-21368 processors

DDINT

).

DDEXT

Analog Devices provides current consumption
figures and scaling factors for discrete dynamic
activity levels. System application code can be
mapped to these discrete numbers to estimate the
dynamic portion of the internal power
consumption for an ADSP-21368 processor in a
given application.

The total power consumption of the ADSP­21368 processor is the sum of the power
consumed for each of the power supply domains
(V

DDINT, VDDEXT,

and A

). The total power

VDD

consumption has two components: one due to
internal circuitry (i.e., the core and the PLL), and
the other due to the switching of external output

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Internal Power Vector Definitions and Activity Levels

The following power vector definitions define
the dynamic activity levels that apply to the
internal power vectors shown in Table 1.

 I

DD-IDLE VDDINT

supply current for idle

activity. Idle activity is the core executing the

IDLE instruction only, with no core memory

accesses, no DMA, and no interrupts.

 I

DD-INLOW VDDINT

supply current for low

activity. Low activity is the core executing a
single-function instruction fetched from
internal memory, with no core memory
accesses, no DMA, and no activity on the
external port.

 I

DD-INMED VDDINT

supply current for medium

activity. Medium activity is the core
executing a multi-function instruction fetched
from internal memory and a NOP, with 8 core
memory accesses per CLKIN cycle (DMx64),
DMA through three SPORTs running at

3.47 MHz, and no SDRAM or AMI activity
on the external port. The DMA is chained to
itself (running continuously) and does not use
interrupts. The bit pattern for each core
memory access and DMA is random.

 I

DD-INHIGH VDDINT

supply current for high

activity. High activity is the core executing a
multi-function instruction fetched from
internal memory, with 16 core memory
accesses per

CLKIN cycle (DMx64) and DMA

through three SPORTs running at 3.47 MHz,
and no SDRAM or AMI activity on the
external port. The DMA is chained to itself
(running continuously) and does not use
interrupts. The bit pattern for each core
memory access and DMA is random.

multi-function instruction fetched from
internal memory and/or cache, with 32 core
memory accesses per CLKIN cycle (DMx64,
PMx64), DMA through six SPORTs running
at 41.67 MHz, and no SDRAM or AMI
activity on the external port. The DMA is
chained to itself (running continuously) and
does not use interrupts. The bit pattern for
each core memory access and DMA is
random.



The test code used to measure I

represents worst-case

INPEAK

DD-

processor operation. This activity
level is not sustainable under
normal application conditions.

 I

DD-INPEAK-TYP VDDINT

supply current for

typical peak activity. Typical peak activity is
the core executing a multi-function
instruction fetched from internal memory
and/or cache, with 32 core memory accesses
per CLKIN cycle (DMx64, PMx64), DMA
through six SPORTs running at 41.67 MHz,
DMA through one SPI running at 833 KHz,
and SDRAM accesses through the external
port running at 166 MHz. The DMA is
chained to itself (running continuously) and
does not use interrupts. The bit pattern for
each core memory access, DMA and
SDRAM access is random. The SDRAM
accesses are split between 60% reads and
40% writes.

Table 1 summarizes the low, medium, high,

peak, and typical peak dynamic activity levels
corresponding to the internal power vectors
listed above and in Table 2.

 I

DD-INPEAK VDDINT

supply current for peak

activity. Peak activity is the core executing a

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 2 of 12

Operation Low Medium High Peak Peak (Typical)

Instruction Type Single-function Multi-function Multi-function Multi-function Multi-function
Instruction Fetch Int Memory Int Memory,

NOP

Core Memory Access 1 None 8 per tCK cycle 2 16 per tCK cycle 2 32 per tCK cycle 3 32 per tCK cycle 3
DMA Transmit Int to Ext

Ext Port SDRAM
SPORTs
SPI

Data Bit Pattern for Core
Memory Access and DMA

Ratio – Continuous Instruction
Loop to SDRAM Control Code

Table 1. Dynamic activity level definitions

SDCLK only
N/A
N/A

N/A Random Random Random Random

100% Instruct
Loop

SDCLK only
3 @ 1/96*CCLK
N/A

100% Instruction
Loop

Int Memory Int Memory,

Cache

SDCLK only
3 @ 1/96*CCLK
N/A

100% Instruction
Loop

SDCLK only
6 @ 1/8*CCLK
N/A

100% Instruction
Loop

Int Memory,
Cache

60/40 RD/WR
6 @ 1/8*CCLK
N/A

50::50
60::40
70::30

Estimating I

Dynamic Current, I

DDINT

DD-DYN

Two steps are involved in estimating the
dynamic power consumption due to the internal
circuitry (i.e., on the V

supply). The first

DDINT

step is to determine the dynamic baseline current,
and the second step is to determine the
percentage of activity for each discrete power
vector with respect to the entire application.

IDD Baseline Dynamic Current, I

The ADSP-21368 I

DD_BASELINE_DYN

DD-BASELINE-DYN

current graph

is shown in Appendix A. Note that the

I

DD_BASELINE_DYN

I

DD-INHIGH

dynamic activity level vs. core

current is derived using the

frequency. Each curve in the graph represents a
baseline I

dynamic current for a specified

DDINT

power supply setting. Using the curve specific to
the application, the baseline dynamic current
(I

DD_BASELINE_DYN

) for the V

power supply

DDINT

example, with the core operating at 1.2 V
(V

) and a frequency of 333 MHz, the

DDINT

corresponding baseline dynamic current
(I

DD_BASELINE_DYN

) for the V

power supply

DDINT

domain would be approximately 0.76 A.

IDD Dynamic Current Running Your Application

Table 2 lists the scaling factor for each activity

level, used to estimate the dynamic current for
each specific application. With knowledge of the
program flow and an estimate of the percentage
of time spent at each activity level, the system
developer can use the baseline dynamic current
(I

DD_BASELINE_DYN

) shown in Figure 4 and the
corresponding activity scaling factor from

Table 2 to determine the dynamic portion of the

internal current (I

) for each ADSP-21368

DD-DYN

processor in a system.

domain can be estimated at the operating
frequency of the processor in the application. For

1

tCK = CLKIN; Core clock ratio 16:1

2

DMx64 accesses

3

DMx64, PMx64 accesses

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 3 of 12

Power Vector Activity Scaling Factor (ASF)

I

0.21

DD-IDLE

I

DD-INLOW

I

DD-INMED

I

DD-INHIGH

I

DD-INPEAK

I

DD-INPEAK-TYP

50 :: 50
60 :: 40
70 :: 30

Table 2. Internal power vectors and dynamic scaling
factors

0.40

0.85

1.00

1.13

0.65

0.71

0.75

The dynamic current consumption for an ADSP­21368 processor in a specific application is
calculated according to the following formula,
where “%” is the percentage of the overall time
that the application spends in that state:

( % Peak activity level x I
( % High activity level x I
( % High activity level x I
( % Low activity level x I
+( % Idle activity level x I

DD-INPEAK
DD-INHIGH

DD-INMED
DD-INLOW

DD-IDLE

= Total Dynamic Current for V

Equation 1. Internal dynamic current (I

ASF x I

ASF x I
ASF x I
ASF x I

ASF x I

DDINT (IDD-DYN)

DD_BASELINE_DYN
DD_BASELINE_DYN
DD_BASELINE_DYN
DD_BASELINE_DYN

DD_BASELINE_DYN

DD-DYN

)
)
)
)

)

)

For example, after profiling the application code
for a particular system, activity is determined to
be proportioned as follows.

(10% x 1.13 x 0.76)
(30% x 1.00 x 0.76)
(50% x 0.85 x 0.76)
(10% x 0.40 x 0.76)

+ (0% x 0.21 x 0.76)

= 0.67A

I

DD-DYN

Figure 2. Internal dynamic current estimation

a

Therefore, the total estimated dynamic current on
the V

power supply in this example is

DDINT

0.67 A.

Estimating I

The ADSP-21368 I

Static Current, I

DDINT

DD-STATIC

DD-STATIC

current graphs for
the MQFP and LQFP 266 MHz and 333 MHz
processor speed grade models are shown in

Appendix B, and the Super BGA 333 MHz and

400 MHz processor speed grade models are
shown in Appendix C. The static current on the
V

power supply domain is a function of

DDINT

temperature and voltage but is not a function of
frequency or activity level. Therefore, unlike the
dynamic portion of the internal current, the static
current does not need to be calculated for each
discrete activity level or power vector. Using the
static current curve corresponding to the
application (i.e., at the specific V
baseline static current (I

DD-STATIC

estimated vs. junction temperature (T

DDINT

) can be

) of the for

J

estimating TJ).

), the

(10% Peak Activity Level)
(30% High Activity Level)
(50% Med. Activity Level)
(10% Low Activity Level)

(0% Idle Activity Level)

Figure 1. Internal system activity levels

Using the activity scaling factor (ASF) provided
for each activity level in Table 2 (and the core
operating at 1.2 V (V

) and 333 MHz), a

DDINT

value for the dynamic portion of the internal
current consumption of a single processor can be
estimated as follows.

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 4 of 12

For example, in an application with the core
operating at 1.2V (V
processor at a junction temperature (T

) and the ADSP-21368

DDINT

) of

J

+100oC, the corresponding baseline static current
(I

DD-STATIC

) for the V

power supply domain

DDINT

would be approximately 0.56 A.
The ADSP-21368 static power is constant for a

given voltage and temperature. Therefore, it is
simply added to the total estimated dynamic
current when calculating the total power
consumption due to the internal circuitry of the
ADSP-21368 processor. Note that the I

DD-STATIC

current shown in Figure 5 represents the worst-

a

case static current as measured across the wafer
fabrication process for the ADSP-21368 device.

Estimating Total I

DDINT

Current

The total current consumption due to the internal
core circuitry (I

) is the sum of the dynamic

DDINT

current component and the static current
component as shown in Equation 2.

I

= I

DDINT

Equation 2. Internal core current (I

DD-DYN

+ I

DD-STATIC

) calculation

DDINT

Continuing with the example (the processor
operating at 1.2 V and 333 MHz, and with the
code as profiled), assume that the resulting
junction temperature (TJ) is estimated to be
+100oC. The total internal current consumed by
the processor core under these conditions would
then be:

I

= 0.67 + 0.56 = 1.23A

DDINT

Equation 3. Total internal core current estimation

Total Estimated Internal Power, P

DDINT

The resulting internal power consumption
(P

Equation 5. Internal power (P

) is given by Equation 5.

DDINT

P

DDINT

= V

DDINT

DDINT

x I

DDINT

) calculation

Using Equation 5, the total estimated internal
power consumed by the processor in the
application described in this example would be:

P

Equation 6. Total internal power (P

= 1.2V x 1.24A = 1.49W

DDINT

) estimation

DDINT

Estimating External Power Consumption

The external power consumption (on the V
supply) is dependent on the switching of the
output pins. The magnitude of the external power
depends on:

DDEXT

Each ADSP-21368 processor includes an analog
phase-lock loop (PLL) and related internal
circuitry to provide clock signals to the core and
peripheral logic. This circuitry receives power
through the A

power supply pin of the

VDD

processor. Compared to the processor core, this
circuitry consumes little power. However, since
it is always active, it should be considered when
calculating the overall power consumed by the
internal circuitry of each ADSP-21368 processor.

The ADSP-21368 data sheet indicates that the
maximum A

per processor is 10 mA;

IDD

therefore, the total expected internal current
consumed by the processor core and the PLL
logic under the conditions described in the
example would be:

= 0.67 + 0.56 + 0.01= 1.24A

I

DDINT

Equation 4. Total internal current estimation

 The number of output pins that switch during

each cycle, O

 The maximum frequency at which the output

pins can switch, f

 The voltage swing of the output pins, V
 The load capacitance of the output pins, C

DDEXT

L

In addition to the input capacitance of each
device connected to an output, the total load
capacitance should include the capacitance
(C

) of the processor pin itself, which is

OUT

driving the load.
The SDRAM controller is capable of running up

to 166 MHz and can run at various frequencies,
depending on the programmed SDRAM clock
(SDCLK) to core clock (CCLK) ratio. The
maximum read/write throughput of the
asynchronous memory interface (AMI) is one
32-bit word per 3 SDCLK cycles (wait state of 2).
This corresponds to a maximum switching
frequency of 83.3 MHz for

ADDR23-0 and

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 5 of 12

a

DATA31-0 during SDRAM writes and a

maximum switching frequency of 27.8 MHz for

ADDR23-0 and DATA31-0 during writes to

external asynchronous memories.
In addition, the serial ports (SPORTs) and serial

peripheral interface (SPI) can operate up to one-

ADSP-21368

eighth (1/8) the processor core clock rate (CCLK).
With a core clock of 333 MHz, this corresponds
to a maximum switching frequency of 20.8 MHz
for SDATA and MOSI/MISO, and maximum
switching frequency of 41.7 MHz for

SPICLK.

SCLK and

Figure 3. ADSP-21368 system sample configuration

Equation 7 shows how to calculate the average

external current (I

) using the above

DDEXT

parameters:

= O x f x V

I

DDEXT

Equation 7. External current (I

DDEXT

DDEXT

x CL

) calculation

The estimated average external power
consumption (P

) can be calculated as

DDEXT

follows:

DDEXT

= V

P

Equation 8. External power (P

DDEXT

DDEXT

x I

DDEXT

) calculation

Using the sample configuration (Figure 3), we
can estimate the external current and thereby the
external power consumption with the following
assumptions:

 Processor core running at 333 MHz (CCLK)
 64K x 32 bit external SRAM, C

= 10 pF

L

(trace capacitance ignored)

 Writes to external memory occur with WS =2
 During external memory writes, 50% of the

ADDR23-0 and DATA31-0 pins are switching

 DAI configured as SPORT transmitting and

receiving 32-bit words at 1/8*
C

= 10 pF (trace capacitance ignored)

L

 DPI configured as SPI transmitting and

receiving 32-bit words at 1/8*
C

= 10 pF (trace capacitance ignored)

L

 Output capacitance of processor pin,

= 4.7 pF

C

OUT

CCLK,

CCLK,

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 6 of 12

a

The external current (I
calculated for each class of pins that can drive
and is shown in Table 3.

) (Equation 6) can be

DDEXT

Using this current, the estimated average external
power is calculated as:

P

= 3.3V x 0.077A = 0.254W

DDEXT

Summing the individual currents from Table 3,
the total external current (I

) for the sample

DDEXT

configuration shown in Figure 3 would be

Equation 9. External power (P
sample configuration shown in Figure 3

) calculation for

DDEXT

0.077 A.

Pin Type No. of Pins % Switching x f x V

ADDR[23:0] 24 50 27.8 MHz 3.3V 4.7pF + (2 x 10pF) 0.02719
DATA[31:0] 32 50 27.8 MHz 3.3V 4.7pF + (2 x 10pF) 0.03626
RD 1 0 n/a 3.3V 4.7pF + (2 x 10pF) 0.00000
WR 1 100 55.6 MHz 3.3V 4.7pF + (1 x 10pF) 0.00270
MS[1:0] 1 0 n/a 3.3V 4.7pF + (1 x 10pF) 0.00000
SDCLK[0] 1 100 166 MHz 3.3V 4.7pF + (0 x 10pF) 0.00257
DAI_P1 (SCLK) 1 100 41.7 MHz 3.3V 4.7pF + (1 x 10pF) 0.00202
DAI_P2 (FS) 1 100 1.3 MHz 3.3V 4.7pF + (1 x 10pF) 0.00006
DAI_P3 (SDATA) 1 0 n/a 3.3V 4.7pF + (1 x 10pF) 0.00000
DAI_P18 (SCLK) 1 100 41.7 MHz 3.3V 4.7pF + (1 x 10pF) 0.00202
DAI_P19 (FS) 1 100 1.3 MHz 3.3V 4.7pF + (1 x 10pF) 0.00006
DAI_P20 (SDATA) 1 100 20.8 MHz 3.3V 4.7pF + (1 x 10pF) 0.00101
DPI_P1 (SPICLK) 1 100 41.7 MHz 3.3V 4.7pF + (1 x 10pF) 0.00202
DPI_P2 (SPIDS) 1 0 n/a 3.3V 4.7pF + (1 x 10pF) 0.00000
DPI_P3 (MOSI) 1 100 20.8 MHz 3.3V 4.7pF + (1 x 10pF) 0.00101
DPI_P4 (MISO) 1 0 n/a 3.3V 4.7pF + (1 x 10pF) 0.00000

x C I

DDEXT

DDEXT

Table 3. External current (I

Total Power Consumption

) summary for Figure 3.

DDEXT

For example, if we assume that the processor in

Figure 3 is operating under the conditions

For a particular system, the total power
consumption becomes the sum of its individual
components, the power consumed by the internal
circuitry, and the power consumed due to the
switching of the I/O pins, as follows:

P

Equation 10. Total power (P

Where: P

DDINT

= P

TOTAL

DDINT + PDDEXT

) calculation

TOTAL

= Internal power consumption as

defined by Equation 5

P

= External power consumption as defined

DDEXT

detailed in the example (the processor operating
at 1.2 V, 333 MHz, and code as profiled in

Figure 1) and we also assume the resulting

junction temperature (T

) has been estimated to

J

be +100oC (see Appendix B for estimating TJ),
the total estimated power consumed would be:

P

Equation 11. Total power (P
sample configuration shown in Figure 2 while running
code described in Example 1

= 1.49W + 0.254W = 1.74W

TOTAL

TOTAL

) calculation for

by Equation 8

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 7 of 12

Appendix A

a

The ADSP-21368 I
derived using the I
a baseline I

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

(A)

0.65

0.60

DDINT

I

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00
0 50 100 150 200 250 300 350 400 450

dynamic current for a specified power supply setting.

DDINT

DD_BASELINE_DYN

DD-INHIGH

dynamic activity level vs. core frequency. Each curve in the graph represents

ADSP-21367/8/9 Dynamic I

current graph is shown in Figure 4. The I

, High Activity, I

DDINT

(I

DD_BASELINE_DYN

CCK (MHz)

)

DD-INHIGH

DD_BASELINE_DYN

current is

1.10V

1.15V

1.20V

1.25V

1.30V

1.35V

1.40V



Figure 4. I

DD_BASELINE_DYN

The ADSP-21368 processor is not specified for operation at 1.10 V or 1.40 V (V
curve is for reference only.

graph

DDINT

). This

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 8 of 12

Appendix B

a

The ADSP-21367 and ADSP-21369 I

DD-STATIC

current graph for MQFP and LQFP 266 MHz and 333 MHz
speed grade models is shown in Figure 5 (there is no ADSP-21368 version of the QFP package). The
static current on the V
function of frequency or activity level. Each curve in the graph represents a baseline I
for a specified power supply measured at various junction temperatures (T

power supply domain is a function of temperature and voltage and is not a

DDINT

static current

DDINT

). The I

J

DD-STATIC

current graph
(Figure 5) represents the worst-case static currents as measured across the wafer fabrication process for
the ADSP-21367 and ADSP-21369 processors.

ADSP-21367/9 Static Current*

)

1.10V

1.15V

1.20V

1.25V

1.30V

1.35V

1.40V

o

C)

I

DDINT

(A)

(I

1.500

1.450

1.400

1.350

1.300

1.250

1.200

1.150

1.100

1.050

1.000

0.950

0.900

0.850

0.800

0.750

0.700

0.650

0.600

0.550

0.500

0.450

0.400

0.350

0.300

0.250

0.200

0.150

0.100

0.050

0.000

-50 -30 -10 10 30 50 70 90 110 130 150

*Applies only to MQFP and LQFP 266MHz, 333MHz, 350 MHz and 366 MHz speed grade models

Top Center of Package, T (

DD-STATIC

Figure 5. I

DD-STATIC

graph

The ADSP-21367 and ADSP-21369 processors are not specified for operation at 1.10 V or



1.40 V (V

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 9 of 12

). This curve is for reference only.

DDINT

Appendix C

a

The ADSP-21368 I

DD-STATIC

shown in Figure 6. The static current on the V

current graph for Super BGA 333 MHz and 400 MHz speed grade models is

power supply domain is a function of temperature and

DDINT

voltage and is not a function of frequency or activity level. Each curve in the graph represents a baseline

static current for a specified power supply measured at various junction temperatures (TJ). The I

I

DDINT

STATIC

current graph (Figure 6) represents the worst-case static currents as measured across the wafer

DD-

fabrication process for the ADSP-21368 processor.

ADSP-21367/8/9 Static Current*

DD-STATIC

)

1.10V

1.15V

1.20V

1.25V

1.30V

1.35V

1.40V

2.400

2.300

2.200

2.100

2.000

1.900

1.800

1.700

1.600

1.500

1.400

1.300

(A)

1.200

1.100

DDINT

I

1.000

0.900

0.800

0.700

0.600

0.500

0.400

0.300

0.200

0.100

0.000

*Applies only to Super BGA 333MHz and 400MHz speed grade models

(I

-50 -30 -10 10 30 50 70 90 110 130 150

Top Center of Package, TT (ºC)

Figure 6 I

DD-STATIC

The ADSP-21368 processor is not specified for operation at 1.10 V or 1.40 V (V



Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 10 of 12

curve is for reference only.

graph

DDINT

). This

Appendix D

Correct functional operation of the ADSP-21368 processor is guaranteed when the junction temperature of
the device does not exceed the allowed junction temperature (T
ADSP-21368 processor, the total power budget is limited by the maximum allowed junction temperature

) as specified by the data sheet.

(T

J

The ABSOLUTE MAXIMUM RATINGS table in the ADSP-21368 data sheet states that



To determine the junction temperature of the device while on the application printed circuit board (PCB),
use the following equation found in the THERMAL CHARACTERISTICS section of the data sheet:

exposure to junction temperatures greater than +125OC for extended periods of time may
affect device reliability.

) as specified by the data sheet. For the

J

a

TJ = TT + (P

Equation 12 junction temperature (TJ ) calculation

Where:

TT = Package temperature (oC) measured at the top center of the package
P

ψ

Under natural convection,
convection conditions, the junction temperature (TJ) is typically just a little higher than the temperature at
the top-center of the package (TT). The die is physically separated from the surface of the package by only
a thin region of plastic mold compound. Unless the top of the package is forcibly cooled by significant
airflow, there will be very little difference between TT and T
airflow, and the values for
CHARACTERISTICS section of the ADSP-21368 data sheet for the 256-ball sBGA, 208-lead MQFP and
LQFP packages.

The THERMAL CHARACTERISTICS section of the data sheet also provides thermal resistance (
values for the 256-ball Super BGA, 208-lead MQFP and LQFP packages. Data sheet values for
provided for package comparison and PCB design considerations only and are not recommended for
verifying TJ on an actual application PCB.

= Total power consumption (Watts) as defined in Equation 10

TOTAL

= Junction-to-top (of package) characterization parameter (oC/W)

JT

ψ

for a thin plastic package is relatively low. This means that under natural

JT

ψ

under various airflow conditions are listed in the THERMAL

JT

TOTAL

x

ψ

JT)

However, note that

J.

ψ

is affected by

JT

θ

JA

θ

)

JA

are

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 11 of 12

a

References

[1] ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data Sheet, Rev. D, November 2008, Analog Devices, Inc.
[2] ADSP-21368 SHARC Processor Hardware Reference, Rev. 1.0, September 2006. Analog Devices, Inc.
[3] Estimating Power for the ADSP-21362 SHARC Processors (EE-277), Rev. 1, January 2006. Analog Devices Inc.

Document History

Revision Description

Rev 3 – June 22, 2009

by Jeyanthi J.

Rev 2 – February 11, 2008

by John C.

Rev 1 – December 11, 2006

by Chris C.

Updated Figure 5 title to include 350 MHz and 366 MHz speed grade models
information.

Added Super BGA 333-400 MHz Static IDD Graph.

Initial release.

Estimating Power Dissipation for ADSP-21368 SHARC® Processors (EE-299) Page 12 of 12