Datasheet EDS1232CATA-75L, EDS1232CATA-75, EDS1232CATA-1AL, EDS1232CATA-1A, EDS1232CABB-75L-E Datasheet (ELPID)

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PRELIMINARY DATA SHEET

128M bits SDRAM

EDS1232CABB, EDS1232CATA (4M words ×××× 32 bits)

Description

The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock.

They are packaged in 90-ball FBGA, 86-pin plastic TSOP (II).

Features

• 2.5V power supply

• Clock frequency: 133MHz (max.)

• Single pulsed /RAS

• ×32 organization

• 4 banks can operate simultaneously and

independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length (BL): 1, 2, 4, 8 and full page

• 2 variations of burst sequence

 Sequential (BL = 1, 2, 4, 8)  Interleave (BL = 1, 2, 4, 8)

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQM

• Refresh cycles: 4096 refresh cycles/64ms

• 2 variations of refresh

 Auto refresh  Self refresh

• FBGA package is lead free solder (Sn-Ag-Cu)

Document No. E0247E40 (Ver. 4.0) Date Published July 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002

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EDS1232CABB, EDS1232CATA

Ordering Information

Part number EDS1232CABB-75-E 2.5V 4M × 32 4 133 3 90-ball FBGA EDS1232CABB-1A-E 100 2, 3 EDS1232CABB-75L-E 133 3 EDS1232CABB-1AL-E 100 2, 3 EDS1232CATA-75 2.5V 4M × 32 4 133 3 86-pin plastic EDS1232CATA-1A 100 2, 3 TSOP (II) EDS1232CATA-75L 133 3 EDS1232CATA-1AL 100 2, 3

Supply voltage

Organization (words × bits) Internal Banks

Clock frequency MHz (max.)

/CAS latency Package

Part Number

E D S 12 32 C A BB - 75 L - E

Elpida Memory

Type

D: Monolithic Device

Product Code S: SDRAM

Density / Bank 12: 128M/4 Banks

Bit Organization 32: x32

Voltage, Interface C: 2.5V, LVTTL

Die Revision

Lead Free

Power Consumption Blank: Normal L: Low Power

Speed 75: 133MHz/CL3 100MHz/CL2 1A: 100MHz/CL2,3

Package TA: TSOP (II) BB: FBGA

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 3

Pin Configurations

/xxx indic ate active low signal.

EDS1232CABB, EDS1232CATA

90-ball FBGA

23456789

DQ26

DQ28

VSSQ

VDDQ

VSS

CLK

DQM1 NC NC /CAS /WE DQM0

VDDQ DQ8 VSS VDD DQ7 VSSQ

VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ

VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ

DQ11 VDDQ VSSQ VDDQ VSSQ DQ4

DQ13 DQ15 VSS VDD DQ0 DQ2

DQ24

VDDQ

DQ27

DQ29

DQ31

DQM3

CKE

VSS

VSSQ

DQ25

DQ30

VDD

VDDQ

DQ22

DQ17

A10

BA0

DQ23

VSSQ

DQ20

DQ18

DQ16

DQM2

BA1

/CS

VDD

DQ0

DQ21

DQ19

VDDQ

VSSQ

VDD

A11

/RAS

VDDQ

DQ1 DQ2

VSSQ

DQ3 DQ4

VDDQ

DQ5 DQ6

VSSQ

DQ7

VDD

DQM0

/WE /CAS /RAS

/CS

A11 BA0 BA1

A10(AP)

A0 A1 A2

DQM2

VDD

DQ16

VSSQ

DQ17 DQ18

VDDQ

DQ19 DQ20

VSSQ

DQ21 DQ22

VDDQ

DQ23

VDD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

86-pin TSOP

86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS

(Top view) (Top view)

Pin name Function A0 to A11 Address inputs

BA0, BA1 Bank select DQ0 to DQ31 Data input/output CLK Clock input CKE Clock enable /CS Chip select /RAS Row address strobe /CAS Column address strobe /WE Write enable DQM0 to DQM3 DQ mask enable VDD Supply voltage VSS Ground VDDQ Supply voltage for DQ VSSQ Ground for DQ NC No connection

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 4

CONTENTS

EDS1232CABB, EDS1232CATA

Description.................................................................................................................................................... 1

Features........................................................................................................................................................ 1

Ordering Information.....................................................................................................................................2

Part Number.................................................................................................................................................. 2

Pin Configurations......................................................................................................................................... 3

Electrical Specific atio ns ................................................................................................................................5

Block Diagram............................................................................................................................................. 10

Pin Function................................................................................................................................................ 11

Command Operation................................................................................................................................... 12

Truth Table.................................................................................................................................................. 16

Simplified State Diagram ............................................................................................................................ 22

Programming Mode Registers.................................................................................................................... 23

Mode Register.............................................................................................................................................24

Power-up sequence.................................................................................................................................... 27

Operation of the SDRAM ............................................................................................................................ 28

Timing Waveforms......................................................................................................................................44

Package Drawing........................................................................................................................................ 51

Recommended Soldering Conditions .........................................................................................................53

Revision History..........................................................................................................................................56

Preliminary Data Sheet E0247E40 (Ver. 4.0)

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EDS1232CABB, EDS1232CATA

Electrical Specifications

• All voltages are referenced to VSS (GND).

• After power up (refer to the Power up sequence).

Absolute Maximum Ratings

Parameter Symbol Rating Unit Note Voltage on any pin relative to VSS VT Supply voltage relative to VSS VDD, VDDQ Short circuit output current IOS 50 mA Power dissipation PD 1.0 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Recommended Operating Conditions (TA = 0 to +70°°°°C)

–0.5 to +3.6 –0.5 to +3.6

V V

Parameter Symbol min. typ. max. Unit Notes

Supply voltage VDD, VDDQ 2.3 2.5 2.7 V

Input high voltage VIH 1.7  VDD + 0.3*1 V Input low voltage VIL –0.3  0.7 V

VSS 0 0 0 V

Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width ≤ 5ns).

2. VIL (min.) = –1.5V (pulse width ≤ 5ns).

Preliminary Data Sheet E0247E40 (Ver. 4.0)

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EDS1232CABB, EDS1232CATA

DC Characteristics (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V±±±±0.2V, VSS, VSSQ = 0V)

Parameter /CAS latency Symbol Grade max. Unit Tes t c ondition Notes Operating current

(CL = 2) (CL = 3) IDD1 Standby current in power down IDD2P 1 mA

Standby current in power down (input signal stable)

Standby current in non power down

Standby current in non power down (input signal stable)

Active standby current in power down

Active standby current in power down (input signal stable)

Active standby current in non power down

Active standby current in non power down (input signal stable)

Burst operating current IDD4

Refresh current IDD5

Self refresh current IDD6 2.0 mA Self refresh current

(L-version)

IDD1

IDD2PS 1 mA

IDD2N 20 mA

IDD2NS 8 mA CKE ≥ VIH (min.) tCK = ∞

IDD3P 5 mA CKE ≤ VIL (max.) tCK = 15ns

IDD3PS 4 mA CKE ≤ VIL (max.), tCK = ∞

IDD3N 25 mA

IDD3NS 15 mA CKE ≥ VIH (min.), tCK = ∞,

IDD6 -xxL 0.6 mA

-75

-1A

-75

-1A

-75

-1A

-75

-1A

Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In

addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).

2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.).

3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).

105 100 105 100

150 130

210 200

mA 1

mA tRC ≥ tRC (min.) 3

Burst length = 1 tRC ≥ tRC (min.) IO = 0mA One bank active

CKE ≤ VIL (max.) tCK = 15ns CKE ≤ VIL (max.) tCK = ∞

CKE ≥ VIH (min.) tCK = 15ns CS ≥ VIH (min.) Input signals are changed one time during 30ns

CKE ≥ VIH (min.), tCK = 15 ns, /CS ≥ VIH (min.), Input signals are changed one time during 30ns.

tCK ≥ tCK (min.), IO = 0mA, All banks active

VIH ≥ VDD − 0.2V, VIL ≤ GND + 0.2V

DC Characteristics 2 (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V±±±±0.2V, VSS, VSSQ = 0V)

Parameter Symbol min. max. Unit Test condition Notes Input leakage current ILI –1.0 1.0 µA

Output leakage current ILO –1.5 1.5 µA 0 = VIN = VDDQ DOUT is disabled

Output high voltage Output low voltage

VOH 2.0 — V IOH = –1mA VOL — 0.4 V IOL = 1mA

0 = VIN = VDDQ, VDDQ = VDD, All other pins not under test = 0V

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 7

EDS1232CABB, EDS1232CATA

Pin Capacitance (TA = 25°C, f = 1MHz)

90-ball FBGA 86-pin TSOP (II) Parameter Symbol Pins min. Typ max. min. Typ max. Unit Input capacitance CI1 Address 1.5 — 3.0 2.5 — 4.0 pF

CI2 Data input/output

capacitance

CI/O DQ 3.0 — 5.5 4.0 — 6.5 pF

CLK, CKE, /CS, /RAS, /CAS, /WE, DQM

1.5 — 3.0 2.5 — 4.0 pF

AC Characteristics (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V±±±±0.2V, VSS, VSSQ = 0V)

-75 -1A

Parameter Symbol min. max. min. max. Unit Notes System clock cy cl e time

(CL = 2) (CL = 3) tCK 7.5 — 10 — ns

CLK high pulse width tCH 2.5 — 3 — ns CLK low pulse width tCL 2.5 — 3 — ns Access time from CLK tAC — 5.4 — 6 ns Data-out hold time tOH 2 — 2 — ns CLK to Data-out low impedance tLZ 0 — 0 — ns CLK to Data-out high impedance tHZ 2 5.4 2 6 ns Input setup time tSI 1.5 — 2 — ns Input hold time tHI 0.8 — 1 — ns CKE setup time (Power down exit) tCKSP 1.5 — 2 — ns

ACT to REF/ACT command period (operation)

(refresh) tRC 67.5  70  ns Active to Precharge command period tRAS 45 120000 50 120000 ns

Active command to column command (same bank)

Precharge to active command period tRP 20  20  ns Write recovery or data-in to precharge

lead time Last data into active latency tDAL

Active (a) to Active (b) command period tRRD 15  20 — ns Mode register set cycle time tRSC 2  2  CLK Transition time (rise and fall) tT 0.5 30 0.5 30 ns

Refresh period (4096 refresh cycles)

tCK 10 — 10 — ns

tRC 67.5  70  ns

tRCD 20  20  ns

tDPL 15  20  ns

2CLK + 20ns

tREF — 64 — 64 ms



2CLK + 20ns

—

Notes

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 8

Test Conditions

• AC high level input voltage / low level input voltage: 2.1V / 0.3V

• Input timing measurement reference level: 1.2V

• Transition time (Input rise and fall time): 1ns

• Output timing measurement reference level: 1.2V

• Termination voltage (Vtt): 1.2V

tCH tCL

2.1V

CLK

Input

Output

1.2V

0.3V tSETUP tHOLD

2.1V

1.2V

0.3V

tAC

tOH

EDS1232CABB, EDS1232CATA

tCK

Vtt

Z = 50 Ω

Output

Ω

30pF

Input Waveforms and Output Load

Preliminary Data Sheet E0247E40 (Ver. 4.0)

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EDS1232CABB, EDS1232CATA

Relationship Between Frequency and Minimum Latency

Parameter -75 -1A Frequency (MHz) 133 100 100 77 tCK (ns) Symbol 7.5 10 10 13 Notes

Active command to column command (same bank)

Active command to active command (same bank)

Active command to precharge command (same bank)

Precharge command to active command (same bank)

Write recovery or data-in to precharge command (same bank)

Active command to active command (different bank)

Self refresh exit time lSREX 1 1 1 1 2 Last data in to active command

(Auto precharge, same bank) Self refresh exit to command input lSEC 9 7 7 6 Precharge command to high impedance

(CL = 2) (CL = 3) lHZP 3 3 3 3 Last data out to active command

(auto precharge) (same bank) Last data out to precharge

(early precharge) (CL = 2)

(CL = 3) lEP –2 –2 –2 –2 Column command to column command lCCD 1 1 1 1 Write command to data in latency lWCD 0 0 0 0 DQM to data in lDID 0 0 0 0 DQM to data out lDOD 2 2 2 2 CKE to CLK disable lCLE 1 1 1 1 Register set to active command lMRD 2 2 2 2 /CS to command disable lCDD 0 0 0 0 Power down exit to command input lPEC 1 1 1 1

Notes: 1. IRCD to IRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

lRCD 3 2 2 2 1

lRC 9 7 7 6 1

lRAS 6 5 5 4 1

lRP 3 2 2 2 1

lDPL 2 2 2 2 1

lRRD 2 2 2 2 1

lDAL 5 4 4 4 = [lDPL + lRP]

= [lRC] 3

lHZP  2 2 2

lAPR 1 1 1 1

lEP  –1 –1 –1

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 10

Block Diagram

CLK CKE

Address

/CS /RAS /CAS /WE

Clock Generator

Mode Register

Control Logic

Command Decoder

Row Address Buffer & Refresh Counter

Column Address Buffer & Burst Counter

EDS1232CABB, EDS1232CATA

Bank 3

Bank 2

Bank 1

Bank 0

Row Decoder

Sense Amplifier Column Decoder &

Latch Circuit

Data Control Circuit

Latch Circuit

DQM

Input & Output

Buffer

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 11

EDS1232CABB, EDS1232CATA

Pin Function

CLK (input pin)

CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.

CKE (input pins)

CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends operation.

When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low.

/CS (input pins)

/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.

/RAS, /CAS, and /WE (input pins)

/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table.

A0 to A11 (input pins)

Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. Column Address is determined by A0 to 7 at the CLK rising edge in the read or write command cycle. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;

when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.

BA0 and BA1 (input pin)

BA0 and BA1 are bank select signal. (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0 BA1 Bank 0 L L

Bank 1 H L Bank 2 L H Bank 3 H H

Remark: H: VIH. L: VIL.

DQM (input pins) DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,

DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero.

DQ0 to DQ31 (input/output pins)

DQ pins have the same function as I/O pins on a conventional DRAM.

VDD, VSS, VDDQ, VSSQ (Power supply)

VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 12

EDS1232CABB, EDS1232CATA

Command Operation

Mode register set command (/CS, /RAS, /CAS, /WE)

The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through A11 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this command, the Synchronous DRAM cannot accept any other commands.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

Mode Register Set Command

Activate command (/CS, /RAS = Low, /CAS, /WE = High)

The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

Row Row

Row Address Strobe and Bank Activate Command

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 13

EDS1232CABB, EDS1232CATA

Precharge command (/CS, /RAS, /WE = Low, /CAS = High)

This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the Synchronous DRAM can’t accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM’s /RAS rising.

CLK CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

(Precharge select)

Write command (/CS, /CAS, /WE = Low, /RAS = High)

If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks.

A10 Add

Precharge Command

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

Col.

Column Address and Write Command

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 14

EDS1232CABB, EDS1232CATA

Read command (/CS, /CAS = Low, /RAS, /WE = High)

Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

Column Address and and Read Command

CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)

This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle

(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the Synchronous DRAM cannot accept any other command

Col.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

CBR (auto) Refresh Command

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 15

EDS1232CABB, EDS1232CATA

Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)

After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

Self Refresh Entry Command

Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)

This command can stop the current burst operation.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

Burst Stop Command in Full Page Mode

No operation (/CS = Low, /RAS, /CAS, /WE = High)

This command is not an execution command. No operations begin or terminate by this command.

CLK

CKE

/CS /RAS /CAS

/WE

BA0, BA1

(Bank select)

A10 Add

No Operation

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 16

EDS1232CABB, EDS1232CATA

Truth Table

Command Truth Table

CKE BA0, A9 - A0, Function Symbol n – 1 n /CS /RAS /CAS /WE BA1 A10 A11 Device deselect DESL H × H × × × × × ×

No operation NOP H × L H H H × × × Burst stop BST H × L H H L × × × Read READ H × L H L H V L V Read with auto precharge READA H × L H L H V H V Write WRIT H × L H L L V L V Write with auto precharge WRITA H × L H L L V H V Bank activate ACT H × L L H H V V V Precharge select bank PRE H × L L H L V L × Precharge all banks PALL H × L L H L × H × Mode register set MRS H × L L L L L L V

Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data

DQM Truth Table

CKE DQM Function Symbol n – 1 n Data write / output enable ENB H × L L L L

Data mask / output disable MASK H × H H H H DQ0 to DQ7 write enable/output enable ENB0 H × L × × × DQ8 to DQ15 write enable/output enable ENB1 H × × L × × DQ16 to DQ23 write enable/output enable ENB2 H × × × L × DQ24 to DQ31 write enable/output enable ENB3 H × × × × L DQ0 to DQ7 write inhibit/output disable MASK0 H × H × × × DQ8 to DQ15 write inhibit/output disable MASK 1 H × × H × × DQ16 to DQ23 write inhibit/output disable MASK 2 H × × × H × DQ24 to DQ31 write inhibit/output disable MASK 3 H × × × × H

0 1 2 3

Remark: H: VIH. L: VIL. ×: VIH or VIL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 17

EDS1232CABB, EDS1232CATA

CKE Truth Table

CKE Current state Function Symbol n – 1 n /CS /RAS /CAS /WE Address Activating Clock suspend mode entry H L × × × × ×

Any Clock suspend mode L L × × × × × Clock suspend Cloc k suspend mode exit L H × × × × × Idle CBR (auto) refresh command REF H H L L L H × Idle Self refresh entry SELF H L L L L H Self refresh Self refresh exit L H L H H H × L H H × × × × Idle Power down entry H L L H H H × H L H × × × × Power down Power down exit L H H × × × × L H L H H H ×

Remark: H: VIH. L: VIL. ×: VIH or VIL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 18

EDS1232CABB, EDS1232CATA

Function Truth Table*1

Current state /CS /RAS /CAS /WE Address Command Operation Notes Idle H × × × × DESL Nop or power down 2

L H H × × NOP or BST Nop or power down 2 L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT Row activating L L H L BA, A10 PRE/PALL Nop L L L H × REF/SELF CBR (auto) refresh or self refresh 4 L L L L OPCODE MRS Mode register accessing Row active H × × × × DESL Nop L H H × × NOP or BST Nop L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL Read H × × × × DESL Continue burst to end → Row active L H H H × NOP Continue burst to end → Row active L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, new read: Determine AP 7 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, begin write: Determine AP 7, 8 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Terminate burst, Precharging L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL Write H × × × × DESL Continue burst to end → Write recovering L H H H × NOP Continue burst to end → Write recovering L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 7, 8 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write : Determine AP 7 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Terminate burst, Precharging 9 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL

READ/READA WRIT/ WRITA

ILLEGAL 3 ILLEGAL 3

Begin read: Determine AP 5 Begin write: Determine AP 5

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 19

EDS1232CABB, EDS1232CATA

Current state /CS /RAS /CAS /WE Address Command Operation Notes Read with auto precharge L H H H × NOP Continue burst to end → Precharging L H H L × BST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL

Write with auto precharge

H × × × × DESL Continue burst to end → Precharging

READ/READA WRIT/ WRITA

H × × × × DESL

ILLEGAL 3 ILLEGAL 3

Continue burst to end → Write recovering with auto precharge

L H H H × NOP

L H H L × BST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL Precharging H × × × × DESL Nop → Enter idle after tRP L H H H × NOP Nop → Enter idle after tRP L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Nop → Enter idle after tRP L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL

Row activating L H H H × NOP Nop → Enter bank active after tRCD

L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3, 10 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL

H × × × × DESL Nop → Enter bank active after tRCD

READ/READA WRIT/ WRITA

Continue burst to end → Write recovering with auto precharge

ILLEGAL 3 ILLEGAL 3

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 20

EDS1232CABB, EDS1232CATA

Current state /CS /RAS /CAS /WE Address Command Operation Notes Write recovering L H H H × NOP Nop → Enter row active after tDPL L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL

Write recovering with auto L H H H × NOP Nop → Enter precharge aft er tDP L

precharge L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3, 8 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL

Refresh L H H H × NOP/BST Nop → Enter idle after tRC

L H H L × READ/READA ILLEGAL L H L H × ACT/PRE/PALL ILLEGAL L H L L × REF/SELF/MRS ILLEGAL

Mode register accessing L H H H × NOP Nop → Enter idle after tRSC

L H H L × BST ILLEGAL L H L H × READ/READA ILLEGAL

L L L L ×

Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data

Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),

4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.

5. Illegal if tRCD is not satisfied.

6. Illegal if tRAS is not satisfied.

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.

9. Must mask preceding data which don’t satisfy tDPL.

10. Illegal if tRRD is not satisfied.

H × × × × DESL Nop → Enter row active after tDPL

READ/READA WRIT/ WRITA

H × × × × DESL Nop → Enter precharge after tDPL

H × × × × DESL Nop → Enter idle after tRC

H × × × × DESL Nop → Enter idle after tRSC

ACT/PRE/PLL/ REF/SELF/MRS

Start read, Determine AP 8 New write, Determine AP

ILLEGAL

BA: Bank Address, CA: Column Address, RA: Row Address

mode.

depending on the state of that bank.

All input buffers except CKE will be disabled.

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 21

EDS1232CABB, EDS1232CATA

Command Truth Table for CKE

CKE Current State n – 1 n /CS /RAS /CAS /WE Address Operation Notes Self refresh H × × × × × × INVALID, CLK (n – 1) would exit self refresh

L H H × × × × Self refresh recovery L H L H H × × Self refres h recovery L H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × Continue self refresh Self refresh recovery H H H × × × × Idle after tRC H H L H H × × Idle after tRC H H L H L × × ILLEGAL H H L L × × × ILLEGAL H L H × × × × ILLEGAL H L L H H × × ILLEGAL H L L H L × × ILLEGAL H L L L × × × ILLEGAL Power down H × × × × × INVALID, CLK (n – 1) would exit power down L H H × × × × EXIT power down L H L H H H × EXIT power down L L × × × × × Continue power down mode All banks idle H H H × × × Refer to operations in Function Truth Table H H L H × × Refer to operations in Function Truth Table H H L L H × Refer to operations in Function Truth Table H H L L L H × CBR (auto) Refresh H H L L L L OPCODE Refer to operations in Function Truth Table H L H × × × Begin power down next cycle H L L H × × Refer to operations in Function Truth Table H L L L H × Refer to operations in Function Truth Table H L L L L H × Self refresh 1 H L L L L L OPCODE Refer to operations in Function Truth Table L H × × × × × Exit power down next cycle L L × × × × × Power down 1 Row active H × × × × × × Refer to operations in Function Truth Table L × × × × × × Clock suspend 1 Any state other than H H × × × × Refer to operations in Function Truth Table listed above H L × × × × × Begin cl ock suspend next cycle 2 L H × × × × × Exit clock suspend next cycle L L × × × × × Maintain clock suspend

Remark: H = VIH, L = VIL, × = VIH or VIL Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all

banks idle or row active state.

2. Must be legal command as defined in Function Truth Table.

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 22

Simplified State Diagram

EDS1232CABB, EDS1232CATA

Self

Refresh

SELF

WRITE

SUSPEND

WRITEA

SUSPEND

CKE

Mode

Write

CKE

Set

WRITE

WRITEA

MRS

BST

rite

Write with

Auto precharge

PRE (Precharge termination)

ACTIVE

Read

IDLE

ROW

ACT

Auto precharge

Read with

PRE

Write

SELF exit

CKE

Read

CKE

REF

CKE

BST

READ

READA

CBR(auto)

Power

Down

Active Power

Down

Read

Refresh

CKE

READ

SUSPEND

READA

SUSPEND

PRE (Precharge termination)

POWER

Precharge

Automatic sequence

Manual input

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 23

EDS1232CABB, EDS1232CATA

Programming Mode Registers

The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0 and BA1 as data inputs. The registers retain data until it is re-programmed, or the device loses power.

The mode register has three fields;

Options : A11 through A7, BA0, BA1 /CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0

Following mode register programm ing, no comma nd can be iss ued before at least 2 CLK have elapsed.

/CAS Latency

/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. ”Relationship between Frequency and Latency” shows the relationship of /CAS latency to the clock period and the speed grade of the device.

Burst Length

Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.

Wrap Type (Burst Sequence)

The wrap type specifies the order in which the burst data will be addressed. “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.

Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. “Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.

This order is programmable as either

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 24

Mode Register

EDS1232CABB, EDS1232CATA

A0A1A2A3A4A5A7 A6A8A9A10A11BA1BA0

10000 JEDEC Standard Test Set (refresh counter test)

A0A1A2A3A4A5A7 A6A8A9A10A11BA1BA0

BLWTLTMODE001xx Burst Read and Single Write

01 Use in future

BLWTLTMODE00000 Mode Register Set

(for Write Through Cache)

A0A1A2A3A4A5A7 A6A8A9A10A11BA1BA0

VVVVVV1V1xxx Vender Specific

A0A1A2A3A4A5A7 A6A8A9A10A11BA1BA0

V = Valid x = Don’t care

CLK

CKE

Burst length

Wrap type

Latency

Remark R : Reserved

Mode Register Set Timing

mode

Bits2-0

000 001 010 011 100 101 110 111

0 1

Full page

Sequential Interleave

Bits6-4

000 001 010 011 100 101 110 111

WT = 0

1 2 4 8 R R R

/CAS latency

WT = 1

1 2 4 8 R R R R

R R 2 3 R R R R

/CS

/RAS

/CAS

/WE

A0 - A11,

BA0(13), BA1(A12)

Mode Register Set

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 25

EDS1232CABB, EDS1232CATA

Burst Length and Sequence [Burst of Two]

Starting address (column address A0, binary)

0 0, 1 0, 1 1 1, 0 1, 0

[Burst of Four]

Starting address (column address A1 to A0, binary)

00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0

[Burst of Eight]

Starting address (column address A2 to A0, binary)

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

Full page burst is an extension of the above tables of sequential addressing, with the length being 256.

Sequential addressing sequence (decimal)

Interleave addressing sequence (decimal)

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 26

Address Bits of Bank-Select and Precharge

EDS1232CABB, EDS1232CATA

(Activate command)

(Precharge command)

(/CAS strobes)

A11A10A9A8A7A6A4 A5A3A2A1A0Row

A11A10A9A8A7A6A4 A5A3A2A1A0

xA10A9A8A7A6A4 A5A3A2A1A0Col.

BA1 BA0

BA1(A12) BA0(A13)

A10

x : Don’t care

disables Auto-Precharge

(End of Burst) enables Auto-Precharge

(End of Burst)

BA1(A12) BA0(A13)

Result

Select Bank A “Activate” command

Select Bank B “Activate” command

Select Bank C “Activate” command

Select Bank D “Activate” command

Result

Precharge Bank A

Precharge Bank B

Precharge Bank C

Precharge Bank D

Precharge All Banks

Result

enables Read/Write commands for Bank A

enables Read/Write commands for Bank B

enables Read/Write commands for Bank C

enables Read/Write commands for Bank D

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 27

EDS1232CABB, EDS1232CATA

Power-up sequence

The SDRAM should be goes on the following sequence with power up.

The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.

The CKE and DQM is driven to high between power stabilizes and the initialization sequence. This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up,

the large current flows from these pins to VDD through the diodes.

Initialization sequence

When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device.

VDD, VDDQ

CKE, DQM

CLK

/CS, DQ

Power up sequence

100 µs

0 V Low

Low

Power stabilize

Power-up sequence and Initialization sequence

Initialization sequence

200 µs

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 28

EDS1232CABB, EDS1232CATA

Operation of the SDRAM

Read/Write Operations

Bank active

Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input.

Read operation

A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.

The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.

When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output.

The /CAS latency and burst length must be specified at the mode register.

CLK

tRCD

Command

ACT

READ

Address

CLK

Command

Address

BL = 1

BL = 2

BL = 4

BL = 8

CL = 2

CL = 3

ACT

Row

tRCD

READ

Column

out 0

out 0 out 1

out 0 out 1 out 2

/CAS Latency

out 3

out 4

out 5

out 3

Burst Length

out 3

out 6 out 7

out 3

CL = /CAS latency Burst Length = 4

BL : Burst Length /CAS Latency = 2

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 29

EDS1232CABB, EDS1232CATA

Write operation

Burst write or single write mode is selected by the OPCODE of the mode register.

1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations. The write start address is specified by the column address and the bank select address at the write command set cycle.

CLK

tRCD

Command

ACT

WRIT

Address

Row

BL = 1

BL = 2

BL = 4

BL = 8

Column

in 0

in 1

in 2

in 3

in 4

in 5

in 6 in 7

CL = 2, 3

Burst write

2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address and the bank select address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).

CLK

tRCD

Command

Address

ACT

Row

WRIT

Column

in 0

Single write

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 30

EDS1232CABB, EDS1232CATA

Auto Precharge

Read with auto-precharge

In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is required before execution of the next command.

[Clock cycle time]

/CAS latency Precharge start cycle 3 2 cycle before the final data is output

2 1 cycle before the final data is output

CLK

CL=2 Command

CL=3 Command

ACT READA ACT

lRAS

out3out2out1out0

lAPR

out3out2out1out0

Note: Internal auto-precharge starts at the timing indicated by " ".

And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".

lAPR

Burst Read (BL = 4)

Write with auto-precharge

In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is required between the final valid data input and input of next command.

CLK

Command

ACT

WRITA

RAS

in0 in1 in2 in3

ACT

lDAL

Note: Internal auto-precharge starts at the timing indicated by " ".

and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".

Burst Write (BL = 4)

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 31

CLK

EDS1232CABB, EDS1232CATA

Command

Note: Internal auto-precharge starts at the timing indicated by " ".

ACT

IRAS

and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".

WRITA

Single Write

ACT

lDAL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 32

EDS1232CABB, EDS1232CATA

Burst Stop Command

During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command.

CLK

Command

(CL = 2)

(CL = 3)

READ BST

out outout

High-Z

out outout

High-Z

Burst Stop at Read

During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command.

CLK

Command

WRITE

in in in

BST

High-Z

Burst Stop at Write

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 33

EDS1232CABB, EDS1232CATA

Command Intervals

Read command to Read command interval

1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.

CLK

Command

ACT

READ READ

Address

Row

Column A

Column B

Bank0 Active

Column =A

Read

Column =B

Read

out A0

Column =A

Dout

out B0 Column =B

Dout

out B1

out B2

CL = 3 BL = 4 Bank 0

out B3

READ to READ Command Interval (same ROW address in same bank)

2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.

CLK

Command

Address

ACT

Row 0

ACT

Row 1

READ

Column A

READ

Column B

out B3

Bank0

Active

Bank3 Active

Bank0

Read

Bank3

Read

out A0

Bank0

Dout

out B0

Bank3

Dout

out B1

out B2

CL = 3 BL = 4

READ to READ Command Interval (different bank)

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 34

EDS1232CABB, EDS1232CATA

Write command to Write command interval

1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority.

CLK

Command

Address

ACT

Row

WRIT

Column A

WRIT

Column B

Bank0 Active

in A0

Column =A

Write

in B0

Column =B

Write

in B1

in B2

Burst Write Mode

BL = 4

Bank 0

in B3

WRITE to WRITE Command Interval (same ROW address in same bank)

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.

CLK

Command

Address

ACT

Row 0

ACT

Row 1

WRIT

Column A

WRIT

Column B

Bank0 Active

in B1

in B2

Bank3 Active

in A0

Bank0

Write

in B0

Bank3

Write

in B3

WRITE to WRITE Command Interval (different bank)

Burst Write Mode

BL = 4

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 35

EDS1232CABB, EDS1232CATA

Read command to Write command interval

1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.

CLK

Command

READ

WRIT

CL=2

DQM

CL=3

DQ (input)

DQ (output)

in B0

High-Z

in B1

in B2

in B3

BL = 4 Burst write

READ to WRITE Command Interval (1)

CLK

Command

READ

WRIT

DQM

2 clock

CL=2

out out out

CL=3

out outinininininininin

READ to WRITE Command Interval (2)

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command.

3. Di ff ere nt ba nk: When t he bank ch ang es, th e writ e co mman d c an be pe rfo rm ed aft er an inte rva l of no les s th an 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input.

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 36

EDS1232CABB, EDS1232CATA

Write command to Read command interval:

1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed.

CLK

Command

DQM

DQ (input)

DQ (output)

CLK

Command

DQM

DQ (input)

WRIT READ

in A0

Column = A Write

Column = B Read

WRITE to READ Command Interval (1)

WRIT

in A0

Column = A Write

in A1

WRITE to READ Command Interval (2)

READ

Column = B Read

out B0

/CAS Latency

Column = B Dout

out B0DQ (output)

/CAS Latency

Column = B Dout

out B1 out B2 out B3

Burst Write Mode

CL = 2 BL = 4

Bank 0

Burst Write Mode

CL = 2 BL = 4

Bank 0

2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command.

3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 37

EDS1232CABB, EDS1232CATA

Read with auto precharge to Read command interval

1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.

CLK

Command

READA READ

bank0 Read A

Note: Internal auto-precharge starts at the timing indicated by " ".

bank3 Read

out A0 out A1 out B0 out B1

CL= 3

BL = 4

Read with Auto Precharge to Read Command Interval (Different bank)

2. Same bank: The consecutive read command (the same bank) is illegal.

Write with auto precharge to Write command interval

1. Different bank: When s om e ba n ks are in t h e ac ti ve s ta t e, t he seco n d wri t e comm a nd (a n oth e r bank ) is e xec u t ed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts 2 clocks later from the second command.

CLK

Command

Note: Internal auto-precharge starts at the timing indicated by " ".

WRITA WRIT

bank0 Write A

bank3 Write

in B1 in B2 in B3in A0 in A1 in B0

BL= 4

Write with Auto Precharge to Write Command Interval (Different bank)

2. Same bank: The consecutive write command (the same bank) is illegal.

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 38

EDS1232CABB, EDS1232CATA

Read with auto precharge to Write command interval

1. Different bank: When s om e ba n ks are in t h e ac ti ve s ta t e, t he seco n d wri t e comm a nd (a n oth e r bank ) is e xec u t ed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.

CLK

Command

READA WRIT

DQM

2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.

Write with auto precharge to Read command interval

1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.

Command

CL = 2 CL = 3

DQ (input)

DQ (output)

bank0 ReadA

Note: Internal auto-precharge starts at the timing indicated by " ".

Read with Auto Precharge to Write Command Interval (Different bank)

CLK

WRITA READ

in B0 in B1 in B2 in B3

High-Z

bank3 Write

BL = 4

DQM

DQ (input)

DQ (output)

2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.

Preliminary Data Sheet E0247E40 (Ver. 4.0)

in A0

out B0 out B1 out B2 out B3

bank0 WriteA

Note: Internal auto-precharge starts at the timing indicated by " ".

Write with Auto Precharge to Read Command Interval (Different bank)

bank3 Read

CL = 3 BL = 4

Page 39

EDS1232CABB, EDS1232CATA

Read command to Precharge command interval (same bank)

When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution.

CLK

Command

READ

out A0 out A1 out A2 out A3

CL=2

PRE/PALL

lEP = -1 cycle

READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)

CLK

Command

READ

CL=3 lEP = -2 cycle

PRE/PALL

out A0 out A1 out A2 out A3

READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)

CLK

Command

READ

PRE/PALL

out A0

High-Z

lHZP = 2

READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)

CLK

Command

READ

PRE/PALL

lHZP =3

out A0

High-Z

READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 40

EDS1232CABB, EDS1232CATA

Write command to Precharge command interval (same bank)

When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL.

CLK

PRE/PALL

Command

DQM

WRIT

tDPL

CLK

Command

DQM

WRIT

in A0 in A1

PRE/PALL

tDPL

WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))

CLK

Command

DQM

WRIT

in A0 in A1 in A2

in A3

PRE/PALL

tDPL

WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 41

EDS1232CABB, EDS1232CATA

Bank active command interval

1. Same bank: The interval between the two bank active commands must be no less than tRC.

2. In the case of different bank active commands: The interval between the two bank active commands must be no less than tRRD.

CLK

Command

Address

ACT

ROW

Bank 0 Active

tRC

ACT

ROW

Bank 0 Active

Bank Active to Bank Active for Same Bank

CLK

Command

Address

ACT

ROW:0

tRRD

Bank 0 Active

ACT

ROW:1

Bank 3 Active

Bank Active to Bank Active for Different Bank

Mode register set to Bank active command interval

The interval between setting the mode register and executing a bank active command must be no less than lMRD.

CLK

Command

Address

MRS

OPCODE

IMRD

Mode

ACT

BS & ROW

Bank Active

Mode register set to Bank active command interval

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 42

EDS1232CABB, EDS1232CATA

DQM Control

The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM/LDQM is different during reading and writing.

Reading

When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.

Writing

Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0 clock.

CLK

DQM

out 0 out 1

lDOD = 2 Latency

Reading

High-Z

out 3

CLK

DQM

in 0 in 1

lDID = 0 Latency

Writing

in 3

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 43

EDS1232CABB, EDS1232CATA

Refresh

Auto-refresh

All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required.

Self-refresh

After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below.

1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed.

2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode.

Note: tREF (max.) / refresh cycles.

Others

Power-down mode

The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed.

Clock suspend mode

By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 44

Timing Waveforms

Read Cycle

CLK

CKE

/CS

/RAS

/CAS

/WE

A10

Address

DQM

VIH

tCK

tCH t

tHItSI

tRCD

EDS1232CABB, EDS1232CATA

tRC

tRAS

tHI

tHItSI

tSI

tHItSI

DQ (input)

DQ (output)

Bank 0 Active

Bank 0 Read

Bank 0 Precharge

/CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 45

Write Cycle

/RAS

/CAS

Address

DQM

DQ (input)

DQ (output)

CLK

CKE

/CS

/WE

A10

VIH

tCK

tCH t

tRCD

tHItSI tHItSI

tHItSI

tHI

tSI

tHI tHItSItSI tSItSI

tRC

tRAS

tHI

tHI tHI

EDS1232CABB, EDS1232CATA

tRP

tHItSI tHItSI

tHItSI

tDPL

tHItSI

Bank 0 Active

Mode Register Set Cycle

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK

/CS

VIL

valid

Precharge If needed

CKE

/RAS /CAS

/WE

Address

DQM

DQ (output)

DQ (input)

code

Mode register Set

Bank 0 Write

lMRD

R: b

Bank 3 Active

Bank 0 Precharge

C: b

High-Z

lRCDlRP

Bank 3 Read

Output mask

C: b’

b b+3 b’ b’+1 b’+2 b’+3

CL = 2 BL = 4 Bank 0 access = VIH or VIL

RCD

= 3 /CAS latency = 3 Burst length = 4 = VIH or VIL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 46

Read Cycle/Write Cycle

EDS1232CABB, EDS1232CATA

CLK CKE

/CS /RAS /CAS

/WE

Address

DQM

DQ (output)

DQ (input)

CKE

/CS /RAS

/CAS

/WE

Address

DQM

DQ (output)

DQ (input)

0 1 2 3 4 5 6 7 8 9 1011121314151617181920

VIH

R:a C:a R:b C:b C:b' C:b"

Bank 0 Active

Bank 0 Read

a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3

Bank 3 Active

Bank 3 Read

Bank 0 Precharge

High-Z

Bank 3 Read

Bank 3 Precharge

VIH

R:a C:a R:b C:b C:b' C:b"

High-Z

a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1b"+2 b"+3

Bank 0 Active

Bank 0 Write

Bank 3 Active

Bank 3 Write

Bank 0 Precharge

Bank 3 Write

Bank 3 Precharge

Read cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4

VIH or VIL

Write cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 47

Read/Single Write Cycle

EDS1232CABB, EDS1232CATA

CLK

CKE

/CS

/RAS /CAS

/WE

Address

DQM

DQ (input)

DQ (output)

CKE

/CS

/RAS /CAS

/WE

Address

DQM

DQ (input)

DQ (output)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

R:a C:a R:b C:a'

C:a

Bank 0 Active

R:a C:a C:a

Bank 0 Active

Bank 0 Read

Bank 3 Active

R:b

Bank 3 Active

a+1 a+2 a+3

a+1 a+3

Bank 0 Write

Bank 0 Read

C:b

Bank 0 Write

a a+1 a+2 a+3

C:c

Bank 0 Write

Bank 0 Precharge

Read/Single write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 =

VIH or VIL

Bank 3 Precharge

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 48

Read/Burst Write Cycle

EDS1232CABB, EDS1232CATA

CLK CKE

/CS /RAS /CAS

/WE

Address

DQM

DQ (input)

DQ (output)

CKE

VIH

/CS /RAS

/CAS

/WE

Address

DQM

DQ (input)

DQ (output)

Auto Refresh Cycle

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

R:a C:a R:b C:a'

a a+1 a+2 a+3

a+1 a+2 a+3

Bank 0 Active

R:a C:a C:a

Bank 0 Read

Bank 3 Active

R:b

Clock

suspend

Bank 0 Write

Bank 0 Precharge

Bank 3 Precharge

a a+1 a+2 a+3

a+1

a a+3

Bank 0 Active

Bank 0 Read

Bank 3 Active

Bank 0 Write

Bank 0 Precharge

Read/Burst write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 =

VIH or VIL

CLK

CKE

/CS

/RAS

/CAS

/WE

Address

DQM

DQ (input)

DQ (output)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

VIH

A10=1

Precharge If needed

Auto Refresh

High-Z

Auto Refresh

R:a

Active Bank 0

C:a

Refresh cycle and

Read

Read cycle

Bank 0

/RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4

= VIH or VIL

a a+1

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 49

Self Refresh Cycle

EDS1232CABB, EDS1232CATA

CLK

CKE

/CS /RAS

/CAS

/WE

Address

A10=1

DQM

DQ (input)

DQ (output)

Precharge command If needed

Clock Suspend Mode

CLK

CKE

/CS /RAS

/CAS

/WE

Address

DQM

DQ (output)

DQ (input)

CKE

/CS /RAS

/CAS

/WE

Address

DQM

DQ (output)

DQ (input)

01234 5 6 7 8 9 1011121314151617181920

R:a C:a R:b

Bank0 Active

R:a C:a

Bank0 Active

Active clock suspend start

CKE Low

Self refresh entry command

tSI tSI

a a+1 a+2 a+3 b b+1 b+2

Bank0

Active clock suspend end

Read

Bank3 Active

R:b

a a+1

a+2

Bank0 Write

Bank3 Active

Active clock supend end

Self refresh exit ignore command or No operation

tHI

Read suspend

High-Z

Write suspend

start

lSREX

start

High-Z

Read suspend

a+3

Write suspend

Self refresh entry

clock

command

enable

C:b

Bank3

end

Read

C:b

b b+1 b+2 b+3

Bank0

Bank3

Precharge

end

Write

Bank0 Precharge

Next clock enable

b+3

Earliest Bank3 Precharge

Self refresh cycle

Auto refresh

/RAS-/CAS delay = 3 CL = 3 BL = 4 =

Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL

Write cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL

VIH or VIL

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 50

Power Down Mode

CLK

CKE

/CS /RAS

/CAS

/WE

EDS1232CABB, EDS1232CATA

CKE Low

Address

DQM

DQ (input)

DQ (output)

Initialization Sequence

CLK

CKE

/CS

/RAS

/CAS

/WE

Address

DQM

VIH

All banks Precharge

A10=1

RPt

Precharge command If needed

0123456

valid

tRP

Auto Refresh

Power down entry

High-Z

Power down mode exit

78910

Auto Refresh

R: a

Active Bank 0

48 49 50 51

High-Z

Power down cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL

code

MRD

Mode register Set

Valid

Bank active If needed

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 51

Package Drawing

90-ball FBGA

Solder ball: Lead free (Sn-Ag-Cu)

0.2

8.0 ± 0.1

EDS1232CABB, EDS1232CATA

Unit: mm

0.2

13.0 ± 0.1

INDEX AREA

0.1

0.2

1.07 max.

0.27 ± 0.05

0.8

0.9

ECA-TS2-0061-01

INDEX MARK

0.8

1.6

90-φ0.45 ± 0.05

Preliminary Data Sheet E0247E40 (Ver. 4.0)

φ0.08

MSAB

Page 52

86-pin TSOP (II)

86 44

PIN#1 ID

EDS1232CABB, EDS1232CATA

22.22 ± 0.10

143

10.16

11.76 ± 0.20

0.50

Unit: mm

0.15 to 0.30

0.81 max.

0.10

0.80 Nom

0.25

0 to 8°

1.0 ± 0.05

0.10

1.2 max.

+0.08

−0.05

0.10

0.60 ± 0.15

0.09 to 0.20

Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side.

ECA-TS2-0030-01

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 53

EDS1232CABB, EDS1232CATA

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the EDS1232CA.

Type of Surface Mount Device

EDS1232CABB: 90-ball FBGA < Lead free (Sn-Ag-Cu) > EDS1232CATA: 86-pin TSOP (II)

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 54

EDS1232CABB, EDS1232CATA

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.

CME0107

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Page 55

EDS1232CABB, EDS1232CATA

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0247E40 (Ver. 4.0)

Datasheet EDS1232CATA-75L, EDS1232CATA-75, EDS1232CATA-1AL, EDS1232CATA-1A, EDS1232CABB-75L-E Datasheet (ELPID)

Specifications and Main Features

Frequently Asked Questions

User Manual

Description

Features

Ordering Information

Part Number

Pin Configurations

Electrical Specifications

Absolute Maximum Ratings

Test Conditions

Relationship Between Frequency and Minimum Latency

Block Diagram

Pin Function

Command Operation

Truth Table

Command Truth Table

DQM Truth Table

CKE Truth Table

Command Truth Table for CKE

Simplified State Diagram

Programming Mode Registers

Mode Register

Address Bits of Bank-Select and Precharge

Power-up sequence

Operation of the SDRAM

Read/Write Operations

Auto Precharge

Command Intervals

DQM Control

Refresh

Others

Timing Waveforms

Read Cycle

Write Cycle

Mode Register Set Cycle

Read Cycle/Write Cycle

Read/Single Write Cycle

Read/Burst Write Cycle

Auto Refresh Cycle

Self Refresh Cycle

Clock Suspend Mode

Power Down Mode

Initialization Sequence

Package Drawing

90-ball FBGA

86-pin TSOP (II)

Recommended Soldering Conditions