Datasheet EBS25UC8APMA-75L, EBS25UC8APMA-75, EBS25UC8APMA-80L, EBS25UC8APMA-80, EBS25UC8APMA-7AL Datasheet (ELPID)

DATA SHEET

256MB SDRAM Micro DIMM

EBS25UC8APMA (32M words ×××× 64 bits, 1 bank)

Description

The EBS25UC8APMA is 32M words × 64 bits, 1 bank

Synchronous Dynamic RAM Micro Dual In-line Memory
Module (Micro DIMM), mounted 8 pieces of 256M bits

SDRAM sealed in µBGA

provides high density and large quantities of memory in
a small space without utilizing the surface mounting
technology. Decoupling capacitors are mounted on
power supply line for noise reduction.

Note : Do not push the cover or drop the modules in

order to protect from mechanical defects, which
would be electrical defects.



package. This module

Features

• Fully compatible with 8 bytes Micro DIMM: JEDEC

standard outline

• 144-pin socket type micro dual in line memory

module (Micro DIMM)

 PCB height: 30.00mm (1.18inch )
 Lead pitch: 0.50mm

• 3.3V power supply

• Clock frequency: 100MHz/133MHz (max.)

• LVTTL interface

• Data bus width: × 64 non-ECC

• Single pulsed /RAS

• 4 Banks can operates simultaneously and

independently

• Burst read/write operation and burst read/single write

operation capability

• Programmable burst length (BL): 1, 2, 4, 8, Full page

• 2 variations of burst sequence
 Sequential
 Interleave

• Programmable /CAS latency (CL): 2, 3

• Byte control by DQMB

• Refresh cycles: 8192 refresh cycles/64ms

• 2 variations of refresh
 Auto refresh
 Self refresh

Document No. E0241E30 (Ver. 3.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002

Ordering Information

Part number

EBS25UC8APMA-7A
EBS25UC8APMA-75*
EBS25UC8APMA-80

EBS25UC8APMA-7AL
EBS25UC8APMA-75L*
EBS25UC8APMA-80L

Note: 100MHz operation at /CAS latency = 2.

Clock frequency
MHz (max.)

133
133
100

133
133
100

/CAS latency Package

2, 3
3
2, 3

2, 3
3
2, 3

Pin Configurations

1pin 143pin

2pin 144pin

EBS25UC8APMA

Contact pad

144-pin Micro DIMM Gold EDS2508APSA

Front Side

Mounted devices

Back Side

Front side Back side

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VSS 73 NC 2 VSS 74 CLK1

3 DQ0 75 VSS 4 DQ32 76 VSS

5 DQ1 77 NC 6 DQ33 78 NC

7 DQ2 79 NC 8 DQ34 80 NC

9 DQ3 81 VDD 10 DQ35 82 VDD

11 VDD 83 DQ16 12 VDD 84 DQ48

13 DQ4 85 DQ17 14 DQ36 86 DQ49

15 DQ5 87 DQ18 16 DQ37 88 DQ50

17 DQ6 89 DQ19 18 DQ38 90 DQ51

19 DQ7 91 VSS 20 DQ39 92 VSS

21 VSS 93 DQ20 22 VSS 94 DQ52

23 DQMB0 95 DQ21 24 DQMB4 96 DQ53

25 DQMB1 97 DQ22 26 DQMB5 98 DQ54

27 VDD 99 DQ23 28 VDD 100 DQ55

29 A0 101 VDD 30 A3 102 VDD

31 A1 103 A6 32 A4 104 A7

33 A2 105 A8 34 A5 106 BA0

35 VSS 107 VSS 36 VSS 108 VSS

37 DQ8 109 A9 38 DQ40 110 BA1

39 DQ9 111 A10 (AP) 40 DQ41 112 A11

Data Sheet E0241E30 (Ver. 3.0)

2

EBS25UC8APMA

Front side Back side

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

41 DQ10 113 VDD 42 DQ42 114 VDD

43 DQ11 115 DQMB2 44 DQ43 116 DQMB6

45 VDD 117 DQMB3 46 VDD 118 DQMB7

47 DQ12 119 VSS 48 DQ44 120 VSS

49 DQ13 121 DQ24 50 DQ45 122 DQ56

51 DQ14 123 DQ25 52 DQ46 124 DQ57

53 DQ15 125 DQ26 54 DQ47 126 DQ58

55 VSS 127 DQ27 56 VSS 128 DQ59

57 NC 129 VDD 58 NC 130 VDD

59 NC 131 DQ28 60 NC 132 DQ60

61 CLK0 133 DQ29 62 CKE0 134 DQ61

63 VDD 135 DQ30 64 VDD 136 DQ62

65 /RAS 137 DQ31 66 /CAS 138 DQ63

67 /WE 139 VSS 68 NC 140 VSS

69 /CS0 141 SDA 70 A12 142 SCL

71 NC 143 VDD 72 NC 144 VDD

Pin Description

Pin name Function

A0 to A12 Address input

— Row address A0 to A12
— Column address A0 to A9

BA0, BA1 Bank select address

DQ0 to DQ63 Data-input/output

/CS0 Chip select

/RAS Row address asserted bank enable

/CAS Column address asserted

/WE Write enable

DQMB0 to DQMB7 Byte input/output mask

CLK0, CLK1 Clock input

CKE0 Clock enable

SDA Data-input/output for serial PD

SCL Clock input for serial PD

VDD Power supply

VSS Ground

NC No connection

Data Sheet E0241E30 (Ver. 3.0)

3

EBS25UC8APMA

Serial PD Matrix

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1 Total SPD memory size 0 0 0 0 1 0 0 0 08H 256 bytes

2 Memory type 0 0 0 0 0 1 0 0 04H SDRAM

3 Number of row addresses bits 0 0 0 0 1 1 0 1 0DH 13

4 Number of column addresses bits 0 0 0 0 1 0 1 0 0AH 10

5 Number of banks 0 0 0 0 0 0 0 1 01H 1

6 Module data width 0 1 0 0 0 0 0 0 40H 64 bits

7 Module data width (continued) 0 0 0 0 0 0 0 0 00H 0

8 Module interface signal levels 0 0 0 0 0 0 0 1 01H LVTTL

9

(-80/80L) 1 0 0 0 0 0 0 0 80H 8ns

10

(-80/80L) 0 1 1 0 0 0 0 0 60H 6ns

11 Module configuration type 0 0 0 0 0 0 0 0 00H None.

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H 7.8µs
13 SDRAM width 0 0 0 0 1 0 0 0 08H × 8

14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00H None.

15

16

17

18

19

20

21 SDRAM device attributes 0 0 0 0 0 0 0 0 00H

22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0EH

23

(-75/75L, -80/80L) 1 0 1 0 0 0 0 0 A0H 10ns

24

(-75/75L, -80/80L) 0 1 1 0 0 0 0 0 60H 6ns

25 to 26 0 0 0 0 0 0 0 0 00H

27

(-75/75L, -80/80L) 0 0 0 1 0 1 0 0 14H 20ns

Number of bytes used by module
manufacturer

SDRAM cycle time at CL = 3
(highest /CAS latency)
(-7A/7AL, -75/75L)

SDRAM access from Clock at CL = 3
(highest /CAS latency)
(-7A/7AL, -75/75L)

SDRAM device attributes:
minimum clock delay for back-to­back random column addresses

SDRAM device attributes:
Burst lengths supported

SDRAM device attributes: number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

SDRAM cycle time at CL = 2
(2nd highest /CAS latency)
(-7A/7AL)

SDRAM access from Clock at CL = 2
(2nd highest /CAS latency)
(-7A/7AL)

Minimum row precharge time
(-7A/7AL)

1 0 0 0 0 0 0 0 80H 128 bytes

0 1 1 1 0 1 0 1 75H 7.5ns

0 1 0 1 0 1 0 0 54H 5.4ns

0 0 0 0 0 0 0 1 01H 1 CLK

1 0 0 0 1 1 1 1 8FH 1,2,4,8,F

0 0 0 0 0 1 0 0 04H 4

0 0 0 0 0 1 1 0 06H 2,3

0 0 0 0 0 0 0 1 01H 0

0 0 0 0 0 0 0 1 01H 0

0 1 1 1 0 1 0 1 75H 7.5ns

0 1 0 1 0 1 0 0 54H 5.4ns

0 0 0 0 1 1 1 1 0FH 15ns

Data Sheet E0241E30 (Ver. 3.0)

4

EBS25UC8APMA

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

28

(-80/80L) 0 0 0 1 0 0 0 0 10H 16ns

29

(-75/75L, -80/80L) 0 0 0 1 0 1 0 0 14H 20ns

30

(-80/80L) 0 0 1 1 0 0 0 0 30H 48ns

31 Density of each bank on module 0 1 0 0 0 0 0 0 40H 256MB

32

(-80/80L) 0 0 1 0 0 0 0 0 20H 2ns

33

(-80/80L) 0 0 0 1 0 0 0 0 10H 1ns

34

(-80/80L) 0 0 1 0 0 0 0 0 20H 2ns

35

(-80/80L) 0 0 0 1 0 0 0 0 10H 1ns

36 to 61 Superset information 0 0 0 0 0 0 0 0 00H

62 SPD data revision code 0 0 0 1 0 0 1 0 12H 1.2

63

(-75/75L) 1 0 1 1 1 0 0 1 B9H

(-80/80L) 1 1 1 1 1 0 1 0 FAH

64 to 65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH Continuation code

66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location

73 to 90 Manufacturer’s part number

91 to 92 Revision code

93 to 94 Manufacturing date

95 to 98 Assembly serial number

99 to 127 Manufacturer specific data

Row active to row active min
(-7A/7AL, -75/75L)

/RAS to /CAS delay min
(-7A/7AL)

Minimum /RAS pulse width
(-7A/7AL, -75/75L)

Address and command signal input
setup time
(-7A/7AL, -75/75L)

Address and command signal input
hold time
(-7A/7AL, -75/75L)

Data signal input setup time
(-7A/7AL, -75/75L)

Data signal input hold time
(-7A/7AL, -75/75L)

Checksum for Bytes 0 to 62
(-7A/7AL)

0 0 0 0 1 1 1 1 0FH 15ns

0 0 0 0 1 1 1 1 0FH 15ns

0 0 1 0 1 1 0 1 2DH 45ns

0 0 0 1 0 1 0 1 15H 1.5ns

0 0 0 0 1 0 0 0 08H 0.8ns

0 0 0 1 0 1 0 1 15H 1.5ns

0 0 0 0 1 0 0 0 08H 0.8ns

0 1 1 1 1 0 0 0 78H

Data Sheet E0241E30 (Ver. 3.0)

5

Block Diagram

EBS25UC8APMA

/CS0

/WE

DQMB0

DQ0 to DQ7

DQMB2

DQ16 to DQ23

DQMB4

DQ32 to DQ39

DQMB6

8

8

8

N0, N1

N2, N3

N4, N5

/CS

/CS

/CS

/CS

D0

D2

D4

DQMB1

DQ8 to DQ15

DQMB3

DQ24 to DQ31

DQMB5

DQ40 to DQ47

DQMB7

N8, N9

8

N10, N11

8

N12, N13

8

/CS

D1

/CS

D3

/CS

D5

/CS

N6, N7

DQ48 to DQ55

/RAS
/CAS

A0 to A12

BA0

BA1

CKE0

CLK0

VDD VDD (D0 to D7)

C100 to C118

VSS

CLK1

10Ω

8

/RAS (D0 to D7)
/CAS (D0 to D7)

A0 to A12 (D0 to D7)

BA0 (D0 to D7)

BA1 (D0 to D7)
CKE (D0 to D7)
CLK (D0 to D7)

VSS (D0 to D7)

10pF

D6

N14, N15

VSS

8

SCL
A0

A1
A2

Serial PD

SDA

U0

DQ55 to DQ64

SCL

Notes :

1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.

2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.

* D0 to D7: 256M bits SDRAM

U0: 2k bits EEPROM
C100 to C118: 0.1µF
N0 to N15: Network resistors (10Ω)

D7

SDA

Data Sheet E0241E30 (Ver. 3.0)

6

EBS25UC8APMA

Electrical Specifications

• All voltages are referenced to VSS (GND).

• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before

proper device operation is achieved.

Absolute Maximum Ratings

Parameter Symbol Value Unit Note

Voltage on any pin relative to VSS VT

Supply voltage relative to VSS VDD –0.5 to +4.6 V

Short circuit output current IOS 50 mA

Power dissipation PD 8 W

Operating temperature TA 0 to +70 °C 1

Storage temperature Tstg –55 to +125 °C

–0.5 to VDD + 0.5
(≤ 4.6 (max.))

V

Notes: 1. SDRAM device specification

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = 0 to +70°C) (SDRAM device specification)

Parameter Symbol min. max. Unit Note

Supply voltage VDD 3.0 3.6 V 1

VSS 0 0 V 2

Input high voltage VIH 2.0 VDD + 0.3 V 3

Input low voltage VIL −0.3 0.8 V 4

Notes: 1. The supply voltage with all VDD pins must be on the same level.

2. The supply voltage with all VSS pins must be on the same level.

3. VIH (max.) = VDD + 2.0V for pulse width ≤ 3ns at VDD.

4. VIL (min.) = VSS − 2.0V for pulse width ≤ 3ns at VSS.

Data Sheet E0241E30 (Ver. 3.0)

7

EBS25UC8APMA

DC Characteristics 1 (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V)

Parameter Symbol Grade max. Unit Test condition Notes

Operating current ICC1 -7A/7AL 1040 mA

ICC1 -75/75L 880 mA

ICC1 -80/80L 855 mA

Standby current in power down ICC2P 24 mA CKE = VIL, tCK = 12ns 6

Standby current in non power
down

Active standby current in power
down

Active standby current in non
power down

Burst operating current ICC4 1080 mA tCK = tCK (min.), BL = 4 1, 2, 5

Refresh current ICC5 -7A/7AL 2000 mA tRC = tRC (min.) 3

ICC5 -75/75L 1760 mA

ICC5 -80/80L 1700 mA

Self refresh current ICC6 24 mA

Self refresh current
(L-version)

ICC2N 160 mA

ICC3P 32 mA CKE = VIL, tCK = 12ns 1, 2, 6

ICC3N 240 mA

ICC6 -XXL 8 mA

Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output

open condition

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, /CLK operating current.

7. After self refresh mode set, self refresh current.

Burst length = 1
tRC = tRC (min.)

CKE, /CS = VIH,
tCK = 12ns

CKE, /CS = VIH,
tCK = 12ns

VIH ≥ VDD – 0.2V
VIL ≤ 0.2V

1, 2, 3

4

1, 2, 4

7

DC Characteristics 2 (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V)

Parameter Symbol min. max. Unit Test condition Notes

Input leakage current ILI –8 8 µA 0 ≤ VIN ≤ VDD

Output leakage current ILO –1.5 1.5 µA

Output high voltage VOH 2.4 — V IOH = –4mA

Output low voltage VOL — 0.4 V IOL = 4mA

0 ≤ VOUT ≤ VDD
DQ = disable

Data Sheet E0241E30 (Ver. 3.0)

8

EBS25UC8APMA

Pin Capacitance (TA = +25°C, VDD = 3.3V ± 0.3V)

Parameter Symbol Pins max. Unit

Input capacitance CI1 Address 25.0 pF

CI2 /RAS, /CAS, /WE 23.0 pF

CI3 CKE 23.0 pF

CI4 /CS 23.0 pF

CI5 CLK 23.0 pF

CI6 DQMB 5.0 pF

Data input/output capacitance CI/O1 DQ 6.0 pF

AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification)

-7A/7AL -75/75L -80/80L

Parameter Symbol min. max. min. max. min. max. Unit Notes

System clock cycle time
(CL = 2)

(CL = 3) tCK 7.5 — 7.5 — 10 — ns

CLK high pulse width tCH 2.5 — 2.5 — 3 — ns 1

CLK low pulse width tCL 2.5 — 2.5 — 3 — ns 1

Access time from CLK tAC — 5.4 — 5.4 — 6 ns 1, 2

Data-out hold time tOH 2.7 — 2.7 — 2.7 — ns 1, 2

CLK to Data-out low impedance tLZ 1 — 1 — 1 — ns 1, 2, 3

CLK to Data-out high impedance tHZ — 5.4 — 5.4 — 6 ns 1, 4

Input setup time tSI 1.5 — 1.5 — 2 — ns 1

Input hold time tHI 0.8 — 0.8 — 1 — ns 1

Ref/Active to Ref/Active command period tRC 60 — 67.5 — 70 — ns 1

Active to Precharge command period tRAS 45 120000 45 120000 48 120000 ns 1

Active command to column command
(same bank)

Precharge to active command period tRP 15 — 20 — 20 — ns 1

Write recovery or data-in to precharge
lead time

Last data into active latency tDAL

Active (a) to Active (b) command period tRRD 15 — 15 — 20 — ns 1

Transition time (rise and fall) tT 0.5 5 0.5 5 0.5 5 ns

Refresh period
(8192 refresh cycles)

tCK 7.5 — 10 — 10 — ns 1

tRCD 15 — 20 — 20 — ns 1

tDPL 15 — 15 — 20 — ns 1

2CLK +
15ns

tREF — 64 — 64 — 64 ms

—

2CLK +
20ns

—

2CLK +
20ns

—

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

2. Access time is measured at 1.4V. Load condition is CL = 50pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

Notes

Data Sheet E0241E30 (Ver. 3.0)

9

Test Conditions

• Input and output timing reference levels: 1.4V

• Input waveform and output load: See following figures

EBS25UC8APMA

2.4V

0.4V

2.0V

0.8V

t

T

tT

DQ

CL

Input Waveform and Output Load

Relationship Between Frequency and Minimum Latency (SDRAM device specification)

Parameter -7A/7AL -75/75L -80/80L

Frequency (MHz) 133 133 10

tCK (ns) 7.5 7.5 10

/CAS latency Symbol CL = 2 CL = 3 CL = 2 Notes

Active command to column command
(same bank)

Active command to active command
(same bank)

Active command to precharge command
(same bank)

Precharge command to active command
(same bank)

Write recovery or data-in to precharge
command (same bank)

Active command to active command
(different bank)

Self refresh exit time lSREX 1 1 1 2

Last data in to active command
(Auto precharge, same bank)

Self refresh exit to command input lSEC 8 9 7

Precharge command to high impedance lHZP 2 3 2

Last data out to active command
(auto precharge) (same bank)

Last data out to precharge (early precharge) lEP –1 –2 –1

Column command to column command lCCD 1 1 1

Write command to data in latency lWCD 0 0 0

DQM to data in lDID 0 0 0

DQM to data out lDOD 2 2 2

CKE to CLK disable lCLE 1 1 1

Register set to active command lMRD 2 2 2

/CS to command disable lCDD 0 0 0

Power down exit to command input lPEC 1 1 1

lRCD 2 3 2 1

lRC 8 9 7 1

lRAS 6 6 5 1

lRP 2 3 2 1

lDPL 2 2 2 1

lRRD 2 2 2 1

lDAL 4 5 4 = [lDPL + lRP]

= [lRC]
3

lAPR 1 1 1

Notes: 1. IRCD to IRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

Data Sheet E0241E30 (Ver. 3.0)

10

EBS25UC8APMA

Pin Functions

CLK0, CLK1 (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK

rising edge.

/CS0 (input pin): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.

/RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they
function in a different way. These pins define operation commands (read, write, etc.) depending on the combination
of their voltage levels. For details, refer to the command operation section.

A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command
cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command
cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge
mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the
precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged.

BA0 and BA1 (input pin)

BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL

CKE0 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock suspend
modes.

DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the
DQMB is Low, the output buffer becomes Low-Z.

Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data
is written.

DQ0 to DQ63 (input/output pins): Data is input to and output from these pins.

VDD (power supply pins): 3.3V is applied.

VSS (power supply pins): Ground is connected.

Detailed Operation Part

Refer to the EDS2504APSA/08APSA/16APSA (E0228E).

Data Sheet E0241E30 (Ver. 3.0)

11

Physical Outline

EBS25UC8APMA

1.0 min.

30.0

R1.0 ± 0.1

15.0

A

42.0 max.
(38.0)

1.0 min.

Component area

(front)

2.5 min.

1

17.625

35.50

37.0 ± 0.08

35.50

17.875

2

B

0.875

0.625

3.5 min.

3.80 max.

3.5 min.

0.80 ± 0.08

Unit: mm

4-R1.0 ± 0.1

1.0 min. 1.0 min.

Detail A

5.0 ± 0.1

Component area

1.0 ± 0.08

(back)

Detail B

0.37 ± 0.03

4.0 ± 0.1

0.50

2.00 min.

0.25 max.

ECA-TS2-0028-01

Data Sheet E0241E30 (Ver. 3.0)

12

EBS25UC8APMA

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.

When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

MDE0202

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.

CME0107

Data Sheet E0241E30 (Ver. 3.0)

13

EBS25UC8APMA

µBGA is registered trademark of Tessera, Inc.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.

M01E0107

Data Sheet E0241E30 (Ver. 3.0)

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