Datasheet EBD21RD4ABNA-7B, EBD21RD4ABNA-7A, EBD21RD4ABNA-10 Datasheet (ELPID)

PRELIMINARY DATA SHEET

2GB Registered DDR SDRAM DIMM

EBD21RD4ABNA

(256M words ×××× 72 bits, 2 Banks)

Description

The EBD21RD4ABNA is a 256M words × 72 bits, 2

bank Double Data Rate (DDR) SDRAM Module,
mounted 36 pieces of DDR SDRAM sealed in TCP
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high­speed data transfer is realized by the 2-bit prefetch­pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each TCP
on the module board.

Note: Do not push the cover or drop the modules in

order to avoid mechanical defects, which may
result in electrical defects.

Features

• 184-pin socket type dual in line memory module

(DIMM)

 PCB height: 30.48mm
 Lead pitch: 1.27mm

• 2.5V power supply

• Data rate: 266Mbps/200Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at
the receiver

• Data inputs and outputs are synchronized with DQS

• 4 internal banks for concurrent operation

(Component)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• LL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)
 7.8µs maximum average periodic refresh interval

• 2 variations of refresh
 Auto refresh
 Self refresh

• 1 piece of PLL clock driver, 1 piece of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)

Document No. E0273E20 (Ver. 2.0)
Date Published Aug 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002

EBD21RD4ABNA

Ordering Information

Part number

EBD21RD4ABNA-7A
EBD21RD4ABNA-7B
EBD21RD4ABNA-10

Notes: 1. Module /CAS latency = component CL + 1

2. Please refer to 512Mb DDR TSOP product datasheet (E0237E) for electrical characteristics.

Pin Configurations

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

1 VREF 47 DQS8 93 VSS 139 VSS

2 DQ0 48 A0 94 DQ4 140 DM8/DQS17

3 VSS 49 CB2 95 DQ5 141 A10

4 DQ1 50 VSS 96 VDDQ 142 CB6

5 DQS0 51 CB3 97 DM0/DQS9 143 VDDQ

6 DQ2 52 BA1 98 DQ6 144 CB7

7 VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDDQ 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 /RESET 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC 149 DM4/DQS13

12 DQ8 58 VSS 104 VDDQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDDQ 61 DQ40 107 DM1/DQS10 153 DQ44

16 NC 62 VDDQ 108 VDD 154 /RAS

17 NC 63 /WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDDQ

19 DQ10 65 /CAS 111 CKE1 157 /CS0

20 DQ11 66 VSS 112 VDDQ 158 /CS1

21 CKE0 67 DQS5 113 NC 159 DM5/DQS14

22 VDDQ 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 A12 161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 VSS 72 DQ48 118 A11 164 VDDQ

27 A9 73 DQ49 119 DM2/DQS11 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

Data rate
Mbps (max.)

266
266
200

Component JEDEC speed bin*1
(CL-tRCD-tRP)

DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)

Front side

1 pin

93 pin 144 pin 145 pin184 pin

Back side

52 pin53 pin 92 pin

Package

184-pin
DIMM

Contact
pad

Gold

Mounted devices

512M bits DDR
SDRAM TCP*

2

Preliminary Data Sheet E0273E20 (Ver. 2.0)

2

EBD21RD4ABNA

Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name

29 A7 75 NC 121 DQ22 167 NC

30 VDDQ 76 NC 122 A8 168 VDD

31 DQ19 77 VDDQ 123 DQ23 169 DM6/DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDDQ

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 VDDID 128 VDDQ 174 DQ60

37 A4 83 DQ56 129 DM3/DQS12 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 CB4 180 VDDQ

43 A1 89 VSS 135 CB5 181 SA0

44 CB0 90 NC 136 VDDQ 182 SA1

45 CB1 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 /CK0 184 VDDSPD

Preliminary Data Sheet E0273E20 (Ver. 2.0)

3

Pin Description

Pin name Function

Address input

A0 to A12

BA0, BA1 Bank select address

DQ0 to DQ63 Data input/output

CB0 to CB7 Check bit (Data input/output)

/RAS Row address strobe command

/CAS Column address strobe command

/WE Write enable

/CS0, /CS1 Chip select

CKE0, CKE1 Clock enable

CK0 Clock input

/CK0 Differential clock input

DQS0 to DQS8 Input and output data strobe

DM0 to DM8/DQS9 to DQS17 Input and output data strobe

SCL Clock input for serial PD

SDA Data input/output for serial PD

SA0 to SA2 Serial address input

VDD Power for internal circuit

VDDQ Power for DQ circuit

VDDSPD Power for serial EEPROM

VREF Input reference voltage

VSS Ground

VDDID VDD identification flag

/RESET Reset pin (forces register inputs low)

NC No connection

Row address A0 to A12
Column address A0 to A9, A11, A12

EBD21RD4ABNA

Preliminary Data Sheet E0273E20 (Ver. 2.0)

4

EBD21RD4ABNA

Serial PD Matrix*

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

0

1

2 Memory type 0 0 0 0 0 1 1 1 07H SDRAM DDR

3 Number of row address 0 0 0 0 1 1 0 1 0DH 13

4 Number of column address 0 0 0 0 1 1 0 0 0CH 12

5 Number of DIMM banks 0 0 0 0 0 0 1 0 02H 2

6 Module data width 0 1 0 0 1 0 0 0 48H 72 bits

7 Module data width continuation 0 0 0 0 0 0 0 0 00H 0 (+)

8 Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H SSTL 2.5V

9

-10 1 0 1 0 0 0 0 0 A0H

10

-10 1 0 0 0 0 0 0 0 80H 0.8ns*3

11 DIMM configuration type 0 0 0 0 0 0 1 0 02H ECC

12 Refresh rate/type 1 0 0 0 0 0 1 0 82H

13 Primary SDRAM width 0 0 0 0 0 1 0 0 04H × 4
14 Error checking SDRAM width 0 0 0 0 0 1 0 0 04H × 4

15

16

17

18

19

20

21 SDRAM module attributes 0 0 1 0 0 1 1 0 26H Registered

22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H ± 0.2V

23

-7B, -10 1 0 1 0 0 0 0 0 A0H

24

-10 1 0 0 0 0 0 0 0 80H 0.8ns*3

25 Minimum clock cycle time at CLX - 1 0 0 0 0 0 0 0 0 00H

26

27 Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50H 20ns

28

29 Minimum /RAS to /CAS delay (tRCD) 0 1 0 1 0 0 0 0 50H 20ns

Number of bytes utilized by module
manufacturer

Total number of bytes in serial PD
device

DDR SDRAM cycle time, CL = X

-7A, -7B

SDRAM access from clock (tAC)

-7A, -7B

SDRAM device attributes:
Minimum clock delay back-to-back
column access

SDRAM device attributes:
Burst length supported

SDRAM device attributes: Number of
banks on SDRAM device

SDRAM device attributes:
/CAS latency

SDRAM device attributes:
/CS latency

SDRAM device attributes:
/WE latency

Minimum clock cycle time at CLX - 0.5

-7A

Maximum data access time (tAC) from
clock at CLX - 0.5

-7A, -7B

Maximum data access time (tAC) from
clock at CLX - 1

Minimum row active to row active
delay (tRRD)

1

1 0 0 0 0 0 0 0 80H 128

0 0 0 0 1 0 0 0 08H 256 byte

0 1 1 1 0 1 0 1 75H CL = 2.5*3

0 1 1 1 0 1 0 1 75H 0.75ns*3

7.8 µs
Self refresh

0 0 0 0 0 0 0 1 01H 1 CLK

0 0 0 0 1 1 1 0 0EH 2, 4, 8

0 0 0 0 0 1 0 0 04H 4

0 0 0 0 1 1 0 0 0CH 2, 2.5

0 0 0 0 0 0 0 1 01H 0

0 0 0 0 0 0 1 0 02H 1

0 1 1 1 0 1 0 1 75H CL = 2*3

0 1 1 1 0 1 0 1 75H 0.75ns*3

0 0 0 0 0 0 0 0 00H

0 0 1 1 1 1 0 0 3CH 15ns

Preliminary Data Sheet E0273E20 (Ver. 2.0)

5

EBD21RD4ABNA

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

30

-10 0 0 1 1 0 0 1 0 32H 50ns

31 Module bank density 0 0 0 0 0 0 0 1 01H

32

-10 1 0 1 1 0 0 0 0 B0H 1.1ns*3

33

-10 1 0 1 1 0 0 0 0 B0H 1.1ns*3

34

-10 0 1 1 0 0 0 0 0 60H 0.6ns*3

35

-10 0 1 1 0 0 0 0 0 60H 0.6ns*3

36 to 40 Superset information 0 0 0 0 0 0 0 0 00H Future use

41

-10 0 1 0 0 0 1 1 0 46H 70ns*3

42

-10 0 1 0 1 0 0 0 0 50H 80ns*3

43 SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H 12ns*3

44

-10 0 0 1 1 1 1 0 0 3CH 600ps*3

45

-10 1 0 1 0 0 0 0 0 A0H 1000ps*3

46 to 61 Superset information 0 0 0 0 0 0 0 0 00H Future use

62 SPD revision 0 0 0 0 0 0 0 0 00H Initial

63

-7B 1 0 1 1 1 0 0 0 B8H 184

-10 1 0 0 1 1 0 1 1 9BH 155

64 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH

65 Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1 7FH

66 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory

67 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H

72 Manufacturing location × × × × × × × × ××

73 Module part number 0 1 0 0 0 1 0 1 45H E

74 Module part number 0 1 0 0 0 0 1 0 42H B

75 Module part number 0 1 0 0 0 1 0 0 44H D

76 Module part number 0 0 1 1 0 0 1 0 32H 2

Minimum active to precharge time
(tRAS)

-7A, -7B

Address and command setup time
before clock (tIS)

-7A, -7B

Address and command hold time after
clock (tIH)

-7A, -7B

Data input setup time before clock
(tDS)

-7A, -7B

Data input hold time after clock (tDH)

-7A, -7B

Active command period (tRC)

-7A, -7B

Auto refresh to active/
Auto refresh command cycle (tRFC)

-7A, -7B

Dout to DQS skew

-7A, -7B

Data hold skew (tQHS)

-7A, -7B

Checksum for bytes 0 to 62

-7A

0 0 1 0 1 1 0 1 2DH 45ns

2 banks
1GB

1 0 0 1 0 0 0 0 90H 0.9ns*3

1 0 0 1 0 0 0 0 90H 0.9ns*3

0 1 0 1 0 0 0 0 50H 0.5ns*3

0 1 0 1 0 0 0 0 50H 0.5ns*3

0 1 0 0 0 0 1 1 43H 67.5ns*3

0 1 0 0 1 0 1 1 4BH 75ns*3

0 0 1 1 0 0 1 0 32H 500ps*3

0 1 1 1 0 1 0 1 75H 750ps*3

1 0 0 0 1 1 0 1 8DH 141

2

*

(ASCII-8bit

code)

Preliminary Data Sheet E0273E20 (Ver. 2.0)

6

EBD21RD4ABNA

Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments

77 Module part number 0 0 1 1 0 0 0 1 31H 1

78 Module part number 0 1 0 1 0 0 1 0 52H R

79 Module part number 0 1 0 0 0 1 0 0 44H D

80 Module part number 0 0 1 1 0 1 0 0 34H 4

81 Module part number 0 1 0 0 0 0 0 1 41H A

82 Module part number 0 1 0 0 0 0 1 0 42H B

83 Module part number 0 1 0 0 1 1 1 0 4EH N

84 Module part number 0 1 0 0 0 0 0 1 41H A

85 Module part number 0 0 1 0 1 1 0 1 2DH —

86

-10 0 0 1 1 0 0 0 1 31H 1

87

-7B 0 1 0 0 0 0 1 0 42H B

-10 0 0 1 1 0 0 0 0 30H 0

88 to 90 Module part number 0 0 1 0 0 0 0 0 20H (Space)

91 Revision code 0 0 1 1 0 0 0 0 30H Initial

92 Revision code 0 0 1 0 0 0 0 0 20H (Space)

93 Manufacturing date × × × × × × × × ××

94 Manufacturing date × × × × × × × × ××

95 to 98 Module serial number *2

99 to 127 Manufacturer specific data

Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These

2. Bytes 95 through 98 are assembly serial number.

3. These specifications are defined based on component specification, not module.

Module part number

-7A, -7B

Module part number

-7A

0 0 1 1 0 1 1 1 37H 7

0 1 0 0 0 0 0 1 41H A

SPD are based on JEDEC Committee Ballot JC-42.5-99-129.

Year code
(HEX)

Week code
(HEX)

Preliminary Data Sheet E0273E20 (Ver. 2.0)

7

Block Diagram

VSS

/RCS1
/RCS0

DQS0

DQ0 to DQ3

DQS1

DQ8 to DQ11

DQS2

DQ16 to DQ19

DQS3

DQ24 to DQ27

DQS4

DQ32 to DQ35

DQS5

DQ40 to DQ43

DQS6

DQ48 to DQ51

DQS7

DQ56 to DQ59

DQS8

CB0 to CB3

/CS0
/CS1

BA0 to BA1

A0 to A12

/RAS

/CAS
CKE0
CKE1

/WE

PCK

/PCK

VDD, VDDQ

VREF

VSS

VDDID

CK0, /CK0

Note: Wire per Clock loading table/Wiring diagrams.

R

S

R

S

R

S

R

S

R

S

R

S

R

S

R

S

R

S

open

EBD21RD4ABNA

R

S

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R
E
G

I
S
T
E
R

D0

DQ

DQS DM/CS

D1

DQ

DQS DM/CS

D2

DQ

DQS DM/CS

D3

DQ

DQS DM/CS

D4

DQ

DQS DM/CS

D5

DQ

DQS DM/CS

D6

DQ

DQS DM/CS

D7

DQ

DQS DM/CS

D8

DQ

/RCS0 -> /CS: SDRAMs D0 to D17
/RCS1 -> /CS: SDRAMs D18 to D35
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35
/RRAS -> /RAS: SDRAMs D0 to D35
/RCAS -> /CAS: SDRAMs D0 to D35
RCKE0 -> CKE: SDRAMs D0 to D17
RCKE1 -> CKE: SDRAMs D18 to D35
/RWE -> /WE: SDRAMs D0 to D35

/RESET

D0 to D35
D0 to D35
D0 to D35

PLL*

/CS

DQS DM

R

4

/CS

DQS DM

D18

DQ

DQS DM/CS

D19

DQ

DQS DM/CS

D20

DQ

DQS DM/CS

D21

DQ

DQS DM/CS

D22

DQ

DQS DM/CS

D23

DQ

DQS DM/CS

D24

DQ

DQS DM/CS

D25

DQ

DQS DM/CS

D26

DQ

DM0/DQS9

DQ4 to DQ7

DM1/DQS10

DQ12 to DQ15

DM2/DQS11

DQ20 to DQ23

DM3/DQS12

DQ28 to DQ31

DM4/DQS13

DQ36 to DQ39

DM5/DQS14

DQ44 to DQ47

DM6/DQS15

DQ52 to DQ55

DM7/DQS16

DQ60 to DQ63

DM8/DQS17

CB4 to CB7

R

S

/CS

DQS DM

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

R

S

R

4

S

* D0 to D35: 512M bits DDR SDRAM TCP

U0: 2k bits EEPROM
R

: 22Ω (DQ, DQS)

S

PLL: CDCV857
Register: SSTV32852

SCL

DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

Serial PD

SCL

D9

D10

D11

D12

D13

D14

D15

D16

D17

SDA

DQS DM
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

DQS DM/CS
DQ

U0

A0

A1 A2

Notes:

1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.

2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.

SA0 SA1 SA2

/CS

D27

D28

D29

D30

D31

D32

D33

D34

D35

SDA

Preliminary Data Sheet E0273E20 (Ver. 2.0)

8

Differential Clock Net Wiring (CK0, /CK0)

0ns (nominal)

EBD21RD4ABNA

PLL

OUT1

CK0

/CK0

Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl

be set to 0 ns (nominal).

2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.

4. Termination resistors for feedback path clocks are located after the pins of the PLL.

120Ω

IN

240Ω

120Ω

C

OUT'N'

Feedback

SDRAM

stack

SDRAM

stack

Register

120Ω

Preliminary Data Sheet E0273E20 (Ver. 2.0)

9

EBD21RD4ABNA

Electrical Specifications

• All voltages are referenced to VSS (GND).

• After power up, wait more than 200 µs and then, execute power on sequence and auto refresh before proper

device operation is achieved.

Absolute Maximum Ratings

Parameter Symbol Value Unit Note

Voltage on any pin relative to VSS VT –1.0 to +3.6 V

Supply voltage relative to VSS VDD, VDDQ –1.0 to +3.6 V

Short circuit output current IOUT 50 mA

Power dissipation PT 18 W

Operating ambient temperature TA 0 to +70 °C 1

Storage temperature Tstg –55 to +125 °C

Note: 1. DDR SDRAM device specification

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

DC Operating Conditions (TA = 0 to +70°C)

Parameter Symbol Min Typ Max Unit Notes

Supply voltage VDD,VDDQ 2.3 2.5 2.7 V 1

VSS 0 0 0 V

Input reference voltage VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V

Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V

Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2

Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3

Input voltage level,
CK and /CK inputs

Input differential cross point
voltage, CK and /CK inputs

Input differential voltage,
CK and /CK inputs

VIN (DC) –0.3 — VDDQ + 0.3 V 4

VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V

VID (DC) 0.36 — VDDQ + 0.6 V 5, 6

Notes: 1. VDDQ must be lower than or equal to VDD.

2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.

3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.

4. VIN (DC) specifies the allowable dc execution of each differential input.

5. VID (dc) specifies the input differential voltage required for switching.

6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.

Preliminary Data Sheet E0273E20 (Ver. 2.0)

10

EBD21RD4ABNA

DC Characteristics 1 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)

Parameter Symbol Grade max. Unit Test condition Notes

Operating current (ACTV-PRE) IDD0

Operating current
(ACTV-READ-PRE)

Idle power down standby current IDD2P

Floating idle
Standby current
Quiet idle
Standby current
Active power down standby
current

Active standby current IDD3N

Operating current
(Burst read operation)

Operating current
(Burst write operation)

Auto refresh current IDD5

Self refresh current IDD6

Operating current
(4 banks interleaving)

IDD1

IDD2F

IDD2Q

IDD3P

IDD4R

IDD4W

IDD7A

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

-7A, -7B

-10

Notes. 1. These IDD data are measured under condition that DQ pins are not connected.

2. One bank operation.

3. One bank active.

4. All banks idle.

5. Command/Address transition once per one cycle.

6. Data/Data mask transition twice per one cycle.

7. 4 banks active. Only one bank is running at tRC = tRC (min.)

8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.

9. Command/Address transition once per one every two clock cycles.

10. Command/Address stable at ≥ VIH or ≤ VIL.

3830
3550

4190
3910

427
420

1580
1390

1220
1210

1040
1030

2480
2290

4460
3820

4460
3820

6260
5800

463
457

7880
7240

mA

mA

mA CKE ≤ VIL 4

mA

mA

mA CKE ≤ VIL 3

mA

mA

mA

mA

mA

mA BL = 4 5, 6, 7

CKE ≥ VIH,
tRC = tRC (min.)

CKE ≥ VIH, BL = 4,
CL = 3.5, tRC = tRC (min.)

CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF

CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF

CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)

CKE ≥ VIH, BL = 2,
CL = 3.5

CKE ≥ VIH, BL = 2,
CL = 3.5

tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH

Input ≥ VDD – 0.2 V
Input ≤ 0.2 V

1, 2, 9

1, 2, 5

4, 5

4, 10

3, 5, 6

1, 2, 5, 6

1, 2, 5, 6

DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)

Parameter Symbol min. max. Unit Test condition Notes

Input leakage current IL –2 2 µA VDD ≥ VIN ≥ VSS

Output leakage current IOZ –5 5 µA VDDQ ≥ VOUT ≥ VSS

Output high current IOH –15.2 — mA VOUT = 1.95V

Output low current IOL 15.2 — mA VOUT = 0.35V

Preliminary Data Sheet E0273E20 (Ver. 2.0)

11

EBD21RD4ABNA

Pin Capacitance (TA = 25°C, VDD, VDDQ = 2.5V ± 0.2V)

Parameter Symbol Pins max. Unit Notes

Input capacitance CI1

Input capacitance CI2 CK, /CK TBD pF 1, 3

Data and DQS input/output
capacitance

CO DQ, DQS, CB, DM TBD pF 1, 2, 3

Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V.

2. Dout circuits are disabled.

3. This parameter is sampled and not 100% tested.

AC Characteristics (TA = 0 to +70°°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)

(DDR SDRAM device Specification)

-7A -7B -10

Parameter Symbol min. max min. max min. max Unit Notes

Clock cycle time
(CL = 2)

(CL = 2.5) tCK 7.5 12 7.5 12 10 12 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK half period tHP

DQ output access time from
CK, /CK

DQS output access time from CK,
/CK

DQS to DQ skew tDQSQ — 0.5 — 0.5 — 0.6 ns 3

DQ/DQS output hold time from
DQS

Data hold skew factor tQHS — 0.75 — 0.75 — 1.0 ns

Data-out high-impedance time
from CK, /CK

Data-out low-impedance time from
CK, /CK

Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQ and DM input setup time tDS 0.5 — 0.5 — 0.6 — ns 8

DQ and DM input hold time tDH 0.5 — 0.5 — 0.6 — ns 8

DQ and DM input pulse width tDIPW 1.75 — 1.75 — 2 — ns 7

Write preamble setup time tWPRES 0 — 0 — 0 — ns

Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 9

Write command to first DQS
latching transition

DQS falling edge to CK setup time tDSS 0.2 — 0.2 — 0.2 — tCK

DQS falling edge hold time from
CK

DQS input high pulse width tDQSH 0.35 — 0.35 — 0.35 — tCK

DQS input low pulse width tDQSL 0.35 — 0.35 — 0.35 — tCK

tCK 7.5 12 10 12 10 12 ns 10

tAC –0.75 0.75 –0.75 0.75 –0.8 0.8 ns 2, 11

tDQSCK –0.75 0.75 –0.75 0.75 –0.8 0.8 ns 2, 11

tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns

tHZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns 5, 11

tLZ –0.75 0.75 –0.75 0.75 –0.8 0.8 ns 6, 11

tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

tDSH 0.2 — 0.2 — 0.2 — tCK

Address, /RAS, /CAS, /WE,
/CS, CKE

min
(tCH, tCL)

—

min
(tCH, tCL)

TBD pF 1, 3

min

—

(tCH, tCL)

— tCK

Preliminary Data Sheet E0273E20 (Ver. 2.0)

12

EBD21RD4ABNA

-7A -7B -10

Parameter Symbol min. max min. max min. max Unit Notes

Address and control input setup
time

Address and control input hold
time

Address and control input pulse
width

Mode register set command cycle
time

Active to Precharge command
period

Active to Active/Auto refresh
command period

Auto refresh to Active/Auto refresh
command period

Active to Read/Write delay tRCD 20 — 20 — 20 — ns

Precharge to active command
period

Active to auto precharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns

Active to active command period tRRD 15 — 15 — 15 — ns

Write recovery time tWR 15 — 15 — 15 — ns

Auto precharge write recovery
and precharge time

Internal write to Read command
delay

Average periodic refresh interval tREF — 7.8 — 7.8 — 7.8 µs

Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter

definitions, see ‘Timing Waveforms’ section.

2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.

3. The timing reference level is VTT.

4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.

5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.

6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.

7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.

8. The timing reference level is VREF.

9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.

10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.

11. tCK = tCK (min.) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.

12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than

0.4V/400 cycle.

tIS 0.9 — 0.9 — 1.1 — ns 8

tIH 0.9 — 0.9 — 1.1 — ns 8

tIPW 2.2 — 2.2 — 2.5 — ns 7

tMRD 2 — 2 — 2 — tCK

tRAS 45 120000 45 120000 50 120000 ns

tRC 67.5 — 67.5 — 70 — ns

tRFC 75 — 75 — 80 — ns

tRP 20 — 20 — 20 — ns

tDAL

tWTR 1 — 1 — 1 — tCK

(tWR/tCK)
+(tRP/tCK)

—

(tWR/tCK)
+(tRP/tCK)

—

(tWR/tCK)
+(tRP/tCK)

— tCK 13

Preliminary Data Sheet E0273E20 (Ver. 2.0)

13

EBD21RD4ABNA

13. tDAL = (tWR/tCK)+(tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer.

Example: For –7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns,

tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3)
tDAL = 5 clocks

Timing Parameter Measured in Clock Cycle for Registered DIMM

Number of clock cycle

Parameter Symbol min. max.

Write to pre-charge command delay (same bank) tWPD 3 + BL/2

Read to pre-charge command delay (same bank) tRPD BL/2

Write to read command delay (to input all data) tWRD 2 + BL/2

Burst stop command to write command delay
(CL = 3)

(CL = 3.5) tBSTW 3

Burst stop command to DQ High-Z
(CL = 3)

(CL = 3.5) tBSTZ 3.5 3.5

Read command to write command delay (to output all data)
(CL = 3)

(CL = 3.5) tRWD 3 + BL/2

Pre-charge command to High-Z
(CL = 3)

(CL = 3.5) tHZP 3.5 3.5

Write command to data in latency tWCD 2 2

Write recovery tWR 1

Register set command to active or register set command tMRD 2

Self refresh exit to non-read command tSNR 10

Self refresh exit to read command tSRD 200

Power down entry tPDEN 1 1

Power down exit to command input tPDEX 1

tBSTW 2

tBSTZ 3 3

tRWD 2 + BL/2

tHZP 3 3

Preliminary Data Sheet E0273E20 (Ver. 2.0)

14

EBD21RD4ABNA

Pin Functions

CK, /CK (input pin)

The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross
point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross
point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and
the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.

/CS (input pin)

When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".

A0 to A12 (input pins)

Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11, AY12) is loaded via theA0 to the
A9, the A11 and the A12 at the cross point of the CK rising edge and the VREF level in a read or a write command
cycle. This column address becomes the starting address of a burst operation.

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.

BA0, BA1 (input pin)

BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)

[Bank Select Signal Table]

BA0 BA1

Bank 0 L L

Bank 1 H L

Bank 2 L H

Bank 3 H H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.

The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.

DQ, CB (input and output pins)

Data are input to and output from these pins.

DQS (input and output pin)

DQS provide the read data strobes (as output) and the write data strobes (as input).

Preliminary Data Sheet E0273E20 (Ver. 2.0)

15

EBD21RD4ABNA

VDD and VDDQ (power supply pins)

2.5V is applied. (VDD is for the internal circuit and VDDQ is for the output buffer.)

VDDSPD (power supply pin)

2.5V is applied (For serial EEPROM).

VSS (power supply pin)

Ground is connected.

/RESET (input pin)

LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.

Detailed Operation Part, AC Characteristics and Timing Waveforms

Refer to the EDD5104AB, EDD5108AB datasheet (E0237E). DM pins of component device fixed to VSS level on
the module board. DIMM /CAS latency = component CL + 1 for registered type.

Preliminary Data Sheet E0273E20 (Ver. 2.0)

16

Physical Outline

2.30

1 92

2 – φ 2.50 ± 0.10

133.35 ± 0.15

128.95

(64.48)

(DATUM -A-)

Component area

(Front)

64.77 49.53

EBD21RD4ABNA

Unit: mm

4.80

4.00 min

AB

1.27 ± 0.10

93

Component area

184

10.00

17.80

(Back)

30.48 ± 0.15

4.00 ± 0.10

R 2.00

Detail A

1.27 typ

2.50 ± 0.20

1.00 ± 0.05

Note: Tolerance on all dimensions ± 0.13 unless otherwise specified.

Detail B

0.20 ± 0.15

3.80

(DATUM -A-)

6.62

2.175
R 0.90

1.80 ± 0.10

6.35

3.00 min

ECA-TS2-0058-01

Preliminary Data Sheet E0273E20 (Ver. 2.0)

17

EBD21RD4ABNA

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.

When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

MDE0202

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.

CME0107

Preliminary Data Sheet E0273E20 (Ver. 2.0)

18

EBD21RD4ABNA

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.

M01E0107

Preliminary Data Sheet E0273E20 (Ver. 2.0)

19