Datasheet E28F400CV-T80 Datasheet (Intel Corporation)

E

PRELIMINARY

July 1997 Order Number: 290530-005

n

Intel SmartVoltage Technology



5V or 12V Program/Erase



2.7V, 3.3V or 5V Read Operation



Increased Programming Throughput
at 12V V

PP

n

Very High-Performance Read



5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time



3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time



2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time

n

Low Power Consumption



Max 60 mA Read Current at 5V



Max 30 mA Read Current at

2.7V–3.6V

n

x8/x16-Selectable Input/Output Bus



28F400 for High Performance 16- or
32-bit CPUs

n

x8-Only Input/Output Architecture



28F004B for Space-Constrained
8-bit Applications

n

Optimized Array Blocking Architecture



One 16-KB Protected Boot Block



Two 8-KB Parameter Blocks



One 96-KB Main Block



Three 128-KB Main Blocks



Top or Bottom Boot Locations

n

Absolute Hardware-Protection for Boot
Block

n

Software EEPROM Emulation with
Parameter Blocks

n

Extended Temperature Operation



–40°C to +85°C

n

Extended Cycling Capability



100,000 Block Erase Cycles
(Commercial Temperature)



10,000 Block Erase Cycles
(Extended Temperature)

n

Automated Word/Byte Program and
Block Erase



Industry-Standard Command User
Interface



Status Registers



Erase Suspend Capability

n

SRAM-Compatible Write Interface

n

Automatic Power Savings Feature



1 mA Typical ICC Active Current in
Static Operation

n

Reset/Deep Power-Down Input



0.2 µA ICCTypical



Provides Reset for Boot Operations

n

Hardware Data Protection Feature



Write Lockout during Power
Transitions

n

Industry-Standard Surface Mount
Packaging



40-Lead TSOP



44-Lead PSOP: JEDEC ROM
Compatible



48-Lead TSOP



56-Lead TSOP

n

Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories

n

ETOX™ IV Flash Technology

4-MBIT (256K X 16, 512K X 8)

SmartVoltage BOOT BLOCK FLASH

MEMORY FAMILY

28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B

28F400CE-T/B, 28F004BE-T/B

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B may contain design defects or errors

known as errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s Website at http:\\www.intel.com

COPYRIGHT © INTEL CORPORATION, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

3

PRELIMINARY

CONTENTS

PAGE PAGE

1.0 PRODUCT FAMILY OVERVIEW .................... 5

1.1 New Features in the SmartVoltage

Products .....................................................5

1.2 Main Features..............................................5

1.3 Applications .................................................7

1.4 Pinouts.........................................................7

1.5 Pin Descriptions.........................................11

2.0 PRODUCT DESCRIPTION............................13

2.1 Memory Blocking Organization ..................13

2.1.1 Boot Block........................................... 13

2.1.2 Parameter Blocks................................ 13

2.1.3 Main Blocks.........................................13

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION................................................ 15

3.1 Bus Operations..........................................15

3.2 Read Operations........................................15

3.2.1 Read Array.......................................... 15

3.2.2 Intelligent Identifiers ............................17

3.3 Write Operations........................................17

3.3.1 Command User Interface (CUI)...........17

3.3.2 Status Register ...................................20

3.3.3 Program Mode ....................................21

3.3.4 Erase Mode.........................................21

3.4 Boot Block Locking ....................................22

3.4.1 V

PP

= VIL for Complete Protection....... 22

3.4.2 WP# = V

IL

for Boot Block Locking .......22

3.4.3 RP# = V

HH

or WP# = VIH forr Boot Block

Unlocking...........................................22

3.4.4 Upgrade Note for 8-Mbit 44-PSOP

Package............................................. 22

3.5 Power Consumption...................................26

3.5.1 Active Power.......................................26

3.5.2 Automatic Power Savings (APS) .........26

3.5.3 Standby Power....................................26

3.5.4 Deep Power-Down Mode.....................26

3.6 Power-Up/Down Operation.........................26

3.6.1 RP# Connected to System Reset........26

3.6.2 V

CC

, VPP and RP# Transitions.............27

3.7 Power Supply Decoupling..........................27

3.7.1 V

PP

Trace on Printed Circuit Boards....27

4.0 ABSOLUTE MAXIMUM RATINGS................28

5.0 COMMERCIAL OPERATING CONDITIONS.29

5.1 Applying V

CC

Voltages...............................29

5.2 DC Characteristics.....................................30

5.3 AC Characteristics .....................................34

6.0 EXTENDED OPERATING CONDITIONS......44

6.1 Applying V

CC

Voltages...............................44

6.2 DC Characteristics.....................................45

6.3 AC Characteristics .....................................51

APENDIX A: Additional Information.................56

APPENDIX B: Additional Information...............57

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

4

PRELIMINARY

REVISION HISTORY

Number Description

-001 Initial release of datasheet.

-002 Status changed from Product Preview to Preliminary
28F400CV/CE/BE references and information added throughout.

2.7V CE/BE specs added throughout.

The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,

3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying V

CC

Voltages.” These sections completely

changed to clarify V

CC

ramp requirements.

I

PPD

3.3V Commercial spec changed from 10 to 5 µA.
Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component

values in table. (Component values also rounded off).

t

ELFL

, t

ELFH

, t

AVFL

changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V

TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial.

t

WHAX

and t

EHAX

changed from 10 to 0 ns.

t

PHWL

changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial.

t

PHEL

changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial.

-003 28F400BE row removed from Table 1
Applying V

CC

voltages (Sections 5.1 and 6.1) rewritten for clarity.

Minor cosmetic changes/edits.

-004 Corrections: Spec typographical error “t

QWL

” corrected to read “t

QVVL

.”
Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU
specs require less glue logic.
Spec t

ELFL

and t

ELFH

changed from 5 ns (max) to 0 ns (min).

New specs t

PLPH

and t

PLQX

added from Specification Update document (297595).

Specs t

EHQZ

and t

GHQZ

improved on most voltage/speed combinations.

-005 Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80
to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80.
Updated disclaimer.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

5

PRELIMINARY

1.0 PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for the
two branches of products in the SmartVoltage
4-Mbit boot block flash mem ory f amily : t he -BE /CE
suffix products f eature a low V

CC

operating range

of 2.7V–3.6V; the -BV/CV suffix products offer

3.0V–3.6V operation. Both BE/CE and BV/CV
products also operate at 5V for high-s peed acces s
times. Throughout this datasheet, the 28F400
refers to all x8/x16 4-Mbit products, while
28F004B refers to all x8 4-Mbit boot block
products. Also, t he term “2.7V” generally refers to
the full voltage range 2.7V–3.6V. Section 1
provides an overview of the flash mem ory family
including applications, pinouts and pin
descriptions. Sections 2 and 3 describe the
memory organization and operation for these
products. Finally, Sections 4 and 5 contain the
family’s operating specifications.

1.1 New Features in the
SmartVoltage Products

The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12V
program products, except for the dif ferences lis ted
below. All other functions are equivalent t o current
products, including signatures, write commands,
and pinouts.

• WP# pin has replaced a DU (Don’t Use) pin.

Connect the WP# pin to control signal or to
V

CC

or GND (in this case, a logic -level signal
can be placed on DU pin). See Tables 2 and
9 to see how the WP# pin works.

• 5V program/erase operation has been added.
If switching V

PP

for write protection, swi tch to
GND (not 5V) for complete write prot ect ion. To
take advantage of 5V write-capability , allow for
connecting 5V to V

PP

and disconnecting 12V

from V

PP

line.

• Enhanced circuits optimize low V

CC

performance, allowing operation down to
V

CC

= 2.7V (using the BE product).

If you are using BX/BL 12V V

PP

boot block
products today, you should account for the
differences listed above and also allow for
connecting 5V to V

PP

and disconnecting 12V from

V

PP

line, if 5V writes are desired.

1.2 Main Features

Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete volt age s upply pi ns: V

CC

for

read operation, and V

PP

for program and erase
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. The 28F400BV/CV, 28F004BV,
28F400CE and 28F004BE provide program/eras e
capability at 5V or 12V. The 28F400BV/CV and
28F004BV allow reads with V

CC

at 3.3 ± 0.3V or
5V, while the 28F400CE and 28F004BE allow
reads with V

CC

at 2.7V–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, read operation using the

2.7V or 3.3V ranges can provide great power
savings. If read performance is an issue, however,
5V V

CC

provides faster read access times.

Table 1. SmartVoltage Provides Total Voltage Flexibility

Product Bus V

CC

V

PP

Name Width 2.7V–3.6V 3.3 ± 0.3V 5V ± 5%

5V ± 10%

5V ± 10% 12V ± 5%

28F004BV-T/B x8 √√√√
28F400BV-T/B x8 or x16 √√√√
28F400CV-T/B x8 or x16 √√√√
28F004BE-T/B x8 √√√√
28F400CE-T/B x8 or x16 √√√√

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

6

PRELIMINARY

For program and erase operations, 5V V

PP

operation eliminates the need for i n system voltage
converters, while 12V V

PP

operation provides faster
program and erase for situations where 12V is
available, such as manuf acturing or designs where
12V is in-system. For design simplicity, however,
just hook up V

CC

and VPP to the same 5V ± 10%

source.
The 28F400/28F004B boot block flash memory

family is a high-performanc e, 4-Mbit (4,194,304 bit)
flash memory family organized as either
256 Kwords of 16 bits each (28F400 only) or
512 Kbytes of 8 bits each (28F400 and 28F004B).

Separately erasable blocks, including a hardware­lockable boot block (16,384 by tes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes), define the boot block flash family
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently eras ed and
programmed 100,000 times at commercial
temperature or 10,000 times at extended
temperature.

The boot block is located at either the top (denot ed
by -T suffix) or the bottom (-B suff ix) of the addres s
map in order to accommodate different
microprocessor protocols for boot code location.
The hardware-lockable boot block provides
complete code security for the k ernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).

The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automati cally exec utes
the algorithms and timings necessary for program
and erase operations, including verifications,
thereby unburdening the microprocessor or
microcontroller of these tasks. The Status Register
(SR) indicates the status of the WSM and whether i t
successfully completed the desired program or
erase operation.

Program and Erase Automation al l ows program and
erase operations to be executed using an indust ry­standard two-write command sequence t o the CUI.
Data writes are performed in word (28F400 family)
or byte (28F400 or 28F004B families) increment s.

Each byte or word in the flash memory can be
programmed independently of other memory
locations, unlike erases, which erase all locations
within a block simultaneously.

The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off.
This mode is controlled by the RP# pin and its
usage is discussed in Sec tion 3.5, along with other
power consumption issues.

Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically default s to the read array mode, but
during a warm system reset, where power
continues uninterrupted to the system components,
the flash memory could rem ain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the mem ory to
normal read mode upon activation of the Reset
signal. See Section 3.6.

The 28F400 provides both byte-wide or word-wide
input/output, which is controll ed by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ

15/A–1

pin.

The 28F400 products are available in a
ROM/EPROM-compatible pinout and hous ed in the
44-lead PSOP (Plastic Small Outline) pack age, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F004
products are available in the 40-lead TSOP
package as shown in Figure 3.

Refer to the DC Characteristics Table, Section 5.2
(commercial temperature) and Section 6.2
(extended temperature), for complete current and
voltage specifications. Refer to the AC
Characteristics Table, Section 5.3 (commercial
temperature) and Section 6.3 (extended
temperature), for read, write and erase performance
specifications.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

7

PRELIMINARY

1.3 Applications

The 4-Mbit boot block flash memory family
combines high-density, low-power, high­performance, cost-effective flash memories with
blocking and hardware protection capabilit ies. Their
flexibility and versatility reduce c ost s throughout t he
product life cycle. Flash memory is ideal for Just-In­Time production flow, reducing system inventory
and costs, and eliminating component handling
during the production phase.

When your product is in the end-user’s hands, and
updates or feature enhancements become
necessary, flash m emory reduces t he update cost s
by allowing user-performed code changes instead
of costly product returns or technician calls.

The 4-Mbit boot block flas h memory f ami ly prov ides
full-function, block ed flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, di gital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.

Reprogrammable systems, such as personal
computers, are ideal applications for the 4-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard
in desktop and portable PCs enables auto­configuration of ISA and PCI add-in cards.
However, since the “plug and play” specification
continues to evolve, a flash BIOS provides a cost­effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.

The 4-Mbit flash memory products are also
excellent design solutions for di gital cellular phone
and telecommunication switching applications
requiring very low power consumption, high­performance, high-density storage capability,
modular software designs, and a small form factor
package. The 4-Mbit’s bloc king scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four
main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).

Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a singl e flash dev ice. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in plac e, decreasing RAM
requirements.

1.4 Pinouts

Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every pac kage pinout to
the 8-Mbit density. The 28F004B 40-lead TSOP
pinout for space-constrained designs is shown in
Figure 3. The 28F400 44-lead PSOP pinout f ollows
the industry-standard ROM/EPROM pinout, as
shown in Figure 4. For designs that require x16
operation but have space concerns, refer to the
48-lead pinout in Figure 5. Furtherm ore, the 28F400
56-lead TSOP pinout shown in Figure 6 provides
density upgrades to future higher dens it y boot bloc k
memories.

Pinouts for the corresponding 2-Mbit and 8-Mbit
components are also provided for convenient
reference. 4-Mbit pinouts are given on the chip
illustration in the center, with 2-Mbit and 8-Mbit
pinouts going outward from the center.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

8

PRELIMINARY

A[18:1]

CS#

RD#

WR#

D[0:15]

A[0:17]

CE#

OE#

WE#

DQ[0:15]

28F400BV-60

RP#

i386™ EX CPU

(25 MHz)

RESET

RESET

0530_01

NOTE:

A data bus buffer may be needed for processor speeds above 25 MHz.

Figure 1. 28F400 Interface to Intel386™ EX Microprocessor

UCS#

80C188EB

-A15A

8

ALE

P1.X

WR#

RD#

RESIN#

System Reset

WE#
OE#

V

PP

ADDRESS

LATCHES

LE

ADDRESS

LATCHES

LE

CE#

A

0-A18

RP#

28F004-T

-AD

7AD0

A[16:18]

DQ

0

-DQ

7

WP#

V

CC

10K

Ω

P1.X

V

CC

0530_02

Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

9

PRELIMINARY

28F004B

Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

32
31
30
29
28
27
26
25
24
23
22
21

33

34

35

36

37

38

39

40

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

A

1

A

2

A

3

RP#

WE#

V

PP

A

16

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

WP#

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

DQ

3

A

17

GND

NC

A

10

NC

NC

NC

28F002B 28F002B

28F008B 28F008B

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

V

CC

DQ

3

A

17

GND

NC

A

10

NC

A

1

A

2

A

3

RP#

WE#

V

PP

A

16

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

WP#

A

1

A

2

A

3

RP#

WE#

V

PP

A

16

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

WP#

A

18

A

18

A

19

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

DQ

3

A

17

GND

NC

A

10

NC

NC

V

CC

V

CC

0530_03

Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications

PA28F400

Boot Block

44-Lead PSOP

0.525" x 1.110"

TOP VIEW

32
31
30
29
28
27
26
25
24
23

33

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

RP#
WE#

A

A

A

A
A

A

A

A
A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

8
9
10
11
12
13
14
15
16

15
7
14
6
13
5
12
4

CC

-1

28F800 28F200

V

PP

WP#

NC
A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

V

PP

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

A

18

V

PP

WP#

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

RP#
WE#

A

A

A

A
A

A

A

A
A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

8
9
10
11
12
13
14
15
16

15
7
14
6
13
5
12
4

CC

-1

RP#
WE#

A

A

A

A
A

A

A

A
A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

8
9
10
11
12
13
14
15
16

15
7
14
6
13
5
12
4

CC

-1

28F80028F200

0530_04

NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A18 on the 8-Mbit because no other pins were available for the high order
address. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH (12V). To allow upgrades to
the 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A18 at the 8-Mbit density. See
Section 3.4 for details.

Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

10

PRELIMINARY

28F400

Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

25

26

27

28

29

30

31

32

16

15 -1
7
14
6
13

5
12

4

A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

V
DQ

DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A

CC

11
3
10

2
9
1
8

0

0

16

15 -1
7
14
6
13

5
12

4

A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

V
DQ

DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A

CC

11
3
10

2
9
1
8

0

0

28F80028F200

16

15 -1

7
14
6
13

5
12

4

A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A

V

CC

11
3
10

2
9
1
8
0

0

28F20028F800

A
A
A

A

A
A
A
A

NC

NC

WE#

RP#

WP#

NC
A

A
A
A
A
A
A
A

17

7
6
5
4
3
2
1

15
14
13
12
11
10
9
8

A
A
A

A

A
A
A
A

NC

NC

WE#

RP#

WP#

NC

NC
A

A
A
A
A
A
A

7
6
5
4
3
2
1

15
14
13
12
11
10
9
8

A
A
A

A

A
A
A
A

NC

NC

WE#

RP#

WP#

NC

NC
A
A
A
A
A
A
A
A

17
7
6
5
4
3
2
1

15
14
13
12
11
10
9
8

V

PPVPPVPP

A

18

NC

0530_05

Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

28F400

56-Lead TSOP

Boot Block

14 mm x 20 mm

TOP VIEW

28

27

26

25

24

23

22

21

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

A

1

A

2

A

3

RP#

WE#

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

NC

V

PP

NC

NC

NC

NC

NC

NC

A

10

WP#

NC

NC

A

1

A

2

A

3

RP#

WE#

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

NC

V

PP

NC

NC

NC

NC

NC

NC

A

10

WP#

NC

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

V

CC

DQ

3

GND

NC

NC

DQ

9

DQ

10

DQ

11

DQ

8

BYTE#

DQ15/A

-1

DQ

14

DQ

13

DQ

12

A

16

NC

28F200 28F200

A

17

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

32
31

30
29

33

34

35

36

37

38

39

40

DQ

7

CE#

OE#

GND
A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

V

CC

DQ

3

GND

NC

NC

DQ

9

DQ

10

DQ

11

DQ

8

BYTE#

DQ15/A

-1

DQ

14

DQ

13

DQ

12

A

16

NC

0530_06

Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

11

PRELIMINARY

1.5 Pin Descriptions

Table 2. 28F400/004 Pin Descriptions

Symbol Type Name and Function

A0–A

18

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F400 only has A

– A

pins, while the 28F004B

has A

0

– A18.

A

9

INPUT ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During

this mode, A

0

decodes between the manufacturer and device IDs. When BYTE#

is at a logic low, only the lower byte of the signatures are read. DQ

15/A–1

is a

don’t care in the signature mode when BYTE# is low.

DQ0–DQ

7

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and Status Register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.

DQ8–DQ

15

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ

15/A–1

becomes the lowest order address for data output on DQ0–DQ7.

The 28F004B does not include these DQ

8

–DQ

15

pins.

CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during

a read cycle. OE# is active low.

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks.

WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.

RP# INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to

control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.

When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at V

HH

, the boot block is unlocked and can be programmed or

erased. This overrides any control from the WP# input.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

12

PRELIMINARY

Table 2. 28F400/004 Pin Descriptions (Continued)

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Provides a method for unlocking the boot block in a system

without a 12V supply.
When WP# is at logic low, the boot block is locked, preventing program and

erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to indicate the operation
failed.

When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is at
V

HH

. See Section 3.4 for details on write protection.

BYTE# INPUT BYTE# ENABLE: Not available on 28F004B. Controls whether the device

operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.

When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ

0

–DQ7 and DQ15/A–1 becomes the lowest order

address that decodes between the upper and lower byte. DQ

8

–DQ14 are tri-stated

during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is

read and programmed on DQ

0

–DQ15.

V

CC

DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3 ± 0.3V, 2.7V–3.6V (BE/CE only)

V

PP

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must
be applied to this pin. When V

PP

< V

PPL

K

all blocks are locked and protected

against Program and Erase commands.
GND GROUND: For all internal circuitry.
NC NO CONNECT: Pin may be driven or left floating.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

2.0 PRODUCT DESCRIPTION

2.1 Memory Blocking Organization

This product family features an asymmetrically­blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 tim es for
commercial temperature or up to 10,000 tim es for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolat i l e storage. The combination
of block sizes in t he boot block architecture allow
the integration of several memories into a single
chip. For the address locations of t he blocks, see
the memory maps in Figures 4 and 5.

2.1.1 ONE 16-KB BOOT BLOCK

The boot block is intended to repl ace a dedicated
boot PROM in a microprocess or or microcontroller­based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address m ap
to accommodate different microproces sor protocols
for boot code location. This boot block features
hardware controllable write-protection to protec t the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combinati on of the V

PP

, RP#, and

WP# pins, as is detailed in Section 3.4.

2.1.2 TWO 8-KB PARAMETER BLOCKS

The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the by te­rewrite functionality of EEPROMs can be emulated.

These techniques are detailed in Intel ’s application
note,

AP-604 Using Intel’s Boot Block Flash

Memory Parameter Blocks to Replace EEPROM

.
Each boot block component c ontains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.

2.1.3 ONE 96-KB + THREE 128-KB

MAIN BLOCKS

After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 4-Mbit
device contains one 96-Kbyte (98,304 byte) block
and three 128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more information.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

14

PRELIMINARY

3FFFFH
3E000H

3DFFFH

3D000H

3CFFFH

3C000H

3BFFFH

30000H

20000H

1FFFFH

10000H

0FFFFH

00000H

2FFFFH

3FFFFH

30000H

2FFFFH

20000H

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

28F400-T

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

28F400-B

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

0530_07

NOTE: Address = A[17:0]. In x8 operation, the least significant system address should be connected to A-1. Memory maps are
shown for x16 operation.

Figure 7. Word-Wide x16-Mode Memory Maps

7FFFFH

7C000H

7BFFFH

7A000H

79FFFH

78000H

77FFFH

60000H

5FFFFH

40000H

3FFFFH

20000H

1FFFFH

00000H

28F004-T

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

7FFFFH

60000H

5FFFFH

40000H

3FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

28F004-B

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

0530_08

NOTE: Address = A[18:0]. These memory maps apply to the 28F004B or the 28F400 in x8 mode.

Figure 8. Byte-Wide x8-Mode Memory Maps

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

15

PRELIMINARY

3.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION

Flash memory combines E PROM functionality with
in-circuit electrical wri te and erase. The boot block
flash family utilizes a Command User Interface
(CUI) and automated algorithms to simplify write
and erase operations. The CUI allows for 100%
TTL-level control inputs, fixed power supplies
during erasure and programming, and maximum
EPROM compatibility.

When V

PP

< V

PPLK

, the device will only successfully
execute the following commands: Read Array,
Read Status Register, Clear Status Register and
intelligent identifier mode. The device provides
standard EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data c an be acc ess ed through t he CUI
or through the standard EPROM A

9

high voltage

access (V

ID

) for PROM programming equipment.

The same EPROM read, standby and output
disable functions are avai lable when 5V or 12V is
applied to the V

PP

pin. In addition, 5V or 12V on

V

PP

allows write and erase of the device. All
functions associ ated wit h alt ering mem ory c ontent s:
Program and Erase, Intelligent Identifier Read, and
Read Status are accessed via the CUI.

The internal Write State Machi ne (WSM) completely
automates program and erase, beginning operation
signaled by the CUI and reporting status through
the Status Register. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.

3.1 Bus Operations

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles. These bus operations are summarized in
Tables 3 and 4.

3.2 Read Operations

3.2.1 READ ARRAY

When RP# transitions from V

IL

(reset) to VIH, the
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.

When the device is in the read array mode, five
control signals must be cont rolled to obtain data at
the outputs.

• RP# must be logic high (V

IH

)

• WE# must be logic high (V

IH

)

• BYTE# must be logic high or logic low

• CE# must be logic low (V

IL

)

• OE must be logic low (V

IL

)

In addition, the address of the desired l ocat ion mus t
be applied to the address pins. Refer to Figures 15
and 16 for the exact sequence and timing of these
signals.

If the device is not i n read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to t he
CUI before reads can take place.

During system design, consideration should be
taken to ensure address and control inputs meet
required input slew rates of <10 ns as defined in
Figures 12 and 13.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

16

PRELIMINARY

Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE# OE# WE# A

9

A

0

V

PP

DQ

0–15

Read 1,2,3 V

IH

V

IL

V

IL

V

IH

XXX D

OUT

Output Disable V

IH

V

IL

V

IH

V

IH

X X X High Z

Standby V

IH

V

IH

XXXXXHigh Z

Deep Power-Down 9 V

IL

XXXXXXHigh Z

Intelligent Identifier
(Mfr)

4VIHV

IL

V

IL

V

IH

V

ID

V

IL

X 0089 H

Intelligent Identifier
(Device)

4,5 V

IH

V

IL

V

IL

V

IH

V

ID

V

IH

X See

Table 5

Write 6,7,8 V

IH

V

IL

V

IH

V

IL

XXX D

IN

Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE# OE# WE# A

9

A0A

–1

V

PP

DQ

0–7

DQ

8–14

Read 1,2,3 V

IH

V

IL

V

IL

V

IH

XXXXD

OUT

High Z

Output
Disable

V

IH

V

IL

V

IH

V

IH

XXXXHigh Z High Z

Standby V

IH

V

IH

XXXXXXHigh Z High Z

Deep Power­Down

9VILXXXXXXXHigh Z High Z

Intelligent
Identifier (Mfr)

4VIHV

IL

V

IL

V

IH

V

ID

V

IL

X X 89H High Z

Intelligent
Identifier
(Device)

4,5 V

IH

V

IL

V

IL

V

IH

V

ID

V

IH

X X See

Table

5

High Z

Write 6,7,8 V

IH

V

IL

V

IH

V

IL

XXXXDINHigh Z

NOTES:

1. Refer to DC Characteristics.

2. X can be V

IL

, VIH for control pins and addresses, V

PPLK

or V

PPH

for VPP.

3. See DC Characteristics for V

PPLK

, V

PPH1

, V

PPH2

, VHH, VID voltages.

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A

1–A17

= X, A1–A18 = X.

5. See Table 5 for device IDs.

6. Refer to Table 7 for valid D

IN

during a write operation.

7. Command writes for block erase or word/byte program are only executed when V

PP

= V

PPH1

or V

PPH2

.

8. To write or erase the boot block, hold RP# at V

HH

or WP# at VIH. See Section 3.4.

9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

17

PRELIMINARY

3.2.2 INTELLIGENT IDENTIFIERS

To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the intelligent identifier command (90H) or
by taking the A

9

pin to VID. Once in intelligent

identifier read mode, A

0

= 0 outputs the manu-

facturer’s identifi cation code and A

0

= 1 outputs the
device code. In byte-wi de m ode, onl y the lower byt e
of the above signatures is read (DQ

15/A–1

is a

“don’t care” in this mode). S ee Table 5 for product
signatures. To return to read array mode, write a
Read Array command (FFH).

Table 5. Intelligent Identifier Table

Product Mfr. ID Device ID

-T

(Top Boot)-B(Bottom Boot)

28F400 0089 H 4470 H 4471 H
28F004 89 H 78 H 79 H

3.3 Write Operations

3.3.1 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) is t he interface
between the microprocessor and the internal chip
controller. Commands are writ ten to the CUI using
standard microprocessor write timings. The
available commands are Read Array, Read
Intelligent Identifier, Read Status Register, Clear
Status Register, Erase and Program (summarized
in Tables 6 and 7). The three read modes are read
array, intelligent identi fier read, and status register
read. For Program or Erase commands, the CUI
informs the Write State Machine (WS M) that a write
or erase has been requested. During the ex ecution
of a Program command, the WSM will control the
programming sequences and the CUI will only
respond to status reads. Duri ng an erase cycle, the
CUI will respond to status reads and erase
suspend. After the WSM has completed its task , it
will set the WSM Status bit to a “1” (ready), which
indicates that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will s tay in the
current command state until it receives another
command.

3.3.1.1 Command Function Description

Device operations are selected by writing specific
commands into the CUI. Tabl es 6 and 7 define the
available commands.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

18

PRELIMINARY

Table 6. Command Codes and Descriptions

Code Device Mode Decription

00 Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine
these codes for future functions.

FF Read Array Places the device in read array mode, so that array data will be output on the data

pins.

40 Program

Set-Up

Sets the CUI into a state such that the next write will latch the Address and Data
registers on the rising edge and begin the program algorithm. The device then
defaults to the read status mode, where the device outputs Status Register data
when OE# is enabled. To read the array, issue a Read Array command.

To cancel a program operation after issuing a Program Set-Up command, write all

1’s (FFH for x8, FFFFH for x16)

to the CUI. This will return to read status register
mode after a standard program time without modifying array contents. If a program
operation has already been initiated to the WSM this command can not cancel that
operation in progress.

10 Alternate

Prog Set-Up

(See 40H/Program Set-Up)

20 Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an
Erase Confirm command, then the CUI will set both the Program Status (SR.4) and
Erase Status (SR.5) bits of the Status Register to a “1,” place the device into the
read Status Register state, and wait for another command without modifying array
contents. This can be used to cancel an erase operation after the Erase Setup
command has been issued. If an operation has already been initiated to the WSM
this can not cancel that operation in progress.

D0 Erase

Resume/

Erase

Confirm

If the previous command was an Erase Set-Up command, then the CUI will latch
address and data, and begin erasing the block indicated on the address pins.
During erase, the device will respond only to the Read Status Register and Erase
Suspend commands and will output Status Register data when OE# is toggled low.
Status Register data is updated by toggling either OE# or CE# low.

B0 Erase

Suspend

Valid only while an erase operation is in progress and will be ignored in any other
circumstance. Issuing this command will begin to suspend erase operation. The
Status Register will indicate when the device reaches erase suspend mode. In this
mode, the CUI will respond only to the Read Array, Read Status Register, and
Erase Resume commands and the WSM will also set the WSM Status bit to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the
WSM and the remainder of the chip, if it is made active. During a suspend
operation, the data and address latches will remain closed, but the address pads
are able to drive the address into the read path. See Section 3.3.4.1.

70 Read Status

Register

Puts the device into the read Status Register mode, so that reading the device
outputs Status Register data, regardless of the address presented to the device.
The device automatically enters this mode after program or erase has completed.
This is one of the two commands that is executable while the WSM is operating.
See Section 3.3.2.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

Table 6. Command Codes and Descriptions (Continued)

Code Device Mode Decription

50 Clear Status

Register

The WSM can only set the Program Status and Erase Status bits in the Status
Register to “1;” it cannot clear them to “0.”

The Status Register operates in this fashion for two reasons. The first is to give the
host CPU the flexibility to read the status bits at any time. Second, when
programming a string of bytes, a single Status Register query after programming
the string may be more efficient, since it will return the accumulated error status of
the entire string. See Section 3.3.2.1.

90 Intelligent

Identifier

Puts the device into the intelligent identifier read mode, so that reading the device
will output the manufacturer and device codes. (A

= 0 for manufacturer,

A

0

= 1 for device, all other address inputs are ignored). See Section 3.2.2.

Table 7. Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Note Oper Addr Data Oper Addr Data

Read Array 8 Write X FFH
Intelligent Identifier 1 Write X 90H Read IA IID
Read Status Register 2,4 Write X 70H Read X SRD
Clear Status Register 3 Write X 50H
Word/Byte Program Write PA 40H Write PA PD
Alternate Word/Byte

Program

6,7 Write PA 10H Write PA PD

Block Erase/Confirm 6,7 Write BA 20H Write BA D0H
Erase Suspend 5 Write X B0H
Erase Resume Write X D0H

ADDRESS DATA

BA = Block Address SRD = Status Register Data
IA = Identifier Address IID = Identifier Data
PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Bus operations are defined in Tables 3 and 4.

2. IA = Identifier Address: A

0

= 0 for manufacturer code, A0 = 1 for device code.

3. SRD - Data read from Status Register.

4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
device codes.

5. BA = Address within the block being erased.

6. PA = Address to be programmed. PD = Data to be programmed at location PA.

7. Either 40H or 10H commands is valid.

8. When writing commands to the device, the upper data bus [DQ

8

–DQ15] = X (28F400 only) which is either VIL or VIH, to

minimize current draw.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

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PRELIMINARY

Table 8. Status Register Bit Definition

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

SR.7 =WRITE STATE MACHINE STATUS

1 = Ready (WSMS)
0 = Busy

Check Write State Machine bit first to determine
Word/Byte program or Block Erase completion,
before checking Program or Erase Status bits.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended
0 = Erase In Progress/Completed

When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to

“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure
0 = Successful Block Erase

When this bit is set to “1,” WSM has applied the
max number of erase pulses to the block and is
still unable to verify successful block erasure.

SR.4 = PROGRAM STATUS (DWS)

1 = Error in Byte/Word Program
0 = Successful Byte/Word Program

When this bit is set to “1,” WSM has attempted
but failed to program a byte or word.

SR.3 = VPP STATUS (VPPS)

1 = V

PP

Low Detect, Operation Abort

0 = V

PP

OK

The V

PP

Status bit does not provide continuous

indication of V

PP

level. The WSM interrogates V

PP

level only after the Byte Write or Erase command
sequences have been entered, and informs the
system if V

PP

has not been switched on. The V

PP

Status bit is not guaranteed to report accurate
feedback between V

PPLK

and V

PPH

.

SR.2-SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

These bits are reserved for future use and should
be masked out when polling the Status Register.

3.3.2 STATUS REGISTER

The device Status Register indicates when a
program or erase operation is complete, and the
success or failure of that operation. To read the
Status Register write the Read Status (70H)
command to the CUI. This causes all subsequent
read operations to output data from the Status
Register until another command is written to the
CUI. To return to reading from the array, issue a
Read Array (FFH) command.

The Status Register bits are output on DQ

0

–DQ7, in
both byte-wide (x8) or word-wide (x16) m ode. In the
word-wide mode the upper byte, DQ

8

–DQ15,
outputs 00H during a Read Status comm and. In the
byte-wide mode, DQ

8

–DQ14 are tri-stated and

DQ

15/A–1

retains the low order address function.

Important: The contents of the Status Register
are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. This

prevents possible bus errors which might occur if
Status Register cont ents change while being read.
CE# or OE# must be toggled wit h each subs equent
status read, or the Status Register will not indicate
completion of a program or erase operation.

When the WSM is active, the SR.7 register will
indicate the status of the WSM, and will also hold
the bits indicating whether or not the WSM was
successful in performing the desired operation.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

3.3.2.1 Clearing the Status Register

The WSM sets status bits 3 through 7 to “1,” and
clears bits 6 and 7 to “0,” but c annot clear status
bits 3 through 5 to “0.” Bits 3 through 5 can only be
cleared by the controlling CPU through t he use of
the Clear Status Register (50H) com mand, bec ause
these bits indicate various error conditions. By
allowing the system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes
or erasing multiple blocks in sequence) before
reading the Status Register t o determine if an error
occurred during that series. Clear the Status
Register before beginning another command or
sequence. Note, again, that a Read Array
command must be issued bef ore data can be read
from the memory or intelligent identifier.

3.3.3 PROGRAM MODE

Programming is executed using a two-write
sequence. The Program Setup command is writ ten
to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to:

1. Program the desired bits of the addressed

memory word or byte.

2. Verify that the desired bits are sufficiently

programmed.

Programming of the memory resul ts in spec ific bits
within a byte or word being changed to a “0.”

If the user attempts to program “1”s, there will be no
change of the memory cell content and no error
occurs.

The Status Register indic ates programming status:
while the program sequence is exec uting, bit 7 of
the Status Register is a “0.” The Status Register
can be polled by toggling either CE# or OE#. While
programming, the only valid command is Read
Status Register.

When programming is complete, the Program
Status bits should be c hecked. If the programming
operation was unsuccessful, bit 4 of the Status
Register is set to a “1” to indicate a Program
Failure. If bit 3 is set to a “1,” then V

PP

was not
within acceptable limits, and the WSM did not
execute the programming sequence.

The Status Register should be cleared before
attempting the next operati on. Any CUI instruction
can follow after programming is completed;
however, reads from the Memory Array or
Intelligent Identifier cannot be accomplished until
the CUI is given the appropriate command.

3.3.4 ERASE MODE

To erase a block, write the Eras e Set -Up and E rase
Confirm commands to the CUI, along with the
addresses identifying t he bloc k t o be erased. These
addresses are latched internally when the Erase
Confirm command is iss ued. Block erasure results
in all bits within the block being s et to “1.” Only one
block can be erased at a time.

The WSM will execute a sequence of internally
timed events to:

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are
sufficiently programmed to “0.”

3. Erase all bits within the block to “1.”

4. Verify that all bits within the block are
sufficiently erased.

While the erase sequence is executing, bit 7 of the
Status Register is a “0.”

When the Status Register indi cates that erasure is
complete, check t he Erase Status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, bit 5 of the Status
Register will be set to a “1,” indicating an Erase
Failure. If V

PP

was not within acceptable l imits af ter
the Erase Confirm command is issued, the WSM
will not execute an erase sequence; ins t ead, bit 5 of
the Status Register is set to a “1” to indicate an
Erase Failure, and bit 3 is set to a “1” to ident i f y that
V

PP

supply voltage was not within acceptable limits.

Clear the Status Register before attempting the
next operation. Any CUI ins truction can follow after
erasure is completed; however, reads from the
Memory Array, Status Register, or Intelligent
Identifier cannot be accomplished until the CUI is
given the Read Array command.

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PRELIMINARY

3.3.4.1 Suspending and Resuming Erase

Since an erase operation requires on the order of
seconds to complete, an Erase Suspend c ommand
is provided to allow erase-s equence interruption in
order to read data from another block of the
memory. Once the erase sequence is started,
writing the Erase Suspend command to the CUI
requests that the WSM paus e the erase sequence
at a predetermined point in the erase al gori thm. The
Status Register will indicate if/when the erase
operation has been suspended.

At this point, a Read Array com mand c an be writ ten
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register command.

During erase suspend mode, the chip c an go into a
pseudo-standby mode by taki ng CE# to V

IH

, which

reduces active current draw.
To resume the erase operation, enable the chip by

taking CE# to V

IL

, then issuing the Erase Res ume
command, which continues the erase s equence to
completion. As with the end of a standard erase
operation, the Status Register must be read,
cleared, and the next instruc tion issued in order t o
continue.

3.4 Boot Block Locking

The boot block family architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks. The truth table, Table 9, clearly defines the
write protection methods.

3.4.1 V

PP

= VIL FOR COMPLETE

PROTECTION

For complete write protection of all blocks in the
flash device, the V

PP

programming voltage can be

held low. When V

PP

is below V

PPLK

, any program or
erase operation will result in a error in the Status
Register.

3.4.2 WP# = V

IL

FOR BOOT BLOCK

LOCKING

When WP# = V

IL

, the boot block is loc ked and any
program or erase operation to the boot block will
result in an error in the Status Register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
when RP# = V

HH

.

3.4.3 RP# = V

HH

OR WP# = VIH FOR BOOT

BLOCK UNLOCKING

Two methods can be used to unlock the boot block:

1. WP# = V

IH

2. RP# = V

HH

If both or either of these t wo condit ions are met , the
boot block will be unlocked and can be
programmed or erased.

3.4.4 UPGRADE NOTE FOR 8-MBIT

44-PSOP PACKAGE

If upgradability to 8M is required, note that the
8-Mbit in the 44-PSOP does not have a WP#
because no pins were available for the 8-Mbit
upgrade address. Thus, in this density-package
combination only, V

HH

(12V) on RP# is required to
unlock the boot block. Unloc king with a logic-level
signal is not possible. If this functionality is
required, and 12V is not available, consider using
the 48-TSOP package, which has a WP# pin and
can be unlocked with a logic-lev el signal. All other
density-package combinations have WP# pins.

Table 9. Write Protection Truth Table

V

PP

RP# WP# Write Protection

Provided

V

IL

X X All Blocks Locked

≥ V

PPLKVIL

X All Blocks Locked

(Reset)

≥ V

PPLKVHH

X All Blocks Unlocked

≥ V

PPLKVIH

VILBoot Block Locked

≥ V

PPLKVIH

VIHAll Blocks Unlocked

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PRELIMINARY

SR.7 = 1

?

NO

YES

Start

Write 40H,

Word/Byte Address

Write Word/Byte

Data/Address

Full Status

Check if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

1

0

Read Status Register

Data (See Above)

1

0

Read

Status Register

VPP Range Error

Bus

Operation

Standby

Standby

Check SR.3
1 = V

PP

Low Detect

SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register command,
in cases where multiple bytes are programmed before full
status is checked.

If error is detected, clear the Status Register before attempt ing
retry or other error recovery.

Bus

Operation

Command Comments

Write

Write

Setup

Program

Data = Data to Program
Addr = Location to Program

Read

Data = 40H
Addr = Word/Byte to Program

Check SR.7
1 = WSM Ready
0 = WSM Busy

Repeat for subsequent word/byte program operations.
SR Full Status Check can be done after each word/byte program,
or after a sequence of word/byte programs.
Write FFH after the last program operation to reset device to
read array mode.

Standby

SR.3=

SR.4 =

Word/Byte Program

Error

Word/Byte Program

Successful

Check SR.4
1 = Word/Byte Program Error

Program

Status Register Data
Toggle CE# or OE#
to Update SRD.

Command Comments

0530_09

Figure 9. Automated Word/Byte Programming Flowchart

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PRELIMINARY

SR.7 =

0

1

Start

Write 20H,

Block Address

Write D0H and
Block Address

Full Status

Check if Desired

Block Eras e

Complete

FULL STATUS CHECK PROCEDURE

1

0

Read Status Register

Data (See Above)

1

0

Read Status

Register

VPP Range Error

Suspend

Erase

Suspend Erase

Loop

YES

NO

1

0

Command Sequence

Error

SR.3 =

SR.5 =

SR.4,5 =

Block Erase Error

Bus

Operation

Command Comments

Standby

Check SR.4,5
Both 1 = Command Sequ ence Error

Standby

Check SR.3
1 = V

PP

Low Detect

SR.3 MUST be cleared, if set d uring an erase attempt, before further
attempts are allowed by the Write State Machine.

SR.5 is only cleared by th e Cl ear Status Register Command, in
cases where multiple blocks are erase before full status is checked.

If error is detected, clear the Status Registe r before attempting
retry or other error recovery.

Check SR.5
1 = Block Erase Error

Standby

Bus

Operation

Command

Comments

Write

Write

Erase Setup

Read

Data = 20H
Addr = Within Block to Be Erased

Check SR.7
1 = WSM Ready
0 = WSM Busy

Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the la st operation to reset device to read array mode.

Status Register Data Toggle CE#
or OE# to Update Status Register

Standby

Erase

Confirm

Data = D0H
Addr = Within Block to Be Erased

Block Erase Successful

0530_10

Figure 10. Automated Block Erase Flowchart

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PRELIMINARY

SR.7 =

0

1

Start

Write B0H

Read

Status Register

Write D0H

Erase Resumed

Bus

Operation

Command Comments

Write

Erase

Suspend

Read

Data = B0H
Addr = X

Check SR.7
1 = WSM Ready
0 = WSM Busy

Status Register Data Toggle CE#
or OE# to Update SRD
Addr = X

Standby

CSR.6 =

Write FFH

Read Array Data

Done

Reading

Erase Completed

Write F F H

Read Array Data

YES

NO

0

1

Check SR.6
1 = Erase Suspended
0 = Erase Completed

Standby

Data = FFH
Addr = X

Write

Read array data from block other
than the one being erased.

Read

Data = D0H
Addr = X

Write

Read Array

Erase Resume

0530_11

Figure 11. Erase Suspend/Resume Flowchart

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PRELIMINARY

3.5 Power Consumption

3.5.1 ACTIVE POWER

With CE# at a logic-low level and RP# at a logic­high level, the device is placed in the active mode.
Refer to the DC Characterist ics t able for I

CC

current

values.

3.5.2 AUTOMATIC POWER SAVINGS (APS)

Automatic Power Savings (APS) provides low­power operation during active mode. Power
Reduction Control (PRC) circuit ry allows the dev ice
to put itself into a low c urrent state when not bei ng
accessed. After data is read from the memory

array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical I

CC

current is less than 1 mA. The device
stays in this static state with outputs valid until a
new location is read.

3.5.3 STANDBY POWER

With CE# at a logic-high level (V

IH

), and the CUI in
read mode, the memory is plac ed in st andby m ode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ

0

–DQ15 or DQ0–DQ7) are placed in a high­impedance state independent of the status of the
OE# signal. When CE# is at logic-high level duri ng
erase or program operations, the device will
continue to perform the operation and consume
corresponding active power until the operation is
completed.

3.5.4 DEEP POWER-DOWN MODE

The SmartVoltage boot block family s upports a low
typical I

CC

in deep power-down mode, which turns
off all circuits to s ave power. This m ode is ac tiv ated
by the RP# pin when it is at a logic-low
(GND ± 0.2V). Note: BYTE# pin must be at CMOS
levels to meet the I

CCD

specification.

During read modes, the RP# pin going low de­selects the memory and pl aces the out put driv ers in
a high impedance state. Recovery from the deep
power-down state, requires a mi nimum access ti me
of t

PHQV

(see AC Characteristics table).

During erase or program modes, RP# low will abort
either erase or program operations, but the memory
contents are no longer valid as t he data has been
corrupted by the RP# functi on. As i n the read mode
above, all internal circui try is turned off to achieve
the power savings.

RP# transitions to V

IL

, or turning power off to the

device will clear the Status Register.

3.6 Power-Up/Down Operation

The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, s inc e the
device is indifferent as to which power supply , V

PP

or VCC, powers-up first. The CUI is reset to t he read
mode after power-up, but the system must drop
CE# low or present a new address to ens ure valid
data at the outputs.

A system designer must guard against spurious
writes when V

CC

voltages are above V

LKO

and V

PP

is active. Since both WE# and CE# mus t be low for
a command write, driving either signal to V

IH

will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled unt il RP# is brought to
V

IH

, regardless of the stat e of its c ontrol inputs. By
holding the device in reset (RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.

3.6.1 RP# CONNECTED TO SYSTEM

RESET

The use of RP# during system reset is important
with automated write/erase devices because the
system expects to read from the flash memory
when it comes out of res et. If a CPU reset occ urs
without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may be providing status information
instead of array data. Int el’s Flash memories all ow
proper CPU initialization following a system reset
by connecting the RP# pin to the same RESET#
signal that resets the system CPU.

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PRELIMINARY

3.6.2 VCC, VPP AND RP# TRANSITIONS

The CUI latches commands as issued by system
software and is not altered by V

PP

or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode,
or after V

CC

transitions above V

LKO

(Lockout

voltage), is read array mode.
After any word/byte writ e or bl ock erase operation is

complete and even after V

PP

transitions down to

V

PPLK

, the CUI must be reset to read array mode
via the Read Array command if accesses to the
flash memory are desired.

Please refer to Intel’s application note

AP-617

Additional Flash Data Protection Using V

PP

, RP#,

and WP#,

for a circuit-level discription of how to

implement the protection discussed in Section 3.6.

3.7 Power Supply Decoupling

Flash memory’s power switching characteristics
require careful device decoupling methods. System
designers should consider three supply current
issues:

1. Standby current levels (I

CCS

)

2. Active current levels (I

CCR

)

3. Transient peaks produced by falling and rising

edges of CE#.

Transient current magnitudes depend on t he devi ce
outputs’ capacitiv e and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between eac h V

CC

and GND,

and between its V

PP

and GND. These high­frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.

3.7.1 V

PP

TRACE ON PRINTED CIRCUIT

BOARDS

Designing for in-system writes to the flash memory
requires special consideration of the V

PP

power
supply trace by the printed c ircuit board designer.
The V

PP

pin supplies the flash mem ory cel ls c urrent
for programming and erasing. One should use
similar trace widths and l ayout considerat ions given
to the V

CC

power supply trace. Adequate V

PP

supply traces, and decoupling capacitors placed
adjacent to the component, will decrease spikes
and overshoots.

NOTE:

Table headings in Sections 5 and 6 (i.e., BV-60, BV-80, BV-120, TBV-80, TBE-120) refer to the
specific products listed below. See Appendix A for more information on product naming and line items.

Abbreviation Applicable Product Names

BV-60 E28F004BV-T60, E28F004BV-B60, PA28F400BV-T60, PA28F400BV-B60,

E28F400CV-T60, E28F400CV-B60, E28F400BV-T60, E28F400BV-B60

BV-80 E28F004BV-T80, E28F004BV-B80, PA28F400BV-T80, PA28F400BV-B80,

E28F400CV-T80, E28F400CV-B80, E28F400BV-T80, E28F400BV-B80
BV-120 E28F004BV-T120, E28F004BV-B120, PA28F400BV-T120, PA28F400BV-B120
TBV-80 TE28F004BV-T80, TE28F004BV-B80, TB28F400BV-T80, TB28F400BV-B80,

TE28F400CV-T80, TE28F400CV-B80, TE28F400BV-T80, TE28F400BV-B80

TBE-120 TE28F004BE-T120, TE28F004BE-B120, TE28F400CE-T120, TE28F400CE-B120

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

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4.0 ABSOLUTE MAXIMUM
RATINGS*

Commercial Operating Temperature

During Read.................................0°C to +70°C

During Block Erase

and Word/Byte Program...............0°C to +70°C

Temperature Bias.....................–10°C to +80°C

Extended Operating Temperature

During Read.............................–40°C to +85°C

During Block Erase

and Word/Byte Program...........–40°C to +85°C

Temperature Under Bias..........–40°C to +85°C

Storage Temperature....................–65°C to +125°C

Voltage on Any Pin

(except V

CC

, VPP, A9 and RP#)

with Respect to GND..............–2.0V to +7.0V

(2)

Voltage on Pin RP# or Pin A

9

with Respect to GND......... –2.0V to +13.5V

(2,3)

VPP Program Voltage with Respect

to GND during Block Erase

and Word/Byte Program.... –2.0V to +14.0V

(2,3)

VCC Supply Voltage

with Respect to GND..............–2.0V to +7.0V

(2)

Output Short Circuit Current...................100 mA

(4)

NOTICE: This datasheet contains preliminary information on
new products in production. Do not finalize a design with
this information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.

* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.

NOTES:

1. Operating temperature is for commercial product
defined by this specification.

2. Minimum DC voltage is –0.5V on input/output pins.

During transitions, this level may undershoot to –2.0V
for periods
<20 ns. Maximum DC voltage on input/output pins is
V

CC

+ 0.5V which, during transitions, may overshoot to

V

CC

+ 2.0V for periods <20 ns.

3. Maximum DC voltage on V

PP

may overshoot to +14.0V

for periods <20 ns. Maximum DC voltage on RP# or A

9

may overshoot to 13.5V for periods <20 ns.

4. Output shorted for no more than one second. No more
than one output shorted at a time.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

5.0 COMMERCIAL OPERATING CONDITIONS

Table 10. Commercial Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Units

T

A

Operating Temperature 0 +70 °C

V

CC

3.3V VCC Supply Voltage (± 0.3V) 3.0 3.6 Volts
5V VCC Supply Voltage (10%) 1 4.50 5.50 Volts
5V VCC Supply Voltage (5%) 2 4.75 5.25 Volts

NOTES:

1. 10% V

CC

specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration.

2. 5% V

CC

specifications apply to the 60 ns version in its high-speed test configuration.

5.1 Applying VCC Voltages

When applying VCC voltage to the device, a delay
may be required before initiating device operat ion,
depending on the V

CC

ramp rate. If VCC ramps

slower than 1V/100 µs (0.01 V/µs) t hen no delay is

required. If V

CC

ramps faster than 1V/100 µs (0.01
V/µs), then a delay of 2 µs is required before
initiating device operation. RP# = GND is
recommended during power-up to protect against
spurious write signals when V

CC

is between V

LKO

and V

CCMIN

.

VCC Ramp Rate Required Timing

≤ 1V/100 µs No delay required.
> 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read

operations, command writes, program operations, and erase operations. This delay

is

measured beginning from the time V

CC

reaches V

CCMIN

(3.0V for 3.3 ± 0.3V operation;

and 4.5V for 5V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3V and 5V operation, the system should first transition V

CC

from the existing voltage range to GND,

and then to the new voltage. Any time the V

CC

supply drops below V

CCMIN

, the chip may be reset, aborting any operations

pending or in progress.

3. These guidelines must be followed for any V

CC

transition from GND.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

30

PRELIMINARY

5.2 DC Characteristics

Table 11. DC Characteristics (Commercial)

Prod

BV-60

BV-80

BV-120

Sym Parameter V

CC

3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Note Typ Max Typ Max

I

IL

Input Load Current 1 ± 1.0 ± 1.0 µA

V

CC

= V

CC

Max

V

IN

= VCC or GND

I

LO

Output Leakage Current 1 ± 10 ± 10 µA

V

CC

= V

CC

Max

V

IN

= VCC or GND

I

CCS

V

CC

Standby Current 1,3 0.4 1.5 0.8 2.0 mA

V

CC

= V

CC

Max

CE# = RP# = BYTE# =

WP# = V

IH

60 110 50 130 µA

V

CC

= V

CC

Max

CE# = RP# = V

CC

±

0.2V

I

CCD

VCC Deep Power-Down
Current

1 0.2 8 0.2 8 µA

V

CC

= V

CC

Max

V

IN

= VCC or GND

RP# = GND ± 0.2V

I

CCR

VCC Read Current for
Word or Byte

1,5,6 15 30 50 60 mA

CMOS INPUTS

V

CC

= V

CC

Max

CE# = GND, OE# = V

CC

f = 10 MHz (5V)

5 MHz (3.3V)

I

OUT

= 0 mA, Inputs =

GND ± 0.2V or V

CC

± 0.2V

15 30 55 65 mA

TTL INPUTS

V

CC

= V

CC

Max

CE# = V

IL

, OE# = V

IH

f = 10 MHz (5V)

5 MHz (3.3V)

I

OUT

= 0 mA, Inputs =

V

IL

or V

IH

I

CCW

VCCProgram Current for
Word or Byte

1,4 13 30 30 50 mA

V

PP

= V

PPH

1 (at 5V)

Program in Progress

10 25 30 45 mA

V

PP

= V

PPH

2 (at 12V)

Program in Progress

I

CCE

VCC Erase Current 1,4 13 30 18 35 mA

V

PP

= V

PPH

1 (at 5V)

Block Erase in Progress

10 25 18 30 mA

V

PP

= V

PPH

2 (at 12V)

Block Erase in Progress

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

31

PRELIMINARY

Table 11. DC Characteristics (Commercial) (Continued)

Prod

BV-60

BV-80

BV-120

Sym Parameter V

CC

3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Note Typ Max Typ Max

I

CCES

VCCErase Suspend
Current

1,2 3 8.0 5 10 mA

CE# = V

IH

Block Erase Suspend

I

PPS

V

PP

Standby Current 1 ± 0.5 ± 15 ± 0.5 ± 10 µA V

PP

< V

PPH

2

I

PPD

VPPDeep Power-Down
Current

1 0.2 5.0 0.2 5.0 µA RP# = GND ± 0.2V

I

PPR

V

PP

Read Current 1 50 200 30 200 µA VPP ≥ V

PPH

2

I

PPW

VPPProgram Current for
Word or Byte

1,4 13 30 13 25 mA

V

PP

= V

PPH

1 (at 5V)

Program in Progress

825820

V

PP

= V

PPH

2 (at 12V)

Program in Progress

I

PPE

VPP Erase Current 1,4 13 30 10 20 mA

V

PP

= V

PPH

1 (at 5V)

Block Erase in Progress

825515

V

PP

= V

PPH

2 (at 12V)

Block Erase in Progress

I

PPES

VPP Erase
Suspend Current

1 50 200 30 200 µA

V

PP

= V

PPH

Block Erase Suspend in

Progress

I

RP#

RP# Boot Block Unlock
Current

1,4 500 500 µA RP# = V

HH

I

ID

A9 Intelligent
Identifier Current

1,4 500 500 µA A

9

= V

ID

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

32

PRELIMINARY

Table 11. DC Characteristics (Commercial) (Continued)

Prod

BV-60

BV-80

BV-120

Sym Parameter V

CC

3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Note Min Max Min Max

V

ID

A9 Intelligent Identifier
Voltage

11.4 12.6 11.4 12.6 V

V

IL

Input Low Voltage –0.5 0.8 –0.5 0.8 V

V

IH

Input High Voltage 2.0

V

CC

+

0.5V

2.0

VCC +

0.5V

V

V

OL

Output Low Voltage 0.45 0.45 V

V

CC

= V

CC

Min

I

OL

= 5.8 mA

VOH1 Output High Voltage (TTL) 2.4 2.4 V

V

CC

= V

CC

Min

I

OH

= –2.5 mA

VOH2 Output High Voltage (CMOS)

0.85 ×
V

CC

0.85 ×
V

CC

V

V

CC

= V

CC

Min

I

OH

= –2.5 mA

V

CC–

0.4V

V

CC–

0.4V

V

V

CC

= V

CC

Min

I

OH

= –100 µA

V

PPLK

VPP Lock-Out Voltage 3 0.0 1.5 0.0 1.5 V Total Write Protect

V

PPH

1VPP (Prog/Erase Operations) 4.5 5.5 4.5 5.5 V V

PP

at 5V

V

PPH

2VPP (Prog/Erase Operations) 11.4 12.6 11.4 12.6 V V

PP

at 12V

V

LKO

V

CC

Erase/Prog Lock Voltage 8 2.0 2.0 V

V

HH

RP# Unlock Voltage 11.4 12.6 11.4 12.6 V Boot Block Unlock

Table 12. Capacitance (T

A

= 25°C, f = 1 MHz)

Symbol Parameter Note Typ Max Unit Conditions

C

IN

Input Capacitance 4 6 8 pF VIN = 0V

C

OUT

Output Capacitance 4, 7 10 12 pF V

OUT

= 0V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

CC

= 5.0V, T = +25°C. These currents are valid for all

product versions (packages and speeds).

2. I

CCES

is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of

I

CCES

and I

CCR

.

3. Block erases and word/byte writes are inhibited when V

PP

= V

PPLK

, and not guaranteed in the range between V

PPH

1 and

V

PPLK

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical, in static operation.

6. CMOS Inputs are either V

CC

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

7. For the 28F004B, address pin A

10

follows the C

OUT

capacitance numbers.

8. For all BV/CV parts, V

LKO

= 2.0V for both 3.3V and 5V operations.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

33

PRELIMINARY

TEST POINTSINPUT

OUTPUT

1.5

3.0

0.0

1.5

NOTE:

AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.

0530_12

Figure 12. 3.3V Inputs and Measurement Points

TEST POINTS

INPUT OUTPUT

2.0

0.8 0.8

2.0

2.4

0.45

NOTE:

AC test inputs are driven at VOH (2.4 V

TTL

) for a logic “1” and VOL (0.45 V

TTL

) for a logic “0.” Input timing begins at VIH (2.0 V

TTL

)

and VIL (0.8 V

TTL

) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.

0530_13

Figure 13. 5V Inputs and Measurement Points

C

L

OUT

V

CC

DEVICE
UNDER

TEST

R

1

R

2

0530_14

NOTE: See table for component values.

Figure 14. Test Configuration

Test Configuration Component Values

Test Configuration CL (pF) R1 (Ω)R2 (Ω)

3.3V Standard Test 50 990 770
5V Standard Test 100 580 390
5V High-Speed Test 30 580 390

NOTE: CL includes jig capacitance.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

34

PRELIMINARY

5.3 AC Characteristics

Table 13. AC Characteristics: Read Only Operations (Commercial)

Prod BV-60

Sym Parameter V

CC

3.3 ± 0.3V

(5)

5V ± 5%

(6)

5V ± 10%

(7)

Unit
Load 50 pF 30 pF 100 pF
Note Min Max Min Max Min Max

t

AVAV

Read Cycle Time 110 60 70 ns

t

AVQV

Address to Output Delay 110 60 70 ns

t

ELQV

CE# to Output Delay 2 110 60 70 ns

t

PHQV

RP# to Output Delay 0.8 0.45 0.45 µs

t

GLQV

OE# to Output Delay 2 65 30 35 ns

t

ELQX

CE# to Output in Low Z 3 0 0 0 ns

t

EHQZ

CE# to Output in High Z 3 25 20 20 ns

t

GLQX

OE# to Output in Low Z 3 0 0 0 ns

t

GHQZ

OE# to Output in High Z 3 25 20 20 ns

t

OH

Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First

3000ns

t

ELFL

t

ELFH

CE# Low to BYTE# High or
Low

3000ns

t

AVFL

Address to BYTE# High or
Low

3555ns

t

FLQV

t

FHQV

BYTE# to Output Delay 3,4 110 60 70 ns

t

FLQZ

BYTE# Low to Output in
High Z

3452025ns

t

PLPH

Reset Pulse Width Low 8 150 60 60 ns

t

PLQZ

RP# Low to Output High Z 150 60 60 ns

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

35

PRELIMINARY

Table 13. AC Characteristics: Read Only Operations (Commercial) (Continued)

BV-80 BV-120

Sym Parameter VCC3.3 ± 0.3V

(5)

5V ± 10%

(7)

3.3 ± 0.3V

(5)

5V ± 10%

(7)

Unit
Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

t

AVAV

Read Cycle Time 150 80 180 120 ns

t

AVQV

Address to Output Delay 150 80 180 120 ns

t

ELQV

CE# to Output Delay 2 150 80 180 120 ns

t

PHQV

RP# to Output Delay 0.8 0.45 0.8 0.45 µs

t

GLQV

OE# to Output Delay 2 90 40 90 40 ns

t

ELQX

CE# to Output in Low Z 3 0 0 0 0 ns

t

EHQZ

CE# to Output in High Z 3 25 20 25 20 ns

t

GLQX

OE# to Output in Low Z 3 0 0 0 0 ns

t

GHQZ

OE# to Output in High Z 3 25 20 25 20 ns

t

OH

Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First

30 0 0 0 ns

t

ELFL

t

ELFH

CE# Low to BYTE# High or
Low

30 0 0 0 ns

t

AVFL

Address to BYTE# High or
Low

35555ns

t

FLQV

t

FHQV

BYTE# to Output Delay 3,4 150 80 180 120 ns

t

FLQZ

BYTE# Low to Output in
High Z

3 60306030ns

t

PLPH

Reset Pulse Width Low 8 150 60 150 60 ns

t

PLQZ

RP# Low to Output High Z 150 60 150 60

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t

CE–tOE

after the falling edge of CE# without impact on tCE.

3. Sampled, but not 100% tested.

4. t

FLQV

, BYTE# switching low to valid output delay will be equal to t

AVQV

, measured from the time DQ15/A–1 becomes valid.

5. See Test Configurations (Figure 14), 3.3V Standard Test component values.

6. See Test Configurations (Figure 14), 5V High-Speed Test component values.

7. See Test Configurations (Figure 14), 5V Standard Test component values.

8. The specification t

PLPH

is the minimum time RP# must be held low to produce a valid reset of the device.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

36

PRELIMINARY

Address Stable

Device and

Address Selection

IH

V

IL

V

ADDRESSES (A)

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

IH

V

IL

V

RP#(P)

OL

V

OH

V

PHQV

t

High Z

Valid Output

Data

Valid

Standby

AVAV

t

EHQZ

t

GHQZ

t

OH

t

GLQV

t

GLQX

t

ELQV

t

ELQX

t

AVQV

t

High Z

0530_15

Figure 15. AC Waveforms for Read Operations

Address Stable

Device

Address Select i on

IH

V

IL

V

ADDRESSES (A)

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

CE# (E)

OE# (G)

BYTE# (F)

DATA (D/Q)

(DQ0-DQ7)

OL

V

OH

V

High Z

Data Output

on DQ0-DQ7

Data

Valid

Standby

AVAV

t

EHQZ

t

GHQZ

t

AVQV

t

High Z

GLQV

t

ELQV

t

AVQV

t

OH

t

Data Output

on DQ0-DQ7

DATA (D/Q)

(DQ8-DQ14)

OL

V

OH

V

High Z

Data Output

on DQ8-DQ14

High Z

(DQ15/A-1)

OL

V

OH

V

High Z

High Z

Data Output

on DQ15

Address Input

FLQZ

t

ELQX

t

ELFL

t

AVFL

t

GLQX

t

0530_16

Figure 16. BYTE# Timing Diagram for Read Operations

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

37

PRELIMINARY

Table 14. AC Characteristics: WE#–Controlled Write Operations

(1)

(Commercial)

Prod BV-60

Sym Parameter V

CC

3.3 ± 0.3V

(9)

5V ± 5%

(10)

5V ± 10%

(10)

Unit

Load 50 pF 30 pF 100 pF

Note Min Max Min Max Min Max

t

AVAV

Write Cycle Time 110 60 70 ns

t

PHWL

RP# Setup to WE# Going Low 0.8 0.45 0.45 µs

t

ELWL

CE# Setup to WE# Going Low 0 0 0 ns

t

PHHWH

Boot Block Lock Setup to WE#
Going High

6,8 200 100 100 ns

t

VPWH

VPP Setup to WE# Going High

5,8 200 100 100 ns

t

AVWH

Address Setup to WE# Going
High

3905050ns

t

DVWH

Data Setup to WE# Going High 4 90 50 50 ns

t

WLWH

WE# Pulse Width 90 50 50 ns

t

WHDX

Data Hold Time from WE# High 4 0 0 0 ns

t

WHAX

Address Hold Time from WE#
High

3000ns

t

WHEH

CE# Hold Time from WE# High 0 0 0 ns

t

WHWL

WE# Pulse Width High 20 10 20 ns

t

WHQV1

Duration of Word/Byte Program 2,5 6 6 6 µs

t

WHQV2

Duration of Erase (Boot) 2,5,6 0.3 0.3 0.3 s

t

WHQV3

Duration of Erase (Parameter) 2,5 0.3 0.3 0.3 s

t

WHQV4

Duration of Erase (Main) 2,5 0.6 0.6 0.6 s

t

QVVL

VPP Hold from Valid SRD 5,8 0 0 0 ns

t

QVPH

RP# VHH Hold from Valid SRD 6,8 0 0 0 ns

t

PHBR

Boot-Block Lock Delay 7,8 200 100 100 ns

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

38

PRELIMINARY

Table 14. AC Characteristics: WE#–Controlled Write Operations

(1)

(Commercial) (Continued)

Prod BV-80 BV-120

Sym Parameter VCC3.3 ±0.3V

(9)

5V±10%

(11)

3.3 ± 0.3V

(9)

5V±10%

(11)

Unit
Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

t

AVAV

Write Cycle Time 150 80 180 120 ns

t

PHWL

RP# Setup to WE# Going
Low

0.8 0.45 0.8 0.45 µs

t

ELWL

CE# Setup to WE# Going
Low

0000ns

t

PHHWH

Boot Block Lock Setup to
WE# Going High

6,8 200 100 200 100 ns

t

VPWH

VPP Setup to WE# Going
High

5,8 200 100 200 100 ns

t

AVWH

Address Setup to WE#
Going High

3 120 50 150 50 ns

t

DVWH

Data Setup to WE# Going
High

4 120 50 150 50 ns

t

WLWH

WE# Pulse Width 120 50 150 50 ns

t

WHDX

Data Hold Time from
WE# High

40 0 0 0 ns

t

WHAX

Address Hold Time from
WE# High

30 0 0 0 ns

t

WHEH

CE# Hold Time from WE#
High

0000ns

t

WHWL

WE# Pulse Width High 30 30 30 30 ns

t

WHQV1

Word/Byte Program Time 2,5 6 6 6 6 µs

t

WHQV2

Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s

t

WHQV3

Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s

t

WHQV4

Erase Duration (Main) 2,5 0.6 0.6 0.6 0.6 s

t

QVVL

VPP Hold from Valid SRD 5,8 0 0 0 0 ns

t

QVPH

RP# VHH Hold from Valid
SRD

6,8 0 0 0 0 ns

t

PHBR

Boot-Block Lock Delay 7,8 200 100 200 100 ns

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

39

PRELIMINARY

NOTES:

1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.

3. Refer to command definition table for valid A

IN

. (Table 7)

4. Refer to command definition table for valid D

IN

. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).

6. For boot block program/erase, RP# should be held at V

HH

or WP# should be held at VIH until operation completes

successfully.

7. Time t

PHBR

is required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See Test Configurations (Figure 14), 3.3V Standard Test component values.

10. See Test Configurations (Figure 14), 5V High-Speed Test component values.

11. See Test Configurations (Figure 14), 5V Standard Test component values.

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

HH

V

6.5V

IL

V

IL

V

IN

D

IN

A

IN

A

WHEH

t

WHWL

t

Valid
SRD

IN

D

WHQV1,2,3,4

t

PHHWH

t

IH

V

PHWL

t

High Z

WHDX

t

IH

V

IL

V

V (V)

PP

12 3 4 65

PPH

V

PPLK

V

PPH

V1

2

WP#

IL

V

IH

V

AVAV

t

AVWH

t

WHAX

t

DVWH

t

WLWH

t

QVPH

t

QVVL

t

VPWH

t

IN

D

ELWL

t

0530_17

NOTES:

1. V

CC

Power-Up and Standby.

2. Write Program or Erase Setup Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

40

PRELIMINARY

Table 15. AC Characteristics: CE#–Controlled Write Operations

(1,12)

(Commercial)

Prod BV-60

Sym Parameter V

CC

3.3 ± 0.3V

(9)

5V ± 5%

(10)

5V ± 10%

(11)

Unit

Load 50 pF 30 pF 100 pF

Note Min Max Min Max Min Max

t

AVAV

Write Cycle Time 110 60 70 ns

t

PHEL

RP# High Recovery to CE#
Going Low

0.8 0.45 0.45

µs

t

WLEL

WE# Setup to CE# Going Low 0 0 0 ns

t

PHHEH

Boot Block Lock Setup to CE#
Going High

6,8 200 100 100 ns

t

VPEH

VPP Setup to CE# Going High

5,8 200 100 100 ns

t

AVEH

Address Setup to CE# Going
High

3905050ns

t

DVEH

Data Setup to CE# Going High 4 90 50 50 ns

t

ELEH

CE# Pulse Width 90 50 50 ns

t

EHDX

Data Hold Time from CE# High 4 0 0 0 ns

t

EHAX

Address Hold Time from CE#
High

3000ns

t

EHWH

WE # Hold Time from CE# High 0 0 0 ns

t

EHEL

CE# Pulse Width High 20 10 20 ns

t

EHQV1

Duration of Word/Byte
Programming Operation

2,5 6 6 6 µs

t

EHQV2

Erase Duration (Boot)

2,5,6 0.3 0.3 0.3 s

t

EHQV3

Erase Duration (Param)

2,5 0.3 0.3 0.3 s

t

EHQV4

Erase Duration(Main)

2,5 0.6 0.6 0.6 s

t

QVVL

VPP Hold from Valid SRD

5,8 0 0 0 ns

t

QVPH

RP# V

HH

Hold from

Valid SRD

6,8 0 0 0 ns

t

PHBR

Boot-Block Lock Delay 7,8 200 100 100 ns

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

41

PRELIMINARY

Table 15. AC Characteristics: CE#–Controlled Write Operations

(1,12)

(Commercial) (Continued)

Prod BV-80 BV-120

Sym Parameter VCC3.3 ± 0.3V

(9)

5V±10%

(11)

3.3 ± 0.3V

(9)

5V±10%

(11)

Unit

Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

t

AVAV

Write Cycle Time

150 80 180 120 ns

t

PHEL

RP# High Recovery to
CE# Going Low

0.8 0.45 0.8 0.45 µs

t

WLEL

WE# Setup to CE# Going
Low

0000ns

t

PHHEH

Boot Block Lock Setup to
CE# Going High

6,8 200 100 200 100 ns

t

VPEH

VPP Setup to CE# Going
High

5,8 200 100 200 100 ns

t

AVEH

Address Setup to CE#
Going High

3 120 50 150 50 ns

t

DVEH

Data Setup to CE# Going
High

4 120 50 150 50 ns

t

ELEH

CE# Pulse Width

120 50 150 50 ns

t

EHDX

Data Hold Time from CE#
High

40 0 0 0 ns

t

EHAX

Address Hold Time from
CE# High

30 0 0 0 ns

t

EHWH

WE # Hold Time from
CE# High

0000ns

t

EHEL

CE# Pulse Width High

30 30 30 30 ns

t

EHQV1

Duration of Word/Byte
Programming Operation

2,56666µs

t

EHQV2

Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s

t

EHQV3

Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s

t

EHQV4

Erase Duration(Main) 2,5 0.6 0.6 0.6 0.6 s

t

QVVL

VPP Hold from Valid SRD 5,8 0 0 0 0 ns

t

QVPH

RP# V

HH

Hold from

Valid SRD

6,8 0 0 0 0 ns

t

PHBR

Boot-Block Lock Delay

7,8 200 100 200 100 ns

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

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PRELIMINARY

NOTES:

See WE# Controlled Write Operations for notes 1 through 11.

12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.

ADDRESSES (A)

WE# (W)

OE# (G)

CE# (E)

DATA (D/Q)

RP# (P)

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

HH

V

6.5V

IL

V

IN

D

IN

A

IN

A

AVAV

t

Valid
SRD

IN

D

QVPH

t

PHHEH

t

High Z

EHDX

t

IH

V

IL

V

V (V)

PP

12 3 4 65

EHAX

t

EHQV1,2,3,4

t

EHEL

t

EHWH

t

ELEH

t

DVEH

t

VPEH

t

QVVL

t

PHEL

t

WLEL

t

AVEH

t

PPLK

V

PPH

V1

2

PPH

V

IL

V

IH

V

IL

V

IH

V

WP#

IN

D

0530_18

NOTES:

1. V

CC

Power-Up and Standby.

2. Write Program or Erase Setup Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

Figure 18. Alternate AC Waveforms for Write Operations (CE#–Controlled Writes)

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

Table 16. Erase and Program Timings (Commercial TA = 0°C to +70°C)

V

PP

5V ± 10% 12V ± 5%

V

CC

3.3 ± 0.3V

5V ± 10% 3.3 ± 0.3V 5V ± 10%

Parameter Typ Max Typ Max Typ Max Typ Max Unit

Boot/Parameter Block Erase Time 0.84 7 0.8 7 0.44 7 0.34 7 s
Main Block Erase Time 2.4 14 1.9 14 1.3 14 1.1 14 s
Main Block Program Time (Byte) 1.7 1.8 1.6 1.2 s
Main Block Program Time (Word) 1.1 0.9 0.8 0.6 s
Byte Program Time

(4)

10 10 8 8 µs

Word Program Time

(4)

13 13 8 8 µs

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value

independent of V

CC

and VPP. See Note 3 for typical conditions.

3. Typical conditions are +25°C with V

CC

and VPP at the center of the specifed voltage range. Production programming using

V

CC

= 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time.

4. Contact your Intel field representative for more information.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

44

PRELIMINARY

6.0 EXTENDED OPERATING CONDITIONS

Table 17. Extended Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Units

T

A

Operating Temperature –40 +85 °C

V

CC

2.7V–3.6V VCC Supply Voltage 1 2.7 3.6 Volts

3.3V VCC Supply Voltage (± 0.3V) 1 3.0 3.6 Volts
5V VCC Supply Voltage (10%) 2 4.50 5.50 Volts

NOTES:

1. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.

2. 10% V

CC

specifications apply to 80 ns and 120 ns versions in their standard test configuration.

6.1 Applying VCC Voltages

When applying VCC voltage to the device, a delay
may be required before initiating device operat ion,
depending on the V

CC

ramp rate. If VCC ramps

slower than 1V/100 µs (0.01 V/µs) t hen no delay is

required. If V

CC

ramps faster than 1V/100 µs (0.01
V/µs), then a delay of 2 µs is required before
initiating device operation. RP# = GND is
recommended during power-up to protect against
spurious write signals when V

CC

is between V

LKO

and V

CCMIN

.

VCC Ramp Rate Required Timing

≤ 1V/100 µs No delay required.
> 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read

operations, command writes, program operations, and erase operations. This delay

is

measured beginning from the time V

CC

reaches V

CCMIN

(2.7V for 2.7V–3.6V operation,

3.0V for 3.3 ± 0.3V operation; and 4.5V for 5V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3V and 5V operation, the system should first transition V

CC

from the existing voltage range to GND,

and then to the new voltage. Any time the V

CC

supply drops below V

CCMIN

, the chip may be reset, aborting any operations

pending or in progress.

3. These guidelines must be followed for any V

CC

transition from GND.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

6.2 DC Characteristics

Table 18. DC Characteristics: Extended Temperature Operation

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

2.7V–3.6V 3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Notes Typ Max Typ Max Typ Max

I

IL

Input Load
Current

1 ± 1.0 ± 1.0 ± 1.0 µA

V

CC

= VCCMax

V

IN

= VCC or GND

I

LO

Output
Leakage
Current

1 ± 10 ± 10 ± 10 µA

V

CC

= V

CC

Max

V

IN

= VCC or GND

I

CCS

V

CC

Standby
Current

1,3 50 110 60 110 70 150 µA

CMOS Levels

V

CC

= V

CC

Max

CE# = RP# = WP# =

V

CC

± 0.2V

0.4 1.5 0.4 1.5 0.8 2.5 mA

TTL Levels

V

CC

= V

CC

Max

CE# = RP# = BYTE#

= V

IH

I

CCD

VCC Deep
Power­Down
Current

1 0.2 8 0.2 8 0.2 8 µA

V

CC

= V

CC

Max

V

IN

= VCC or GND

RP# = GND ± 0.2V

I

CCR

VCC Read
Current for
Word or
Byte

1,5,6 14 30 15 30 50 65 mA

CMOS INPUTS

V

CC

= V

CC

Max

CE = V

IL

f = 10 MHz (5V)

5 MHz (3.3V)

I

OUT

= 0 mA

Inputs = GND ± 0.2V

or V

CC

± 0.2V

14 30 15 30 55 70 mA

TTL INPUTS

V

CC

= V

CC

Max

CE# = V

IL

f = 10 MHz (5V),

5 MHz (3.3V)

I

OUT

= 0 mA

Inputs = V

IL

or V

IH

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

46

PRELIMINARY

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

2.7V–3.6V 3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Notes Typ Max Typ Max Typ Max

I

CCW

V
Program
Current

1,4 8 3013303050mA

V

= V

1 (at 5V)

Program in Progress

for Word or
Byte

9 2510253045mA

V

= V

2 (at 12V)

Program in Progress

I

CCE

VCC Erase
Current

1,4 12 30 13 30 22 45 mA

V

= V

1 (at 5V)

Erase in Progress

9 2510251840mA

V

= V

2 (at 12V)

Erase in Progress

I

CCES

VCC Erase
Suspend
Current

1,2 2.5 8.0 3 8.0 5 12.0 mA

CE# = V
V

PP

= V

PPH

1 (at 5V)

Block Erase Suspend

I

PPS

V

PP

Standby
Current

1 ± 5 ± 15 ± 5 ± 15 ± 5 ± 15 µA V

PP

< V

PPH

2

I

PPD

VPP Deep
Power­Down
Current

1 0.2 10 0.2 10 0.2 10 µA RP# = GND ± 0.2V

I

PPR

VPP Read
Current

1 50 200 50 200 50 200 µA V

PP

≥ V

PPH

2

I

PPW

V
Program

1,4 13 30 13 30 13 30 mA

V

= V

1 (at 5V)

Program in Progress

Current for
Word/Byte

8 25 8 25 8 25 mA

V

= V

2 (at 12V)

Program in Progress

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

2.7V–3.6V 3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Notes Typ Max Typ Max Typ Max

I

PPE

VPP Erase
Current

1,4 13 30 13 30 15 25 mA

V

PP

= V

PPH

1 (at 5V)

Block Erase in

Progress

8 25 8 25 10 20 mA

V

PP

= V

PPH

2 (at 12V)

Block Erase in

Progress

I

PPES

VPP Erase
Suspend
Current

1 50 200 50 200 50 200 µA

V

PP

= V

PPH

Block Erase Suspend

in Progress

I

RP#

RP# Boot
Block
Unlock
Current

1,4 500 500 500 µA

RP# = V
V

PP

= 12V

I

ID

A

9

Intelligent
Identifier
Current

1,4 500 500 500 µA A

9

= V

ID

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

48

PRELIMINARY

Table 18. DC Characteristics: Extended Temperature Operation (Continued)

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

2.7V–3.6V 3.3 ± 0.3V 5V ± 10% Unit Test Conditions

Notes Min Max Min Max Min Max

V

ID

A

9

Intelligent
Identifier
Voltage

11.4 12.6 11.4 12.6 11.4 12.6 V

V

IL

Input Low
Voltage

–0.5 0.8 –0.5 0.8 –0.5 0.8 V

V

IH

Input High
Voltage

2.0

V

CC

±

0.5V

2.0

V

CC

±

0.5V

2.0

V

CC

±

0.5V

V

V

OL

Output Low
Voltage

0.45 0.45 0.45 V

V

CC

= V

CC

Min

I

OL

= 5.8 mA (5V)

2 mA (3.3V)

V

PP

= 12V

VOH1 Output

High
Voltage
(TTL)

2.4 2.4 2.4 V

V

CC

= V

CC

Min

I

OH

= –2.5 mA

VOH2 Output

High
Voltage

0.85

×

V

CC

0.85

×

V

CC

0.85

×

V

CC

V

V

CC

= V

CC

Min

I

OH

= –2.5 mA

(CMOS) V

CC–

0.4V

V

CC–

0.4V

V

CC–

0.4V

V

V

CC

= V

CC

Min

I

OH

= –100 µA

V

PPLK

V

PP

Lock-Out
Voltage

3 0.0 1.5 0.0 1.5 0.0 1.5 V Complete Write

Protection

V

PPH

1

V

PP

during

Prog/Erase

4.5 5.5 4.5 5.5 4.5 5.5 V V

PP

at 5V

V

PPH

2

Operations

11.4 12.6 11.4 12.6 11.4 12.6 V VPP at 12V

V

LKO

V

CC

Erase/Write
Lock
Voltage

8 2.0 2.0 2.0 V

V

HH

RP#
Unlock
Voltage

11.4 12.6 11.4 12.6 11.4 12.6 V

V

PP

= 12V

Boot Block Write/

Erase

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

Table 19. Capacitance (TA = 25 °C, f = 1 MHz)

Symbol Parameter Note Typ Max Unit Conditions

C

IN

Input Capacitance 4 6 8 pF VIN = 0V

C

OUT

Output Capacitance 4 10 12 pF V

OUT

= 0V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

CC

= 5.0V, T = +25°C. These currents are valid for all

product versions (packages and speeds).

2. I

CCES

is specified with device de-selected. If device is read while in erase suspend, current draw is sum of I

CCES

and I

CCR

.

3. Block erases and word/byte programs inhibited when V

PP

= V

PPLK

, and not guaranteed in the range between V

PPH

1 and

V

PPLK

.

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

CCR

to less than 1 mA typical, in static operation.

6. CMOS Inputs are either V

CC

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

7. For the 28F004B address pin A

10

follows the C

OUT

capacitance numbers.

8. For all BV/CV/BE/CE parts, V

LKO

= 2.0V for 2.7V, 3.3V and 5.0V operations.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

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PRELIMINARY

TEST POINTSINPUT

OUTPUT

1.35

2.7

0.0

1.35

0530_19

NOTE:

AC test inputs are driven at 2.7V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.

Figure 19. 2.7V–3.6V Input Range and Measurement Points

TEST POINTSINPUT

OUTPUT

1.5

3.0

0.0

1.5

0530_12

NOTE:

AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.

Figure 20. 3.3V Input Range and Measurement Points

TEST POINTS

INPUT OUTPUT

2.0

0.8 0.8

2.0

2.4

0.45

0530_13

NOTE:

AC test inputs are driven at VOH (2.4 V

TTL

) for a logic “1” and VOL (0.45 V

TTL

) for a logic “0.” Input timing begins at VIH (2.0 V

TTL

)

and VIL (0.8 V

TTL

). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.

Figure 21. 5V Input Range and Measurement Points

C

L

OUT

V

CC

DEVICE

UNDER

TEST

R

1

R

2

0530_14

NOTE: See table for component values.

Figure 22. Test Configuration

Test Configuration Component Values

Test Configuration CL (pF) R1 (Ω)R2 (Ω)

2.7V and 3.3V Standard
Test

50 990 770

5V Standard Test 100 580 390

NOTE: CL includes jig capacitance.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

6.3 AC Characteristics

Table 20. AC Characteristics: Read Only Operations

(1)

(Extended Temperature)

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter VCC2.7V–3.6V

(5)

3.3 ±0.3V

(5)

5V±10%

(6)

Unit

Load 50 pF 50 pF 100 pF

Notes Min Max Min Max Min Max

t

AVAV

Read Cycle Time 120 110 80 ns

t

AVQV

Address to Output Delay 120 110 80 ns

t

ELQV

CE# to Output Delay 2 120 110 80 ns

t

PHQV

RP# to Output Delay 0.8 0.8 0.45 µs

t

GLQV

OE# to Output Delay 2 65 65 40 ns

t

ELQX

CE# to Output in Low Z 3 0 0 0 ns

t

EHQZ

CE# to Output in High Z 3 25 25 20 ns

t

GLQX

OE# to Output in Low Z 3 0 0 0 ns

t

GHQZ

OE# to Output in High Z 3 25 25 20 ns

t

OH

Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First

30 0 0 ns

t

ELFL

t

ELFH

CE# Low to BYTE# High or Low 3 5 5 5 ns

t

AVFL

Address to BYTE# High or Low 3 0 0 0 ns

t

FLQV

t

FHQV

BYTE# to Output Delay 3,4 120 110 80 ns

t

FLQZ

BYTE# Low to Output in High Z 3 45 45 30 ns

t

PLPH

Reset Pulse Width Low 7 150 150 60 ns

t

PLQZ

RP# Low to Output High Z 150 150 60 ns

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t

CE–tOE

after the falling edge of CE# without impact on tCE.

3. Sampled, but not 100% tested.

4. t

FLQV

, BYTE# switching low to valid output delay will be equal to t

AVQV

, measured from the time DQ15/A–1 becomes valid.

5. See Test Configurations (Figure 22), 2.7V–3.6V and 3.3 ± 0.3V Standard Test component values.

6. See Test Configurations (Figure 22), 5V Standard Test component values.

7. The specification t

PLPH

is the minimum time RP# must be held low to produce a valid reset of the device.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

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PRELIMINARY

Table 21. AC Characteristics: WE#-Controlled Write Operations

(1)

(Extended Temperature)

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

2.7V–3.6V

(9)

3.3±0.3V

(9)

5V±10%

(10)

Unit

Load 50 pF 50 pF 100 pF

Notes Min Max Min Max Min Max

t

AVAV

Write Cycle Time 120 110 80 ns

t

PHWL

RP# High Recovery to WE#
Going Low

0.8 0.8 0.45 µs

t

ELWL

CE# Setup to WE# Going Low 0 0 0 ns

t

PHHWH

Boot Block Lock Setup to WE#
Going High

6,8 200 200 100 ns

t

VPWH

V

Setup to WE#

Going High

5,8 200 200 100 ns

t

AVWH

Address Setup to WE# Going
High

390 90 60 ns

t

DVWH

Data Setup to WE# Going High 4 70 70 60 ns

t

WLWH

WE# Pulse Width 90 90 60 ns

t

WHDX

Data Hold Time from WE# High 4 0 0 0 ns

t

WHAX

Address Hold Time from WE#
High

30 0 0 ns

t

WHEH

CE# Hold Time from WE# High 0 0 0 ns

t

WHWL

WE# Pulse Width High 30 20 20 ns

t

WHQV1

Word/Byte Program Time

2,5,8 6 6 6 µs

t

WHQV2

Erase Duration (Boot)

2,5,
6, 8

0.3 0.3 0.3 s

t

WHQV3

Erase Duration (Param)

2,5,8 0.3 0.3 0.3 s

t

WHQV4

Erase Duration (Main)

2,5,8 0.6 0.6 0.6 s

t

QVVL

VPP Hold from Valid SRD

5,8 0 0 0 ns

t

QVPH

RP# VHH Hold from Valid SRD

6,8 0 0 0 ns

t

PHBR

Boot-Block Lock Delay 7,8 200 200 100 ns

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.

3. Refer to command definition table for valid A

IN

. (Table 7)

4. Refer to command definition table for valid D

IN

. (Table 7)

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)

6. For boot block program/erase, RP# should be held at V

HH

or WP# should be held at VIH until operation completes

successfully.

7. Time t

PHBR

is required for successful locking of the boot block.

8. Sampled, but not 100% tested.

9. See Test Configurations (Figure 22), 2.7V–3.6V and 3.3 ± 0.3V Standard Test component values.

10. See Test Configurations (Figure 22), 5V Standard Test component values.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

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PRELIMINARY

Table 22. AC Characteristics: CE#–Controlled Write Operations

(1,11)

(Extended Temperature)

Prod TBE-120 TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

2.7V–3.6V

(9)

3.3 ±0.3V

(9)

5V±10%

(10)

Unit

Load 50 pF 50 pF 100 pF

Notes Min Max Min Max Min Max

t

AVAV

Write Cycle Time 120 110 80 ns

t

PHEL

RP# High Recovery to CE#
Going Low

0.8 0.8 0.45 µs

t

WLEL

WE# Setup to CE# Going Low 0 0 0 ns

t

PHHEH

Boot Block Lock Setup to CE#
Going High

6,8 200 200 100 ns

t

VPEH

VPP Setup to CE# Going High 5,8 200 200 100 ns

t

AVEH

Address Setup to CE# Going
High

90 90 60 ns

t

DVEH

Data Setup to CE# Going High 3 70 70 60 ns

t

ELEH

CE# Pulse Width 4 90 90 60 ns

t

EHDX

Data Hold Time from CE# High 0 0 0 ns

t

EHAX

Address Hold Time from CE#
High

40 0 0 ns

t

EHWH

WE# Hold Time from CE# High 3 0 0 0 ns

t

EHEL

CE# Pulse Width High 20 20 20 ns

t

EHQV1

Word/Byte Program Time

2,5 6 6 6 µs

t

EHQV2

Erase Duration (Boot)

2,5,6 0.3 0.3 0.3 s

t

EHQV3

Erase Duration (Param)

2,5 0.3 0.3 0.3 s

t

EHQV4

Erase Duration (Main)

2,5 0.6 0.6 0.6 s

t

QVVL

VPP Hold from Valid SRD 5,8 0 0 0 ns

t

QVPH

RP# V

HH

Hold from Valid SRD 6,8 0 0 0 ns

t

PHBR

Boot-Block Lock Delay 7,8 200 200 100 ns

NOTES:

See WE# Controlled Write Operations for notes 1 through 10.

11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be
measured relative to the CE# waveform.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

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PRELIMINARY

Table 23. Erase and Program Timings (Extended TA = –40°C to +85°C)

V

PP

5V ± 10% 12V ± 5%

V

CC

2.7V–3.6V 3.3 ± 0.3V 5V ± 10% 2.7V–3.6V 3.3 ± 0.3V 5V ± 10%

Parameter Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Unit

Boot/Parameter
Block Erase Time

0.88 7 0.84 7 0.8 7 0.46 7 0.44 7 0.34 7 s

Main Block
Erase Time

2.5 14 2.4 14 1.9 14 1.36 14 1.3 14 1.1 14 s

Main Block
Program Time
(Byte Mode)

1.87 1.7 1.4

1.76

1.6 1.2 s

Main Block
Program Time
(Word Mode)

1.21 1.1 0.9

0.88

0.8 0.6 s

Byte Program
Time

(4)

11 10 10

8.8

88µs

Word Program
Time

(4)

14.3 13 13

8.8

88µs

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value

independent of V

CC

and VPP. See Note 3 for typical conditions.

3. Typical conditions are +25°C with V

CC

and VPP at the center of the specifed voltage range. Production programming using

V

CC

= 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time.

4. Contact your Intel field representative for more information.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

56

PRELIMINARY

APPENDIX A

ORDERING INFORMATION

Product line designator

for all Intel Flash products

Density / Organiza t ion
00X

= x8-only (X = 1, 2, 4, 8)

X00

= x8/x16 Selectable (X = 2, 4, 8)

Access Speed

(ns)

BV/CV:

V

CC

= 5V

BE/CE:

V

CC

= 2.7V

Architecture
B

= Boot Block

C

= Compact 48-Lead TSOP

Boot Block

Operating Tempe rature
T

= Extended Temp

Blank

= Commercial Temp

Package
E

= TSOP

PA

= 44-Lead PSOP

TB

= Ext. Temp 44-Lead PSOP

E28F4 00 CV- T 08

T =

Top Boot

B =

Bottom Boot

Voltage Options

(V

PP/VCC

)

V

= (5 or 12 / 3.3 or 5)

E

= (5 or 12 / 2.7 or 5)

T

0530_23

VALID COMBINATIONS:

40-Lead TSOP 44-Lead PSOP 48-Lead TSOP 56-Lead TSOP

Commercial E28F004BVT60 PA28F400BVT60 E28F400CVT60 E28F400BVT60

E28F004BVB60 PA28F400BVB60 E28F400CVB60 E28F400BVB60
E28F004BVT80 PA28F400BVT80 E28F400CVT80 E28F400BVT80
E28F004BVB80 PA28F400BVB80 E28F400CVB80 E28F400BVB80
E28F004BVT120 PA28F400BVT120
E28F004BVB120 PA28F400BVB120

Extended TE28F004BVT80 TB28F400BVT80 TE28F400CVT80 TE28F400BVT80

TE28F004BVB80 TB28F400BVB80 TE28F400CVB80 TE28F400BVB80
TE28F004BET120 TE28F400CET120

TE28F004BEB120 TE28F400CEB120

Table 24. Summary of Line Items

V

CC

V

PP

40-Ld 44-Ld 48-Ld 56-Ld 0°C – –40°C –

Name 2.7V 3.3V 5V 5V 12V TSOP PSOP TSOP TSOP +70°C +85°C

28F004BV √√√√ √ √ √
28F400BV √√√√ √ √ √ √
28F400CV √√√√ √ √ √
28F004BE √√√√√ √
28F400CE √√√√ √ √

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

57

PRELIMINARY

APPENDIX B

ADDITIONAL INFORMATION

RELATED INTEL INFORMATION

(1,2)

Order

Number

Document

290599

Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit Datasheet

292194

AB-65 Migrating Designs from SmartVoltage Boot Block to Smart 5 Flash

292154

AB-60 2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family

290531

2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

290539

8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

292164

AP-611 2/4M Boot Block Compatibility with 2/4/8-M SmartVoltage Boot Block Flash
Memories

290448

28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet

290449

28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet

290451

28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet

290450

28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet

292148

AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM

292172

AP-617 Additional Flash Data Protection Using VPP, RP#, and WP#

292130

AB-57 Boot Block Architecture for Safe Firmware Updates

NOTES:

1. Please call the Intel Literature Center at [phone] to request Intel documentation. International customers should
contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.