Datasheet E28F200CV-T80, E28F200CV-B80 Datasheet (Intel Corporation)

E

December 1997

REFERENCE ONLY

2-MBIT SmartVoltage BOOT BLOCK

FLASH MEMORY FAMILY

28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B

n

Intel SmartVoltage Technology

 5 V or 12 V Program/Erase
 3.3 V or 5 V Read Operation

n

Very High-Performance Read

 5 V: 60 ns Access Time
 3 V: 110 ns Access Time

n

Low Power Consumption

 Max 60 mA Read Current at 5 V
 Max 30 mA Read Current at

3.3 V–3.6 V

n

x8/x16-Selectable Input/Output Bus

 28F200 for High Performance 16- or

32-bit CPUs

n

x8-Only Input/Output Architecture

 28F002B for Space-Constrained

8-bit Applications

n

Optimized Array Blocking Architecture

 One 16-KB Protected Boot Block
 Two 8-KB Parameter Blocks
 96-KB and 128-KB Main Blocks
 Top or Bottom Boot Locations

n

Extended Temperature Operation

 –40 °C to +85 °C

SEE NEW DESIGN RECOMMENDATIONS

n

Extended Block Erase Cycling

 100,000 Cycles at Commercial Temp
 10,000 Cycles at Extended Temp

n

Automated Word/Byte Program and
Block Erase

 Command User Interface
 Status Registers
 Erase Suspend Capability

n

SRAM-Compatible Write Interface

n

Automatic Power Savings Feature

n

Reset/Deep Power-Down Input

 0.2 µA I
 Provides Reset for Boot Operations

n

Hardware Data Protection Feature

 Absolute Hardware-Protection for

Boot Block

 Write Lockout during Power

Transitions

n

Industry-Standard Surface Mount
Packaging

 40-, 48-, 56-Lead TSOP
 44-Lead PSOP

n

Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories

n

ETOX™ IV Flash Technology

Typical

CC

New Design Recommendations:

For new 2.7 V–3.6 V VCC designs with this devi ce, Intel recommends using the Smart 3 Adv anced Boot
Block. Reference
order number 290580.

For new 5 V V

Smart 5 Flash Memory Family 2, 4, 8 Mbit

These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.

Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family

designs with this devi ce, Int el rec ommends usi ng the 2-Mbi t S mart 5 Boot Bloc k. Ref erence

CC

datasheet, order number 290599.

Order Number: 290531-005

datasheet,

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B may contain design defects or errors known as errata. Current

characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 5937
Denver, CO 8021-9808

or call 1-800-548-4725

or visit Intel’s website at http://www.intel.com

COPYRIGHT © INTEL CORPORATION, 1997 CG-041493

*Third-party brands and names are the property of their respective owners..

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

CONTENTS

PAGE PAGE

1.0 PRODUCT FAMILY OVERVIEW.....................5

1.1 New Features in the SmartVoltage Products5

1.2 Main Features..............................................5

1.3 Applications..................................................6

1.4 Pinouts.........................................................7

1.5 Pin Descriptions.........................................11

2.0 PRODUCT DESCRIPTION............................13

2.1 Memory Blocking Organization...................13

2.1.1 One 16-KB Boot Block.........................13

2.1.2 Two 8-KB Parameter Blocks................13

2.1.3 One 96-KB + One 128-KB Main Block.13

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION ................................................15

3.1 Bus Operations ..........................................15

3.2 Read Operations........................................15

3.2.1 Read Array..........................................15

3.2.2 Intelligent Identifiers ............................17

3.3 Write Operations........................................17

3.3.1 Command User Interface (CUI)...........17

3.3.2 Status Register....................................20

3.3.3 Program Mode.....................................21

3.3.4 Erase Mode.........................................21

3.4 Boot Block Locking ....................................22

3.4.1 V

3.4.2 WP# = V

3.4.3 RP# = V

3.4.4 Upgrade Note for 8-Mbit 44-PSOP

3.5 Power Consumption...................................26

3.5.1 Active Power .......................................26

3.5.2 Automatic Power Savings (APS) .........26

3.5.3 Standby Power....................................26

3.5.4 Deep Power-Down Mode.....................26

= VIL for Complete Protection .......22

PP

for Boot Block Locking .......22

IL

or WP# = VIH for Boot Block

HH

Unlocking ...........................................22

Package.............................................22

3.6 Power-Up/Down Operation.........................26

3.6.1 RP# Connected To System Reset.......26

3.6.2 V

3.7 Power Supply Decoupling ..........................27

3.7.1 VPP Trace On Printed Circuit Boards..27

4.0 ELECTRICAL SPECIFICATIONS..................28

4.1 Absolute Maximum Ratings........................28

4.2 Commercial Operating Conditions..............28

4.2.1 Applying V

4.3 Capacitance...............................................29

4.4 DC Characteristics—Commercial...............30

4.5 AC Characteristics—Commercial...............34

4.6 AC Characteristics—WE#-Controlled Write

4.7 AC Characteristics—CE#-Controlled Write

4.8 Erase and Program Timings—Commercial.43

4.9 Extended Operating Conditions..................43

4.9.1 Applying V

4.10 Capacitance.............................................44

4.11 DC Characteristics—Extended

4.12 AC Characteristics—Read Only

4.13 AC Characteristics—WE#-Controlled Write

4.14 AC Characteristics—CE#-Controlled Write

4.15 Erase and Program Timings—Extended

5.0 ORDERING INFORMATION..........................54

6.0 ADDITIONAL INFORMATION.......................55

Related Intel Information..................................55

, VPP AND RP# Transitions............27

CC

Voltages.........................29

CC

Operations—Commercial..........................37

Operations—Commercial..........................40

Voltages.........................44

CC

Temperature Operations............................45

Operations—Extended Temperature.........49

Operations— Extended Temperature........50

Operations— Extended Temperature........52

Temperature..............................................53

SEE NEW DESIGN RECOMMENDATIONS

3

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

REVISION HISTORY

Number Description

-001 Initial release of datasheet.

-002 Status changed from Product Preview to Preliminary

-003 Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity.

-004 Corrections: “This pin not available on 44-PSOP” inaccurate statement removed from pin

-005 Corrections: Figure 4, corrected pin designation 3 to “NC” from A17 on PA28F200.

28F200CV/CE/BE references and information added throughout.

2.7 V CE/BE specs added throughout.

The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,

3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying V

changed to clarify V

I

3.3 V Commercial spec changed from 10 to 5 µA.

PPD

ramp requirements.

CC

Voltages.” These sections completely

CC

Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component

values in table. (Component values also rounded off).

t

, t

, t

ELFL

ELFH

changed from 7 to 5 ns for 3.3 V BV-60 commercial and 3.3 V

AVFL

TBV-80 extended, 10 to 5 ns for 3.3 V BV-80 and BV-120 commercial.

t

and t

WHAX

t

changed from 1000 ns to 800 ns for 3.3 V BV-80, BV-120 commercial.

PHWL

t

changed from 1000 ns to 800 ns for 3.3 V BV-60, BV-80, and BV-120 commercial.

PHEL

changed from 10 to 0 ns.

EHAX

Minor cosmetic changes/edits.

description for WP# pin; Spec “t

” corrected to “t

QWL

” intelligent identifier values

QVVL;

corrected; Intel386™ EX block diagram updated because new 386 specs require less
glue logic.

Max program times for parameter and 96-KB main block added.
Specs t
Specs t
New specs t

Corrected typographical errors in

Added
Updated

ELFL
EHQZ

and t

and t

PLPH

changed from 5 ns (max) to 0 ns (min).

ELFH

improved.

HQZ

and t

added from Specification Update document (297612).

PLQZ

Ordering Information

New Design Recommendations

section to cover page.

Erase Suspend/Resume Flowchart

.

4

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

1.0 PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for the
two branches of products in the SmartVoltage
2-Mbit boot block flash memory family. These

-BV/CV suffi x produc ts off er 3.0 V–3. 6 V operation

and also operate at 5 V for high-speed access
times. Throughout this datasheet, the 28F200
refers to all x8/x16 2-Mbit products, while
28F002B refers to all x8 2-Mbit boot block
products. Section 1. 0 provides an overview of the
flash memory family including applications , pi nouts
and pin descriptions. Sections 2.0 and 3.0
describe the memory organization and operation
for these products. Section 4.0 contains the
family’s operating speci fications. Finally, Secti ons

5.0 and 6.0 provide ordering and document
reference information.

1.1 New Features in the SmartVoltage Products

The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12 V
program products, except for the dif ferences lis ted
below. All other functi ons are equivalent t o current
products, including signatures, write commands,
and pinouts.

• WP# pin has replaced a DU (Don’t Use) pin.

Connect the WP# pin to control signal or to
V

or GND (in this case, a logic -level signal

CC

can be placed on DU pin). Refer to Tables 2
and 9 to see how the WP# pin works.

• 5 V program/erase operation has been added.

If switching V
GND (not 5 V) for complete write protection.
To take advantage of 5 V write-capability,
allow for connecting 5 V to V
disconnecting 12 V from V

for write protection, s witch to

PP

PP

PP

line.

and

• Enhanced circuits optimize low V
performance, allowing operation down to

= 3.0 V.

V

CC

If you are using BX/BL 12 V V
products today, you should account for the
differences listed above and also allow for
connecting 5 V to V
from V

line, if 5 V writes are desired.

PP

and disconnecting 12 V

PP

boot block

PP

CC

1.2 Main Features

Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete vol tage s upply pins: V
read operation, and V
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. This product family, specifically the
28F200BV/CV, and 28F002BV provide program/
erase capability at 5 V or 12 V. The 28F200BV /CV
and 28F002BV allow reads with V

0.3 V or 5 V. Since many designs read from t he

flash memory a large percentage of the time, read
operation using the 3.3 V ranges can provide great
power savings. If read performance is an issue,
however, 5 V V
times.

For program and erase operations, 5 V V
operation eliminates the need for in system
voltage converters, while 12 V V
provides faster program and erase for situations
where 12 V is available, s uch as manufacturi ng or
designs where 12 V is in-system. For design
simplicity, however, just hook up V
the same 5 V ± 10% source.

The 28F200/28F002B boot block flash memory
family is a high-performance, 2-Mbit (2,097,152
bit) flash memory family organized as either
256 Kwords of 16 bits each (28F200 only) or
512 Kbytes of 8 bits each (28F200 and 28F002B).

for program and erase

PP

at 3.3 V ±

CC

provides faster read access

CC

PP

and VPP to

CC

for

CC

operation

PP

Table 1. SmartVoltage Provides Total Voltage Flexibility

Product Bus V

Name Width 3.3 V ± 0.3 V 5 V ± 5%

28F002BV-T/B x8 √√√√
28F200BV-T/B x8 or x16 √√√√
28F200CV-T/B x8 or x16 √√√√

CC

5 V ± 10% 12 V ± 5%

5 V ± 10%

SEE NEW DESIGN RECOMMENDATIONS

V

PP

5

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Separately erasable blocks, including a hardware­lockable boot block (16,384 by tes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and one block of 131,072
bytes), define the boot block flash family
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently eras ed and
programmed 100,000 times at commercial
temperature or 10,000 times at extended
temperature.

The boot block is located at either the t op (denoted
by -T suffix) or the bottom (-B suff ix) of the addres s
map in order to accommodate different
microprocessor protocols for boot code location.
The hardware-lockable boot block provides
complete code security for t he kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).

The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automati cally ex ecutes
the algorithms and timings necessary for program
and erase operations, including verifications,
thereby unburdening the microprocessor or
microcontroller of these tasks. The Status Register
(SR) indicates the st at us of the WSM and whether i t
successfully completed the desired program or
erase operation.

Program and Erase Automation allows program and
erase operations to be executed using an indust ry­standard two-write command sequence t o the CUI.
Data programming is performed in word (28F200
family) or byte (28F200 or 28F002B families)
increments. Each by te or word in the flash mem ory
can be programmed independently of other memory
locations, unlike erases, which erase all locations
within a block simultaneously.

The 2-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by

turning most of the flash memory’s circuitry off. This
mode is controlled by the RP # pin and its usage is
discussed in Section 3.5, along with other power
consumption issues.

Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically defaul ts to the read array mode, but
during a warm system reset, where power
continues uninterrupted to t he system components,
the flash memory could rem ain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the mem ory to
normal read mode upon activation of the Reset
signal. See Section 3.6.

The 28F200 provides both byte-wide or word-wide
input/output, which is control led by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ

The 28F200 products are available in a
ROM/EPROM-compatible pinout and hous ed in the
44-lead PSOP (Plastic Small Outline) pac kage, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F002
products are available in the 40-lead TSOP
package as shown in Figure 3.

Refer to the
(commercial temperature) and Section 4.11
(extended temperature), for complete current and
voltage specifications. Refer to the

Characteristics

temperature) and Section 4.12 (extended
temperature), for read, write and erase performance
specifications.

pin.

15/A–1

DC Characteristics

, Section 4.4

AC

, Section 4.5 (commercial

1.3 Applications

The 2-Mbit boot block flash memory family
combines high-density, low-power, high­performance, cost-effective flash memories with
blocking and hardware protection c apabilities. Their
flexibility and versatility reduce c ost s throughout t he
product life cycle. Flash memory is ideal for Just-In­Time production flow, reducing system inventory
and costs, and eliminating component handling
during the production phase.

When your product is in the end-user’s hands, and
updates or feature enhancements become
necessary, flash m emory reduces t he update cos ts
by allowing user-performed code changes instead
of costly product returns or technician calls.

6

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

The 2-Mbit boot block flas h memory fami ly prov ides
full-function, bloc ked flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, di gital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.

Reprogrammable systems, such as personal
computers, are ideal applications for the 2-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard

in desktop and portable PCs enables auto­configuration of ISA and PCI add-in cards.
However, since the plug and play specification
continues to evolve, a flash BIOS provides a cost­effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.

The 2-Mbit flash memory products are also
excellent design solutions f or digital cellular phone
and telecommunication switching applications
requiring very low power consumption, high­performance, high-density storage capability,
modular software designs, and a small form factor
package. The 2-Mbit’s bloc king scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four

main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).

Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a si ngle flash dev ice. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in plac e, decreasing RAM
requirements.

1.4 Pinouts

Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every pac kage pinout to
the 4 or 8-Mbit density. The 28F002B 40-lead
TSOP pinout for space-constrained designs is
shown in Figure 3. The 28F200 44-lead PSOP
pinout follows the industry-standard ROM/EPROM
pinout, as shown in Figure 4. For designs that
require x16 operation but have space concerns,
refer to the 48-lead pinout i n Figure 5. Furthermore,
the 28F200 56-lead TSOP pinout shown in Figure 6
provides compatibility with BX/BL family product
packages.

Pinouts for the corresponding 4-Mbit and 8-Mbit
components are also provided for convenient
reference. 2-Mbit pinouts are given on the chip
illustration in the center, with 4-Mbit and 8-Mbit
pinouts going outward from the center.

SEE NEW DESIGN RECOMMENDATIONS

7

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

A[17:1]

CS#

RD#

WR#

i386™ EX CPU

(25 MHz)

D[15:0]

RESET

RESET

NOTE:

A data bus buffer may be needed for processor speeds above 25 MHz.

Figure 1. 28F200 Interface to Intel386™ EX Microprocessor

A[16:17]

ADDRESS

LATCHES

LE

A[16:0]

CE#

OE#

WE#

28F200BV-60

D[15:0]

RP#

0530_01

80C188EB

-A15A

8

ALE

-AD

UCS#

WR#

RD#

RESIN#

P1.X

P1.X

7AD0

ADDRESS

LATCHES

LE

System Reset

V

CC

A

0-A17

28F002-T

-DQ

DQ

7

0

CE#

V

CC

10K

Ω

WE#
OE#

RP#

V

PP

WP#

0530_02

Figure 2. 28F002B Interface to Intel80C188EB 8-Bit Embedded Microprocessor

8

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

28F004B 28F004B

28F008B

A

A

A
A

A
A

A

A

A
A

WE#

RP#

V

WP#

A

A
A
A

A

A

A

A

16
15
14

13
12
11

PP

18

A

A
A

A

A

9
8

WE#

RP#

V

WP#

A

7
6
5

4

3

2

1

15

15

A

14

14

A

13

13

A

12

12

A

11

11

A

A
A

A
A
A

A

A

A

A

PP

18

9

9

A

8

8

WE#

RP#

V

PP

WP#

NC

A

7

7

A

6

6

A

5

5

A

4

4

A

3

3

A

2

2

A

1

1

16

16

A

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

28F002B

Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A

17

GND
NC

NC

A

10

DQ
DQ

DQ

DQ

V

CC

V

CC

NC

DQ
DQ
DQ
DQ

OE#

GND

CE#

A

0

7
6

5

4

3
2
1
0

A

17

GND
NC

NC

A

10

DQ
DQ

DQ

DQ

V

CC

V

CC

NC

DQ
DQ
DQ
DQ

OE#

GND

CE#

A

0

7
6

5

4

3
2
1
0

28F008B

A

17

GND
NC

A

19

A

10

DQ
DQ

DQ

DQ

V

CC

V

CC

NC

DQ
DQ
DQ
DQ

OE#

GND

CE#

A

0

Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications

28F800

V

PP

A

18

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

28F400 28F400

WP#

CE#

GND

OE#

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

NC

PP

1
2
3
4

A

7

A

5

6

A

6

5

7

A

4

8

A

3

A

9

2

10

A

1

11

A

0

12
13
14
15

0

16

8

17

1

18

9

19

2

20

10

21

3

22

11

PA28F200
BOOT BLOCK
44-Lead PSOP

0.525" x 1.110"

TOP VIEW

44

RP#

43

WE#

42

A

8

41

A

9

40

A

10

39

A

11

38

A

12

37

A

13

A

36

14

35

A

15

34

A

16

33

BYTE#

32

GND

31

DQ

/A DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

CC

15 -1

7
14
6
13
5
12
4

30
29
28
27
26
25
24
23

RP#

WE#

A

8

A

9

A

10

A

11

A

12

A

13

A

14

A

15

A

16

BYTE#

GND

/A

15 -1

DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

CC

7
14
6
13
5
12
4

V

WP#

A

A

A

A

A
A
A
A

A

CE#

GND

OE#

DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

PP

17
7
6
5
4
3
2
1

0

0
8
1
9
2
10
3

11

NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A18 on the 8-Mbit because no other pins were available for the high order
address. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH (12 V). To allow upgrades to
the 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A18 at the 8-Mbit density. See
Section 3.4 for details.

28F800

RP#

WE#

A
A
A
A
A
A
A
A
A

BYTE#

GND

DQ

15 -1

DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

CC

8
9
10
11
12
13
14
15
16

/A

7
14
6
13
5
12
4

Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards

SEE NEW DESIGN RECOMMENDATIONS

7
6

5

4

3
2
1
0

0530_03

0530_04

9

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

28F400 28F80028F40028F800

16

15

7

14

6
13
5
12

4

CC

11
3
10

2

9
1

8

0

0

NC

A

BYTE#

GND

DQ
DQ
DQ

DQ
DQ
DQ
DQ

DQ

V
V
DQ
DQ

DQ

DQ
DQ
DQ
DQ
DQ

OE#

GND

CE#

A

NC
NC

/A

16

CC

CC

0

A

BYTE#

GND

DQ

-1

DQ

DQ

DQ
DQ

DQ
DQ

DQ

V

CC

DQ
DQ
DQ

DQ

DQ
DQ

DQ

DQ

OE#

GND

CE#

A

15/A-1
7

14

6
13
5
12
4

11
3

10

2

9
1

8

0

A

16

0

16

BYTE#

GND

/A

-1

15
7

14

6
13
5
12

4

11
3
10

2

9
1

8

0

A

BYTE#

GND

DQ

DQ

DQ

DQ

DQ

DQ

DQ

DQ

V
V

DQ

DQ

DQ

DQ
DQ
DQ
DQ
DQ

OE#

GND

CE#

DQ

15

DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

DQ

11

DQ

3

DQ

10

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

OE#

GND

CE#

A

0

NC

16

15/A-1

7

14

6

13

5

12

4

CC

CC

11

3

10

2

9
1

8

0

A

0

NC

/A

0530_05

NC

0530_06

A

A
A

A

A

A

WE#

RP#

V

WP#

A

A

NC

NC

NC

A

A

15

15
14
13
12
11
10

A

9

A

8

WE#

RP#

PP

WP#

18
17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

15

A

A

14

14

A

A

13

13

A

A

12

12

A

A

11

11

A

A

10

10

A

A

9

A

NC

NC

V

PP

NC
NC

A

A
A

A

A

A
A

A

9

A

8

8

NC

NC

WE#

RP#

V

PP

WP#

NC
NC

17

NC

A

7

7

A

6

6

A

5

5

A

4

4

A

3

3

A

2

2

A

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

28F200

Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

A

48
47

BYTE#

46

GND

45

DQ

44

DQ

43

DQ

42

DQ

41

DQ

40

DQ

39

DQ

38

DQ

37

V

36

DQ

35

DQ

34

DQ

33

DQ

32

DQ

31

DQ

30

DQ

29

DQ

28

OE#

27

GND

26

CE#

A

25

Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

28F400 28F400

56
55

54

53
52

51
50
49
48
47
46
45

44

43
42
41
40
39
38
37
36
35
34
33

32

31

30
29

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

28

1
2
3
4
5
6
7
8
9

28F200

Boot Block

56-Lead TSOP

14 mm x 20 mm

TOP VIEW

NC

NC

A

15

A

14

A

13

A

12

A

11

A

10

A
A

NC

NC

WE#

RP#

NC
NC

V

PP

WP#

NC

A

17

A
A

A
A
A
A

A

NC

NC

NC

A

15

A

14

A

13

A

12

A

11

A

10

A
A

NC

NC

WE#

RP#

9

8

9

8

NC
NC

V

PP

WP#

NC
NC

A
A
A
A

A
A

A

NC

7
6
5
4
3
2

1

7
6

5
4
3
2

1

Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits

-1

10

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

1.5 Pin Descriptions

Table 2. 28F200/002 Pin Descriptions

Symbol Type Name and Function

A0–A

17

A

9

DQ0–DQ

DQ8–DQ

CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks.

RP# INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to

INPUT

INPUT ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During

INPUT/

7

OUTPUT

INPUT/

15

OUTPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F200 only has A

the 28F002B has A

this mode, A
is at a logic low, only the lower byte of the signatures are read. DQ

don’t care in the signature mode when BYTE# is low.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle

during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ

The 28F002B does not include these DQ

sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.

a read cycle. OE# is active low.

WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.

control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.

When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at V

erased. This overrides any control from the WP# input.

15/A–1

– A17.

0

decodes between the manufacturer and device IDs. When BYTE#

0

becomes the lowest order address for data output on DQ0–DQ7.

, the boot block is unlocked and can be programmed or

HH

–DQ

8

0

– A

pins, while

16

pins.

15

15/A–1

is a

SEE NEW DESIGN RECOMMENDATIONS

11

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Table 2. 28F200/002 Pin Descriptions

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Provides a method for unlocking the boot block in a system

BYTE# INPUT BYTE# ENABLE: Not available on 28F002B. Controls whether the device

V

CC

V

PP

GND GROUND: For all internal circuitry.
NC NO CONNECT: Pin may be driven or left floating.

without a 12 V supply.
When WP# is at logic low, the boot block is locked, preventing program and

erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the status register to indicate the operation
failed.

When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is at
V

. See Section 3.4 for details on write protection.

HH

operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.

When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ

address that decodes between the upper and lower byte. DQ

–DQ7 and DQ15/A–1 becomes the lowest order

0

–DQ14 are tri-stated

8

during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is

read and programmed on DQ

–DQ15.

0

DEVICE POWER SUPPLY: 5.0 V ± 10%, 3.3 V ± 0.3 V, 2.7 V–3.6 V (BE/CE
only)

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5 V ± 10% or 12 V ± 5% must
be applied to this pin. When V
against Program and Erase commands.

PP

< V

all blocks are locked and protected

PPLK

12

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

2.0 PRODUCT DESCRIPTION

2.1 Memory Blocking Organization

This product family features an asymmetrically­blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 tim es for
commercial temperature or up to 10,000 tim es for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolat i l e storage. The combination
of block sizes in the boot block architecture allow
the integration of several memories into a single
chip. For the address locations of the blocks, see
the memory maps in Figures 4 and 5.

2.1.1 ONE 16-KB BOOT BLOCK

The boot block is intended to repl ace a dedicated
boot PROM in a microprocess or or microcontroller­based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address m ap
to accommodate different microproces sor protocols
for boot code location. This boot block features
hardware controllable write-protection to protec t the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combinat i on of the V
WP# pins, as is detailed in Section 3.4.

, RP#, and

PP

2.1.2 TWO 8-KB PARAMETER BLOCKS

The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the by te­rewrite functionality of EEPROMs can be emulated.

These techniques are detailed in Intel ’s application
note

AP-604, Using Intel’s Boot Block Flash

Memory Parameter Blocks to Replace EEPROM

Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.

2.1.3 ONE 96-KB + ONE 128-KB MAIN

After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 2-Mbit
device contains one 96-Kbyte (98,304 byte) block
and one 128-Kbyte (131,072 byte) block. See the
memory maps for each device for more information.

BLOCK

.

SEE NEW DESIGN RECOMMENDATIONS

13

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

1FFFFH

1E000H

1DFFFH

1D000H

1CFFFH

1C000H
1BFFFH

10000H

0FFFFH

00000H

28F200-T

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK

28F200-B

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

16-Kbyte BOOT BLOCK

NOTE: In x8 operation, the least significant system address should be connected to A-1. Memory maps are shown for x16
operation.

Figure 7. Word-Wide x16-Mode Memory Maps

28F002-T 28F002-B

3FFFFH
3C000H

3BFFFH

3A000H

39FFFH

38000H

37FFFH

20000H

1FFFFH

00000H

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

3FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

NOTE: These memory maps apply to the 28F002B or the 28F200 in x8 mode.

Figure 8. Byte-Wide x8-Mode Memory Maps

0530_07

0530_08

14

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.0 PRODUCT FAMILY PRINCIPLES OF OPERATION

Flash memory combines E PROM functionality with
in-circuit electrical program and erase. The boot
block flash family utilizes a Command User
Interface (CUI) and automated algorithms to
simplify program and erase operations. The CUI
allows for 100% TTL-level control inputs, fixed
power supplies during erasure and programming,
and maximum EPROM compatibility.

When V
execute the following commands: Read Array,
Read Status Register, Clear Status Register and
intelligent identifier mode. The device provides
standard EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data c an be acc ess ed through t he CUI
or through the standard EPROM A
access (V

The same EPROM read, standby and output
disable functions are avai lable when 5 V or 12 V is
applied to the V
V

PP

functions associ ated wit h alt ering mem ory c ontent s:
Program and Erase, Intelligent Identifier Read, and
Read Status are accessed via the CUI.

The internal Write State Mac hi ne (WS M) completely
automates program and erase, beginning operation
signaled by the CUI and reporting status through
the status register. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.

< V

PP

ID

allows program and erase of the device. All

, the device will only successfully

PPLK

high voltage

) for PROM programming equipment.

pin. In addition, 5 V or 12 V on

PP

9

3.2 Read Operations

3.2.1 READ ARRAY

When RP# transitions from V
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.

When the device is in the read array mode, five
control signals must be c ontrolled to obtain data at
the outputs.

• RP# must be logic high (V

• WE# must be logic high (V

• BYTE# must be logic high or logic low

• CE# must be logic low (V

• OE must be logic low (V

In addition, the address of the desired l ocat ion mus t
be applied to the address pins. Refer to Figures 15
and 16 for the exact sequenc e and timing of these
signals.

If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to t he
CUI before reads can take place.

During system design, consideration should be
taken to ensure address and control inputs meet
required input slew rates of <10 ns as defined in
Figures 12 and 13.

(reset) to VIH, the

IL

)

IH

)

IH

)

IL

)

IL

3.1 Bus Operations

Flash memory reads, erases and programs in­system via the local CPU. All bus cycles to or from
the flash memory conform to standard
microprocessor bus cycles. These bus operations
are summarized in Tables 3 and 4.

SEE NEW DESIGN RECOMMENDATIONS

15

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE# OE# WE# A

Read 1,2,3 V
Output Disable V
Standby V
Deep Power-Down 9 V
Intelligent Identifier

4VIHV

(Mfr)
Intelligent Identifier

4,5 V

(Device)
Write 6,7,8 V

V

IH

V

IH

V

IH

IL

V

IH

V

IH

V

IL

V

IL

IH

V

IL

IH

IH

V

IH

XXXXXHigh Z

XXXXXXHigh Z

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

IL

Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE# OE# WE# A

Read 1,2,3 V
Output

Disable
Standby V
Deep Power-

9VILXXXXXXXHigh Z High Z

V

IH

V

IH

IH

V

IL

IL

V

V

IL

IH

V

XXXXXXHigh Z High Z

IH

V

IH

V

IH

A

9

0

XXXXD
XXXXHigh Z High Z

Down
Intelligent

Identifier (Mfr)
Intelligent

Identifier

4VIHV

4,5 V

IH

V

V

V

IL

IL

IH

V

V

IL

V

IL

IH

V

ID

IL

V

V

ID

IH

(Device)
Write 6,7,8 V

NOTES:

1. Refer to

2. X can be V

3. See

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A

5. See Table 5 for device IDs.

6. Refer to Table 7 for valid D

7. Command writes for block erase or word/byte program are only executed when V

8. To program or erase the boot block, hold RP# at V

9. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

DC Characteristics

, VIH for control pins and addresses, V

IL

DC Characteristics

.

for V

PPLK

during a write operation.

IN

V

V

IH

IL

, V

, V

PPH1

, VHH, VID voltages.

PPH2

V

IH

or V

PPLK

or WP# at VIH. See Section 3.4.

HH

XXXXDINHigh Z

IL

for VPP.

PPH

A

9

V

0

XXX D

PP

DQ

0–15

OUT

X X X High Z

V

ID

V

ID

XXX D

A

–1

IL

IH

V

PP

X 0089 H

X See

Table 5

IN

DQ

OUT

0–7

DQ

High Z

8–14

X X 89H High Z

X X See

High Z

Table

5

= X, A1–A17 = X.

1–A16

= V

or V

PP

PPH1

PPH2

.

16

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.2.2 INTELLIGENT IDENTIFIERS

To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the Intelligent Identifier command (90H) or
by taking the A
identifier read mode, A

facturer’s identifi cation code and A
device code. In byte-wi de m ode, only the lower byte
of the above signatures is read (DQ
“don’t care” in this mode). S ee Table 5 for product
signatures. To return to read array mode, write a
Read Array command (FFH).

Table 5. Intelligent Identifier Table

Product Mfr. ID Device ID

28F200 0089 H 2274 H 2275 H
28F002 89 H 7C H 7D H

pin to VID. Once in intelligent

9

= 0 outputs the manu-

0

(Top Boot)-B(Bottom Boot)

-T

= 1 outputs the

0

is a

15/A–1

3.3 Write Operations

3.3.1 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) is t he interface
between the microprocessor and the internal chip
controller. Commands are wri tten to the CUI using
standard microprocessor write timings. The
available commands are Read Array, Read
Intelligent Identifier, Read Status Register, Clear
Status Register, Erase and Program (summarized
in Tables 6 and 7). The three read modes are read
array, intelligent identi fier read, and status register
read. For Program or Erase commands, the CUI
informs the Write State Machine (WSM) that a
program or erase has been requested. During the
execution of a Program command, the WSM will
control the programming sequences and the CUI
will only respond to status reads. During an erase
cycle, the CUI will respond to status reads and
erase suspend. After the WSM has completed its
task, it will set the WSM Status bit to a “1” (ready ),
which indicates that t he CUI can respond to it s full
command set. Note that after the WSM has
returned control to the CUI, the CUI will s tay in the
current command state until it receives another
command.

3.3.1.1 Command Function Description

Device operations are selected by writing specific
commands into the CUI. Tabl es 6 and 7 define the
available commands.

SEE NEW DESIGN RECOMMENDATIONS

17

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Table 6. Command Codes and Descriptions

Code Device Mode Description

00 Invalid/

Reserved

FF Read Array Places the device in read array mode, so that array data will be output on the data

40 Program

Set-Up

10 Alternate

Prog Set-Up

20 Erase

Set-Up

D0 Erase

Resume/

Erase

Confirm

B0 Erase

Suspend

70 Read Status

Register

Unassigned commands that should not be used. Intel reserves the right to redefine
these codes for future functions.

pins.
Sets the CUI into a state such that the next write will latch the Address and Data

registers on the rising edge and begin the program algorithm. The device then
defaults to the read status mode, where the device outputs status register data
when OE# is enabled. To read the array, issue a Read Array command.

To cancel a program operation after issuing a Program Set-Up command, write all

1’s (FFH for x8, FFFFH for x16)
mode after a standard program time without modifying array contents. If a program
operation has already been initiated to the WSM this command cannot cancel that
operation in progress.

(See 40H/Program Set-Up)

Prepares the CUI for the Erase Confirm command. If the next command is not an
Erase Confirm command, then the CUI will set both the Program Status (SR.4) and
Erase Status (SR.5) bits of the status register to a “1,” place the device into the
read status register state, and wait for another command without modifying array
contents. This can be used to cancel an erase operation after the Erase Set-Up
command has been issued. If an operation has already been initiated to the WSM
this can not cancel that operation in progress.

If the previous command was an Erase Set-Up command, then the CUI will latch
address and data, and begin erasing the block indicated on the address pins.
During erase, the device will respond only to the Read Status Register and Erase
Suspend commands and will output status register data when OE# is toggled low.
Status register data is updated by toggling either OE# or CE# low.

Valid only while an erase operation is in progress and will be ignored in any other
circumstance. Issuing this command will begin to suspend erase operation. The
status register will indicate when the device reaches erase suspend mode. In this
mode, the CUI will respond only to the Read Array, Read Status Register, and
Erase Resume commands and the WSM will also set the WSM Status bit to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the
WSM and the remainder of the chip, if it is made active. During a suspend
operation, the data and address latches will remain closed, but the address pads
are able to drive the address into the read path. See Section 3.3.4.1.

Puts the device into the read status register mode, so that reading the device
outputs status register data, regardless of the address presented to the device.
The device automatically enters this mode after program or erase has completed.
This is one of the two commands that is executable while the WSM is operating.
See Section 3.3.2.

to the CUI. This will return to read status register

18

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

Table 6. Command Codes and Descriptions (Continued)

Code Device Mode Description

50 Clear Status

Register

90 Intelligent

Identifier

Command Note Oper Addr Data Oper Addr Data

Read Array 1 Write X FFH
Intelligent Identifier 1, 2, 4 Write X 90H Read IA IID
Read Status Register 3 Write X 70H Read X SRD
Clear Status Register Write X 50H
Word/Byte Program 1, 6, 7 Write PA 40H/10H Write PA PD
Block Erase/Confirm 1, 5 Write BA 20H Write BA D0H
Erase Suspend Write X B0H
Erase Resume Write X D0H

The WSM can only set the Program Status and Erase Status bits in the status
register to “1;” it cannot clear them to “0.”

The status register operates in this fashion for two reasons. The first is to give the
host CPU the flexibility to read the status bits at any time. Second, when
programming a string of bytes, a single status register query after programming the
string may be more efficient, since it will return the accumulated error status of the
entire string. See Section 3.3.2.1.

Puts the device into the intelligent identifier read mode, so that reading the device
will output the manufacturer and device codes. (A

= 1 for device, all other address inputs are ignored). See Section 3.2.2.

A

0

Table 7. Command Bus Definitions

First Bus Cycle

(1)

= 0 for manufacturer,

0

Second Bus Cycle

(1)

ADDRESS DATA

BA= Block Address SRD= Status Register Data
IA= Identifier Address IID= Identifier Data
PA= Program Address PD= Program Data

X= Don’t Care

NOTES:

1. Bus operations are defined in Tables 3 and 4.

2. IA = Identifier Address: A

3. SRD = Data read from status register.

4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and

device codes.

5. BA = Address within the block being erased.

6. PA = Address to be programmed. PD = Data to be programmed at location PA.

7. Either 40H or 10H commands is valid.

8. When writing commands to the device, the upper data bus [DQ

minimize current draw.

SEE NEW DESIGN RECOMMENDATIONS

= 0 for manufacturer code, A0 = 1 for device code.

0

–DQ15] = X (28F200 only) which is either VIL or VIH, to

8

19

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Table 8. Status Register Bit Definition

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

SR.7 = WRITE STATE MACHINE STATUS

1 = Ready (WSMS)
0 = Busy

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended
0 = Erase In Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure
0 = Successful Block Erase

SR.4 = PROGRAM STATUS (DWS)

1 = Error in Byte/Word Program
0 = Successful Byte/Word Program

SR.3 = VPP STATUS (VPPS)

Low Detect, Operation Abort

1 = V

PP

OK

0 = V

PP

SR.2–SR.0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

Check Write State Machine bit first to determine
Word/Byte program or Block Erase completion,
before checking Program or Erase Status bits.

When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to

“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.

When this bit is set to “1,” WSM has applied the
max number of erase pulses to the block and is
still unable to verify successful block erasure.

When this bit is set to “1,” WSM has attempted
but failed to program a byte or word.

The V
indication of V

Status bit does not provide continuous

PP

level. The WSM interrogates V

PP

level only after the Program or Erase command
sequences have been entered, and informs the
system if V

has not been switched on. The V

PP

PP

Status bit is not guaranteed to report accurate
feedback between V

PPLK

and V

PPH

.

These bits are reserved for future use and should
be masked out when polling the status register.

PP

3.3.2 STATUS REGISTER

The device status register indicates when a
program or erase operation is complete, and the
success or failure of that operation. To read the
status register write the Read Status (70H)
command to the CUI. This causes all subsequent
read operations to output data from the status
register until another command is written to the
CUI. To return to reading from the array, issue a
Read Array (FFH) command.

The status register bit s are output on DQ

–DQ7, in

0

both byte-wide (x8) or word-wide (x16) m ode. In the
word-wide mode the upper byte, DQ

–DQ15,

8

outputs 00H during a Read Status comm and. In t he
byte-wide mode, DQ
DQ

retains the low order address function.

15/A–1

20

–DQ14 are tri-stated and

8

SEE NEW DESIGN RECOMMENDATIONS

Important: The contents of the status register
are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. This

prevents possible bus errors which might occur if
status register contents change while being read.
CE# or OE# must be toggled wi th eac h subs equent
status read, or the status regis ter will not indicate
completion of a program or erase operation.

When the WSM is active, the SR.7 register will
indicate the status of the WSM, and will also hold
the bits indicating whether or not the WSM was
successful in performing the desired operation.

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.3.2.1 Clearing the Status Register

The WSM sets status bits 3 through 7 to “1,” and
clears bits 6 and 7 to “0,” but cannot clear status
bits 3 through 5 to “0.” Bits 3 through 5 can only be
cleared by the controlling CPU through t he use of
the Clear Status Register (50H) com mand, bec aus e
these bits indicate various error conditions. By
allowing the system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes
or erasing multiple blocks in sequence) before
reading the status regist er to determine if an error
occurred during that series. Cl ear the status register
before beginning another command or sequence.
Note, again, that a Read Array command must be
issued before data can be read from the memory or
intelligent identifier.

3.3.3 PROGRAM MODE

Programming is executed using a two-write
sequence. The Program Set-Up com m and i s written
to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to:

1. Program the desired bits of the addressed

memory word or byte.

2. Verify that the desired bits are sufficiently

programmed.

Programming of the memory res ults in spec ific bits
within a byte or word being changed to a “0.”

If the user attempts to program “1”s, there will be no
change of the memory cell content and no error
occurs.

The status register indicates programming status:
while the program sequence is exec uting, bit 7 of
the status register i s a “0.” The status register c an
be polled by toggling either CE# or OE#. While
programming, the only valid command is Read
Status Register.

When programming is complete, the program status
bits should be checked. If the programming
operation was unsuccessful, bit 4 of the status
register is set to a “1” t o i ndicat e a P rogram Failure.
If bit 3 is set to a “1,” then V
acceptable limits , and the WSM did not exec ute the
programming sequence.

was not within

PP

The status register should be cleared before
attempting the next operat ion. Any CUI instruction
can follow after programming is completed;
however, reads from the memory array or intelligent
identifier cannot be accomplished until the CUI is
given the appropriate command.

3.3.4 ERASE MODE

To erase a block, write the E rase Set -Up and E rase
Confirm commands to the CUI, along with the
addresses identifying t he bloc k t o be eras ed. These
addresses are latched internally when the Erase
Confirm command is iss ued. Block erasure results
in all bits within the block being s et to “1.” Only one
block can be erased at a time.

The WSM will execute a sequence of internally
timed events to:

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are
sufficiently programmed to “0.”

3. Erase all bits within the block to “1.”

4. Verify that all bits within the block are
sufficiently erased.

While the erase sequence is executing, bit 7 of the
status register is a “0.”

When the status register indicates that erasure is
complete, check the erase status bit to verify that
the erase operation was successful. If the erase
operation was unsuccessful, bit 5 of the status
register will be set to a “1,” indicating an Erase
Failure. If V
the Erase Confirm command is issued, the WSM
will not execute an erase sequence; ins tead, bit 5 of
the status register is set to a “1” to indicate an
Erase Failure, and bit 3 is s et to a “1” to ident i f y that
V

supply voltage was not within acceptable limits.

PP

Clear the status register before att empting the next
operation. Any CUI instruction can follow after
erasure is completed; however, reads from the
memory array, status register, or intelligent
identifier cannot be accomplished until the CUI is
given the Read Array command.

was not within acceptable l imits af ter

PP

SEE NEW DESIGN RECOMMENDATIONS

21

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

3.3.4.1 Suspending and Resuming Erase

Since an erase operation requires on the order of
seconds to complete, an Erase Suspend c ommand
is provided to allow erase-s equence interruption in
order to read data from another block of the
memory. Once the erase sequence is started,
writing the Erase Suspend command to the CUI
requests that the WSM paus e the erase sequence
at a predetermined point in the erase algorithm. The
status register will indicate if/when the erase
operation has been suspended.

At this point, a Read Array com mand c an be wri tt en
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register command.

During erase suspend mode, the chi p can go into a
pseudo-standby mode by taki ng CE# to V

, which

IH

reduces active current draw.
To resume the erase operation, enable the chip by

taking CE# to V

, then issuing the Eras e Resume

IL

command, which continues the erase s equence to
completion. As with the end of a standard erase
operation, the status regi st er must be read, c leared,
and the next instruction issued in order to continue.

3.4 Boot Block Locking

The boot block family architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Onl y the boot
block can be locked independently from the other
blocks. The truth table, Table 9, clearly defines the
write protection methods.

3.4.1 V

For complete write protection of all blocks in the
flash device, the V
held low. When V
erase operation will result in a error in the status
register.

= VIL FOR COMPLETE

PP

PROTECTION

programming voltage can be

PP

is below V

PP

, any program or

PPLK

3.4.2 WP# = V

LOCKING

When WP# = V

FOR BOOT BLOCK

IL

, the boot block is loc ked and any

IL

program or erase operation to the boot block will
result in an error in the status register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
when RP# = V

3.4.3 RP# = V

.

HH

OR WP# = VIH FOR BOOT

BLOCK UNLOCKING

HH

Two methods can be used to unlock the boot block:

1. WP# = V

2. RP# = V

IH

HH

If both or either of these t wo condit ions are met , the
boot block will be unlocked and can be
programmed or erased.

3.4.4 UPGRADE NOTE FOR 8-MBIT

44-PSOP PACKAGE

If upgradability to 8 Mbit is required, note that the
8-Mbit in the 44-PSOP does not have a WP#
because no pins were available for the 8-Mbit
upgrade address. Thus, in this density-package
combination only, V

(12 V) on RP# is required to

HH

unlock the boot block. Unloc king with a logic-level
signal is not possible. If this functionality is
required, and 12 V is not av ailable, consider usi ng
the 48-TSOP package, which has a WP# pin and
can be unlocked with a logic-l evel signal. All other
density-package combinations have WP# pins.

Table 9. Write Protection Truth Table

V

≥ V

≥ V
≥ V
≥ V

RP# WP# Write Protection

PP

V

PPLKVIL

PPLKVHH

PPLKVIH

PPLKVIH

X X All Blocks Locked

IL

X All Blocks Locked

X All Blocks Unlocked

VILBoot Block Locked

VIHAll Blocks Unlocked

(Reset)

Provided

22

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

Start

Write 40H,

Word/Byte Address

Write Word/Byte

Data/Address

Read

Status Register

SR.7 = 1

?

Full Status

Check if Desired

Word/Byte Program

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

NO

YES

Bus

Operation

Write

Write

Read

Standby

Repeat for subsequent word/byte program operations.
SR Full Status Check can be done after each word/byte program,
or after a sequence of word/byte programs.
Write FFH after th e last program operation to reset device to
read array mode.

Bus

Operation

Command Comments

Setup

Program

Program

Command Comments

Data = 40H
Addr = Word/Byte to Program

Data = Data to Program
Addr = Location to Program

Status Register Data Toggle CE#
or OE# to Update SRD

Check SR.7
1 = WSM Ready
0 = WSM Busy

Standby

Standby

SR.3 MUST be cleared, if se t during a program attem pt, before further
attempts are allo w e d by t he Wr ite State Mach in e.

SR.4 is only cleared by the Clear Status Register Command, in cases
where multiple byte s are programmed before ful l status is checked.

If error is detected, clear the Status Register before attempting ret ry or
other error recovery.

SR.3 =

0

SR.4 =

0

Word/Byte Program

Successful

1

1

VPP Range Error

Word/Byte Program

Error

Figure 9. Automated Word/Byte Programming Flowchart

SEE NEW DESIGN RECOMMENDATIONS

Check SR.3
1 = V

Low Detect

PP

Check SR.4
1 = Word/Byte Program Error

0530_09

23

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Start

Write 20H,

Block Address

Write D0H and

Block Address

Read Status

Register

NO

0

SR.7 =

1

Full Status

Check if Desired

Block Erase

Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Suspend

Erase

Suspend Erase

Loop

YES

Bus

Operation

Write

Write

Read

Standby

Repeat for subsequent block erasures.
Full Status Check can be done after each block erase, or after a
sequence of block erasures.
Write FFH after the last operation to reset device to read array mode.

Bus

Operation

Command

Erase Setup

Erase

Confirm

Command Comments

Data = 20H
Addr = Within Block to Be Erased

Data = D0H
Addr = Within Block to Be Erased

Status Register Data Toggle CE#
or OE# to Update Status Register

Check SR.7
1 = WSM Ready
0 = WSM Busy

Comments

SR.3 =

SR.4,5 =

SR.5 =

Block Erase Successful

24

1

VPP Range Error

0

1

Command Sequence

Error

0

1

Block Erase Error

0

Standby

Standby

Standby

SR.3 MUST be cleared, if set during an erase attempt, be for e fu rt her
attempts are allowed by the Write State Machine.

SR.5 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.

If error is detected, clear the Status Register befo re at te m pti ng
retry or other error recovery.

Check SR.3
1 = V

Low Detect

PP

Check SR.4,5
Both 1 = Command Sequence Error

Check SR.5
1 = Block Erase Error

0530_10

Figure 10. Automated Block Erase Flowchart

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

Start

Write B0H

Write 70H

Read Status Register

SR.7 =

1

SR.6 =

1

Write FFH

Read Array Data

Done

Reading

0

0

No

Erase Completed

Bus

Operation

Write

Write

Write
Read

Read

Standby

Standby
Standby

Standby

Write

Write
Read

Read
Write

Write

Command

Command

Program

Program

Erase Suspend

Suspend

Suspend

Read Status

Read Array

Read Array

Read Array

Program

Program

Resume

Resume

Erase Resume

Comments

Data = B0H
Addr = X

Data=70H
Addr=X

Status Register Data Toggle

Status Register Data Toggle
CE# or OE# to Update Status

CE# or OE# to Update Status
Register Data

Register Data
Addr = X

Addr = X
Check SR.7

1 = WSM Ready
0 = WSM Busy

Check SR.6
1 = Erase Suspended
0 = Erase Completed

Data = FFH
Addr = X

Read array data from block
other than the one being
programmed.

Data = D0H
Addr = X

Yes

Write FFHWrite D0H

Erase Resumed Read Array Data

Figure 11. Erase Suspend/Resume Flowchart

SEE NEW DESIGN RECOMMENDATIONS

0530_11

25

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

3.5 Power Consumption

3.5.1 ACTIVE POWER

With CE# at a logic-low level and RP# at a logic­high level, the device i s placed in the active mode.
Refer to the DC Characterist ics table for I
values.

3.5.2 AUTOMATIC POWER SAVINGS (APS)

Automatic Power Savings (APS) provides low­power operation during active mode. Power
Reduction Control (PRC) circuit ry allows the dev ice
to put itself into a l ow current state when not bei ng
accessed. After data is read from the memory

array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical I

current is less than 1 mA. The device

CC

stays in this static state with outputs valid until a
new location is read.

3.5.3 STANDBY POWER

With CE# at a logic-high level (V

), and the CUI in

IH

read mode, the memory is plac ed in s tandby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ

–DQ15 or DQ0–DQ7) are placed in a high-

0

impedance state independent of the status of the
OE# signal. When CE# is at logic-high level during
erase or program operations, the device will
continue to perform the operation and consume
corresponding active power until the operation is
completed.

3.5.4 DEEP POWER-DOWN MODE

The SmartVoltage boot block family supports a low
typical I

in deep power-down mode, which turns

CC

off all circuits to s ave power. This mode is ac ti vat ed
by the RP# pin when it is at a logic-low (GND ±

0.2 V).

NOTE

Note: BYTE# pin must be at CMOS level s to
meet the I

specification.

CCD

During read modes, the RP# pin going low de­selects the memory and places the out put dri vers i n
a high impedance state. Recovery from the deep
power-down state, requires a mi nimum acces s t ime
of t

(see

PHQV

AC Characteristics

table).

current

CC

During erase or program modes, RP# low will abort
either erase or program operations, but the mem ory
contents are no longer valid as t he data has been
corrupted by the RP# functi on. As in the read mode
above, all internal circ uitry is turned off to achieve
the power savings.

RP# transitions to V
device will clear the status register.

, or turning power off to the

IL

3.6 Power-Up/Down Operation

The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, sinc e the
device is indifferent as to which power supply , V
or VCC, powers-up first. The CUI i s res et t o the read
mode after power-up, but the system must drop
CE# low or present a new address to ensure valid
data at the outputs.

A system designer must guard against spurious
writes when V

voltages are above V

CC

LKO

is active. Since both WE# and CE# mus t be low for
a command write, driving either signal to V
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabl ed until RP# is brought to
V

, regardless of the stat e of its c ontrol inputs. By

IH

holding the device in reset (RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.

3.6.1 RP# CONNECTED TO SYSTEM

RESET

The use of RP# during system reset is important
with automated program/erase devi ces becaus e the
system expects to read from the flash memory
when it comes out of res et. If a CPU reset occ urs
without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may be providing status information
instead of array data. Int el’s Flash memories al low
proper CPU initialization following a system reset
by connecting the RP# pin to the same RESET#
signal that resets the system CPU.

and V

IH

PP

PP

will

26

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.6.2 VCC, VPP AND RP# TRANSITIONS

The CUI latches commands as issued by system
software and is not altered by V
transitions or WSM actions. Its default state upon
power-up, after exit from deep power-down mode,
or after V
voltage), is read array mode.

After any word/byte program or block erase
operation is complete and even after V
down to V
mode via the Read Array command if acces ses to
the flash memory are desired.

Please refer to Intel’s application note

Additional Flash Data Protection Using V
and WP#

implement the protection discussed in Section 3.6.

transitions above V

CC

, the CUI must be reset to read array

PPLK

for a circuit-level description of how to

or CE#

PP

(lockout

LKO

transitions

PP

AP-617

PP

, RP#,

3.7 Power Supply Decoupling

Flash memory’s power switching characteristics
require careful device decoupli ng methods. System
designers should consider three supply current
issues:

1. Standby current levels (I

2. Active current levels (I

3. Transient peaks produced by falling and rising
edges of CE#.

CCR

CCS

)

)

Transient current magnitudes depend on t he dev ice
outputs’ capacitiv e and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between eac h V
and between its V
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.

3.7.1 V

Designing for in-system programming of the flash
memory requires special consideration of the V
power supply trace by the printed circuit board
designer. The V
cells current for programming and erasing. One
should use similar trace widths and layout
considerations given to t he V
Adequate V
capacitors placed adjacent to the component, will
decrease spikes and overshoots.

TRACE ON PRINTED CIRCUIT

PP

BOARDS

PP

and GND. These high-

PP

pin supplies the flash memory

PP

power supply trace.

supply traces, and decoupling

CC

and GND,

CC

PP

NOTE:

Table headings in the DC and AC characterist ics tables (i.e., BV-60, BV-80, BV-120, TBV-80, TBE-

120) refer to the specific products listed below. See Section 5.0 for more information on product
naming and line items.

Abbreviation Applicable Product Names

BV-60 E28F002BV-T60, E28F002BV-B60, PA28F200BV-T60, PA28F200BV-B60,

E28F200CV-T60, E28F200CV-B60, E28F200BV-T60, E28F200BV-B60

BV-80 E28F002BV-T80, E28F002BV-B80, PA28F200BV-T80, PA28F200BV-B80,

E28F200CV-T80, E28F200CV-B80, E28F200BV-T80, E28F200BV-B80
BV-120 E28F002BV-T120, E28F002BV-B120, PA28F200BV-T120, PA28F200BV-B120
TBV-80 TE28F002BV-T80, TE28F002BV-B80, TB28F200BV-T80, TB28F200BV-B80,

TE28F200CV-T80, TE28F200CV-B80, TE28F200BV-T80, TE28F200BV-B80

SEE NEW DESIGN RECOMMENDATIONS

27

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings*

Commercial Operating Temperature

During Read..............................0 °C to +70 °C

During Block Erase

and Word/Byte Program............0 °C to +70 °C

Temperature Under Bias ....... –10 °C to +80 °C

Extended Operating Temperature

During Read..........................–40 °C to +85 °C

During Block Erase

and Word/Byte Program........–40 °C to +85 °C

Temperature Under Bias ....... –40 °C to +85 °C

Storage Temperature................. –65 °C to +125 °C

Voltage on Any Pin

(except V

with Respect to GND........... –2.0 V to +7.0 V

Voltage on Pin RP# or Pin A

with Respect to GND....... –2.0 V to +13.5 V

VPP Program Voltage with Respect

to GND during Block Erase

and Word/Byte Program..–2.0 V to +14.0 V
VCC Supply Voltage

with Respect to GND........... –2.0 V to +7.0 V

Output Short Circuit Current....................100 mA

, VPP, A9 and RP#)

CC

9

(2,3)

(2,3)

NOTICE: This datasheet contains preliminary information on
new products in production. Do not finalize a design with
this information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.

* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.

NOTES:

1. Operating temperature is for commercial product
defined by this specification.

2. Minimum DC voltage is –0.5 V on input/output pins.

During transitions, this level may undershoot to –2.0 V
for periods
<20 ns. Maximum DC voltage on input/output pins is
V

(2)

(2)
(4)

+ 0.5 V which, during transitions, may overshoot to

CC

V

+ 2.0 V for periods <20 ns.

CC

3. Maximum DC voltage on V
for periods <20 ns. Maximum DC voltage on RP# or A
may overshoot to 13.5 V for periods <20 ns.

4. Output shorted for no more than one second. No more
than one output shorted at a time.

may overshoot to +14.0 V

PP

9

4.2 Commercial Operating Conditions

Table 10. Commercial Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Units

T

A

V

CC

NOTES:

1. 10% V

2. 5% V

28

Operating Temperature 0 +70 °C

3.3 V VCC Supply Voltage (± 0.3 V) 3.0 3.6 Volts
5 V VCC Supply Voltage (10%) 1 4.50 5.50 Volts
5 V VCC Supply Voltage (5%) 2 4.75 5.25 Volts

specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration.

CC

specifications apply to the 60 ns version in its high-speed test configuration.

CC

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.2.1 APPLYING VCC VOLTAGES

When applying V
may be required before initiating device operat ion,
depending on the V

slower than 1V/100 µs (0.01 V/µs) t hen no delay is

VCC Ramp Rate Required Timing

≤ 1V/100 µs No delay required.
> 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3 V and 5 V operation, the system should first transition V
and then to the new voltage. Any time the V
pending or in progress.

3. These guidelines must be followed for any V

voltage to the device, a delay

CC

ramp rate. If VCC ramps

CC

operations, command writes, program operations, and erase operations. This delay
measured beginning from the time V
and 4.5 V for 5 V operation).

supply drops below V

CC

transition from GND.

CC

required. If V
V/µs), then a delay of 2 µs is required before
initiating device operation. RP# = GND is
recommended during power-up to protect against
spurious write signals when V
and V

CCMIN

reaches V

CC

CCMIN

ramps faster than 1V/100 µs (0.01

CC

is between V

.

(3.0 V for 3.3 ± 0.3 V operation;

CCMIN

from the existing voltage range to GND,

CC

, the chip may be reset, aborting any operations

CC

4.3 Capacitance

TA = 25 °C, f = 1 MHz

Symbol Parameter Note Typ Max Unit Conditions

C

IN

C

OUT

NOTES:

1. Sampled, not 100% tested.

2. For the 28F002B, address pin A

Input Capacitance 1 6 8 pF VIN = 0 V
Output Capacitance 1, 2 10 12 pF V

follows the C

10

capacitance numbers.

OUT

OUT

= 0 V

LKO

is

SEE NEW DESIGN RECOMMENDATIONS

29

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.4 DC Characteristics—Commercial

Prod

BV-80

BV-120

BV-60

Sym Parameter V

3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions

CC

Note Typ Max Typ Max

I

Input Load Current 1 ± 1.0 ± 1.0 µA

IL

I

Output Leakage Current 1 ± 10 ± 10 µA

LO

I

V

Standby Current 1,3 0.4 1.5 0.8 2.0 mA

CCS

CC

60 110 50 130 µA

I

VCC Deep Power-Down

CCD

1 0.2 8 0.2 8 µA

Current

VCC Read Current for

I

CCR

Word or Byte

1,5,6 15 30 50 60 mA

15 30 55 65 mA

V

Program Current for

CC

I

CCW

Word or Byte

1,4 13 30 30 50 mA

10 25 30 45 mA

I

VCC Erase Current 1,4 13 30 18 35 mA

CCE

10 25 18 30 mA

= V

V

CC

V

IN

V

CC

V

IN

V

CC

Max

CC

= VCC or GND

= V

Max

CC

= VCC or GND

= V

Max

CC

CE# = RP# = BYTE# =

WP# = V

V

CC

CE# = RP# = V

= V

CC

Max

IH

±

CC

0.2 V
= V

V

CC

V

IN

Max

CC

= VCC or GND

RP# = GND ± 0.2 V

CMOS INPUTS

= V

CC

Max

V

CC

CE# = GND, OE# = V
f = 10 MHz (5 V),

5 MHz (3.3 V)

= 0 mA, Inputs =

I

OUT

GND ± 0.2 V or V

CC

± 0.2 V

TTL INPUTS

= V

V

CC

CE# = V

Max

CC

, OE# = V

IL

IH

f = 10 MHz (5 V),

5 MHz (3.3 V)

= 0 mA, Inputs =

I

OUT

or V

V

IL

IH

1 (at 5 V)

= V

V

PP

PPH

Program in Progress

2 (at 12 V)

= V

PP

PPH

V
Program in Progress

1 (at 5 V)

= V

V

PP

PPH

Block Erase in Progress

= V

V

PP

2 (at 12 V)

PPH

Block Erase in Progress

CC

30

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.4 DC Characteristics—Commercial (Continued)

Prod

BV-80

BV-120

BV-60

Sym Parameter V

3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions

CC

Note Typ Max Typ Max

V

Erase Suspend

CC

I

CCES

I

PPS

I

PPD

I

PPR

I

PPW

Current
V

Standby Current 1 ± 0.5 ± 15 ± 0.5 ± 10 µA V

PP

V

Deep Power-Down

PP

Current
V

Read Current 1 50 200 30 200 µA VPP ≥ V

PP

V

Program Current for

PP

1,2 3 8.0 5 10 mA

1 0.2 5.0 0.2 5.0 µA RP# = GND ± 0.2 V

1,4 13 30 13 25 mA

Word or Byte

825820

I

VPP Erase Current 1,4 13 30 10 20 mA

PPE

825515

VPP Erase

I

PPES

Suspend Current

I

RP# Boot Block Unlock

RP#

1 50 200 30 200 µA

1,4 500 500 µA RP# = V

Current

I

ID

A9 Intelligent
Identifier Current

1,4 500 500 µA A

CE# = V

IH

Block Erase Suspend

< V

= V

PPH

PPH

PPH

2

2

1 (at 5 V)

PP

V

PP

Program in Progress

= V

V

PP

2 (at 12 V)

PPH

Program in Progress

= V

PPH

1 (at 5 V)

V

PP

Block Erase in Progress

= V

V

PP

2 (at 12 V)

PPH

Block Erase in Progress
V

= V

PP

PPH

Block Erase Suspend in

Progress

HH

= V

9

ID

SEE NEW DESIGN RECOMMENDATIONS

31

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.4 DC Characteristics—Commercial (Continued)

Prod

BV-80

BV-120

BV-60

Sym Parameter V

3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions

CC

Note Min Max Min Max

V

A9 Intelligent Identifier

ID

11.4 12.6 11.4 12.6 V

Voltage

V

Input Low Voltage –0.5 0.8 –0.5 0.8 V

IL

+

V

V

Input High Voltage 2.0

IH

V

Output Low Voltage 0.45 0.45 V

OL

CC

0.5V

VOH1 Output High Voltage (TTL) 2.4 2.4 V

VOH2 Output High Voltage (CMOS)

0.85 ×
V

CC

V

CC–

0.4V

V

VPP Lock-Out Voltage 3 0.0 1.5 0.0 1.5 V Total Write Protect

PPLK

V

1VPP (Prog/Erase Operations) 4.5 5.5 4.5 5.5 V V

PPH

V

2VPP (Prog/Erase Operations) 11.4 12.6 11.4 12.6 V V

PPH

V

V

Erase/Prog Lock Voltage 8 2.0 2.0 V

CC

LKO

V

HH

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

product versions (packages and speeds).

2. I

CCES

I

CCES

3. Block erases and word/byte programs are inhibited when V
V

PPLK

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

6. CMOS Inputs are either V

7. For the 28F002B, address pin A

8. For all BV/CV parts, V

RP# Unlock Voltage 11.4 12.6 11.4 12.6 V Boot Block Unlock

= 5.0 V, T = +25 °C. These currents are valid for all

CC

is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of
and I

.

CCR

.

to less than 1 mA typical, in static operation.

± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.

CC

10

= 2.0 V for both 3.3 V and 5 V operations.

LKO

CCR

follows the C

capacitance numbers.

OUT

= V

PP

, and not guaranteed in the range between V

PPLK

2.0

0.85 ×
V

CC

V

CC–

0.4V

VCC +

0.5V

V

V

CC

I

OL

V

CC

I

OH

V

CC

V

I

OH

V

CC

V

I

OH

PP

PP

= V

Min

CC

= 5.8 mA

= V

Min

CC

= –2.5 mA

= V

Min

CC

= –2.5 mA

= V

Min

CC

= –100 µA

at 5 V
at 12 V

PPH

1 and

32

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.0

1.5

0.0

NOTE:

AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.

TEST POINTSINPUT

1.5

OUTPUT

0530_12

Figure 12. 3.3 V Inputs and Measurement Points

2.4
INPUT OUTPUT

0.45

NOTE:

AC test inputs are driven at VOH (2.4 V
and VIL (0.8 V

) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.

TTL

2.0
TEST POINTS

0.8 0.8

) for a logic “1” and VOL (0.45 V

TTL

) for a logic “0.” Input timing begins at VIH (2.0 V

TTL

2.0

0530_13

Figure 13. 5 V Inputs and Measurement Points

V

CC

Test Configuration Component Values

Test Configuration CL (pF) R1 (Ω)R2 (Ω)

R

1

3.3 V Standard Test 50 990 770
5 V Standard Test 100 580 390

DEVICE
UNDER

TEST

C

L

R

2

OUT

5 V High-Speed Test 30 580 390

NOTE: CL includes jig capacitance.

TTL

)

NOTE: See table for component values.

0530_14

Figure 14. Test Configuration

SEE NEW DESIGN RECOMMENDATIONS

33

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.5 AC Characteristics—Commercial

Prod BV-60

Sym Parameter V

CC

3.3 ± 0.3 V

(5)

5 V ± 5%

Load 50 pF 30 pF 100 pF

Note Min Max Min Max Min Max

t

Read Cycle Time 110 60 70 ns

AVAV

t

Address to Output Delay 110 60 70 ns

AVQV

t

CE# to Output Delay 2 110 60 70 ns

ELQV

t

RP# to Output Delay 0.8 0.45 0.45 µs

PHQV

t

OE# to Output Delay 2 65 30 35 ns

GLQV

t

CE# to Output in Low Z 3 0 0 0 ns

ELQX

t

CE# to Output in High Z 3 45 20 20 ns

EHQZ

t

OE# to Output in Low Z 3 0 0 0 ns

GLQX

t

OE# to Output in High Z 3 45 20 20 ns

GHQZ

t

Output Hold from Address,

OH

CE#, or OE# Change,

3000ns

Whichever Occurs First

t

ELFL

CE# Low to BYTE# High or

t

ELFH

Low

t

Address to BYTE# High or

AVFL

3000ns

3555ns

Low

t

FLQV

BYTE# to Output Delay 3,4 110 60 70 ns

t

FHQV

t

BYTE# Low to Output in

FLQZ

High Z

t

Reset Pulse Width Low 8 150 60 60 ns

PLPH

t

RP# Low to Output High-Z 150 60 60 ns

PLQZ

3452025ns

(6)

5 V ± 10%

(7)

Unit

34

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.5 AC Characteristics—Commercial (Continued)

Prod BV-80 BV-120

Sym Parameter VCC3.3 ± 0.3V

(5)

Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

t

Read Cycle Time 150 80 180 120 ns

AVAV

t

Address to Output Delay 150 80 180 120 ns

AVQV

t

CE# to Output Delay 2 150 80 180 120 ns

ELQV

t

RP# to Output Delay 0.8 0.45 0.8 0.45 µs

PHQV

t

OE# to Output Delay 2 90 40 90 40 ns

GLQV

t

CE# to Output in Low Z 3 0 0 0 0 ns

ELQX

t

CE# to Output in High Z 3 45 20 45 25 ns

EHQZ

t

OE# to Output in Low Z 3 0 0 0 0 ns

GLQX

t

OE# to Output in High Z 3 45 20 45 20 ns

GHQZ

t

Output Hold from Address,

OH

CE#, or OE# Change,

30 0 0 0 ns

Whichever Occurs First

t

ELFL

CE# Low to BYTE# High or

t

ELFH

Low

t

Address to BYTE# High or

AVFL

30 0 0 0 ns

35555ns

Low

t

FLQV

BYTE# to Output Delay 3,4 150 80 180 120 ns

t

FHQV

t

BYTE# Low to Output in

FLQZ

High Z

t

Reset Pulse Width Low 8 150 60 150 60 ns

PLPH

t

RP# Low to Output High-Z 150 60 150 60 ns

PLQZ

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t

3. Sampled, but not 100% tested.

4. t

, BYTE# switching low to valid output delay will be equal to t

FLQV

5. See

Test Configuration

6. See

Test Configuration

7. See

Test Configuration

8. The specification t

CE–tOE

(Figure 14), 3.3 V Standard Test component values.
(Figure 14), 5 V High-Speed Test component values.
(Figure 14), 5 V Standard Test component values.

is the minimum time that RP# must be held low in order to product a valid reset of the device.

PLPH

3 60306030ns

after the falling edge of CE# without impact on tCE.

AVQV

5V ± 10%

, measured from the time DQ15/A–1 becomes valid.

(7)

3.3 ± 0.3V

(5)

5V ± 10%

(7)

Unit

SEE NEW DESIGN RECOMMENDATIONS

35

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

V

IH

ADDRESSES (A)

V

IL

V

IH

CE# (E)

V

IL

V

IH

OE# (G)

V

IL

V

IH

WE# (W)

V

IL

V

OH

DATA (D/Q)

V

OL

V

IH

RP#(P)

V

IL

ADDRESSES (A)

CE# (E)

OE# (G)

BYTE# (F)

DATA (D/Q)

(DQ0-DQ7)

DATA (D/Q)

(DQ8-DQ14)

(DQ15/A-1)

Device and

Address Selection

Data

Valid

Address Stable

t

AVAV

t

GLQV

t

GLQX

t

High Z

t

PHQV

t

ELQX

t

AVQV

ELQV

Valid Output

Figure 15. AC Waveforms for Read Operations

t

AVAV

Data Output

on DQ0-DQ7

on DQ15

Data

Valid

Standby

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

High Z

V

OL

V

OH

High Z

V

OL

V

OH

High Z

V

OL

Device

Address Select ion

Address Stable

t

AVFL

t

ELFL

t

ELQX

t

AVQV

t

FLQZ

t

GLQV

t

ELQV

t

GLQX

Data Output

on DQ8-DQ14

Data Output

Figure 16. BYTE# Timing Diagram for Read Operations

t

OH

t

OH

Data Output

on DQ0-DQ7

t

AVQV

Address Input

Standby

t

EHQZ

t

GHQZ

High Z

High Z

High Z

High Z

t

EHQZ

t

GHQZ

0530_15

0530_16

36

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.6 AC Characteristics—WE#-Controlled Write Operations

Prod BV-60

Sym Parameter V

t

AVAV

t

PHWL

t

ELWL

t

PHHWH

t

VPWH

t

AVWH

t

DVWH

t

WLWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

t

WHQV1

t

WHQV2

t

WHQV3

t

WHQV4

t

QVVL

t

QVPH

t

PHBR

Write Cycle Time 110 60 70 ns
RP# Setup to WE# Going Low 0.8 0.45 0.45 µs
CE# Setup to WE# Going Low 0 0 0 ns
Boot Block Lock Setup to WE#

Going High
VPP Setup to WE# Going High

Address Setup to WE# Going
High

Data Setup to WE# Going High 4 90 50 50 ns
WE# Pulse Width 90 50 50 ns
Data Hold Time from WE# High 4 0 0 0 ns
Address Hold Time from WE#

High
CE# Hold Time from WE# High 0 0 0 ns
WE# Pulse Width High 20 10 20 ns
Duration of Word/Byte Program 2,5 6 6 6 µs

Duration of Erase (Boot) 2,5,6 0.3 0.3 0.3 s
Duration of Erase (Parameter) 2,5 0.3 0.3 0.3 s
Duration of Erase (Main) 2,5 0.6 0.6 0.6 s
VPP Hold from Valid SRD 5,8 0 0 0 ns
RP# VHH Hold from Valid SRD 6,8 0 0 0 ns
Boot-Block Lock Delay 7,8 200 100 100 ns

3.3 ± 0.3 V

CC

Load 50 pF 30 pF 100 pF
Note Min Max Min Max Min Max

6,8 200 100 100 ns

5,8 200 100 100 ns

3905050ns

3000ns

(9)

5 V ± 5%

(1)

—Commercial

(10)

5 V ± 10%

(10)

Unit

SEE NEW DESIGN RECOMMENDATIONS

37

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.6 AC Characteristics—WE#-Controlled Write Operations

(Continued)

Prod BV-80 BV-120

Sym Parameter VCC3.3 ±0.3V

Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

t

AVAV

t

PHWL

t

ELWL

t

PHHWH

t

VPWH

t

AVWH

t

DVWH

t

WLWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

t

WHQV1

t

WHQV2

t

WHQV3

t

WHQV4

t

QVVL

t

QVPH

t

PHBR

Write Cycle Time 150 80 180 120 ns
RP# Setup to WE# Going

0.8 0.45 0.8 0.45 µs

Low
CE# Setup to WE# Going

0000ns

Low
Boot Block Lock Setup to

6,8 200 100 200 100 ns

WE# Going High
VPP Setup to WE# Going

High
Address Setup to WE#

5,8 200 100 200 100 ns

3 120 50 150 50 ns

Going High
Data Setup to WE# Going

4 120 50 150 50 ns

High
WE# Pulse Width 120 50 150 50 ns
Data Hold Time from

40 0 0 0 ns

WE# High
Address Hold Time from

30 0 0 0 ns

WE# High
CE# Hold Time from WE#

0000ns

High
WE# Pulse Width High 30 30 30 30 ns
Word/Byte Program Time 2,5 6 6 6 6 µs

Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s
Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s
Erase Duration (Main) 2,5 0.6 0.6 0.6 0.6 s
VPP Hold from Valid SRD 5,8 0 0 0 0 ns

RP# VHH Hold from Valid
SRD

6,8 0 0 0 0 ns

Boot-Block Lock Delay 7,8 200 100 200 100 ns

(9)

5V±10%

(11)

3.3 ± 0.3V

(1)

—Commercial

(9)

5V±10%

(11)

Unit

38

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to

Characteristics

during read mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.

3. Refer to command definition table for valid A

4. Refer to command definition table for valid D

. (Table 7)

IN

. (Table 7)

IN

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).

6. For boot block program/erase, RP# should be held at V
successfully.

7. Time t

is required for successful locking of the boot block.

PHBR

or WP# should be held at VIH until operation completes

HH

8. Sampled, but not 100% tested.

9. See

10. See

11. See

Test Configuration
Test Configuration
Test Configuration

ADDRESSES (A)

(Figure 14), 3.3 V Standard Test component values.
(Figure 14), 5 V High-Speed Test component values.
(Figure 14), 5 V Standard Test component values.

12 3 4 65

V

V

V

CE# (E)

V

V

OE# (G)

V

V

WE# (W)

V

V

DATA (D/Q)

V

V

6.5V

V

RP# (P)

V

V

WP#

V

V
V1

V (V)

V

PP

V

IH

IL
IH

IL
IH

IL
IH

IL

IH

IL

HH

IH

IL
IH

IL

PPH

PPH
PPLK

IL

t

ELWL

High Z

2

t

PHWL

A

t

IN

AVAV

A

IN

t

AVWH

t

WHEH

t

WHWL

t

WLWH

t

DVWH

t

WHDX

D

IN

D

IN

t

t

PHHWH

VPWH

t

WHAX

t

WHQV1,2,3,4

Valid
SRD

t

QVPH

t

QVVL

D

IN

NOTES:

1. V

Power-Up and Standby.

CC

2. Write program or Erase Set-Up Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)

SEE NEW DESIGN RECOMMENDATIONS

AC

0530_17

39

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.7 AC Characteristics—CE#-Controlled Write Operations

Prod BV-60

Sym Parameter V

t

AVAV

t

PHEL

Write Cycle Time 110 60 70 ns
RP# High Recovery to CE#

Going Low

t

WLEL

t

PHHEH

WE# Setup to CE# Going Low 0 0 0 ns
Boot Block Lock Setup to CE#

Going High

t

VPEH

t

AVEH

VPP Setup to CE# Going High

Address Setup to CE# Going
High

t

DVEH

t

ELEH

t

EHDX

t

EHAX

Data Setup to CE# Going High 4 90 50 50 ns
CE# Pulse Width 90 50 50 ns
Data Hold Time from CE# High 4 0 0 0 ns
Address Hold Time from CE#

High

t

EHWH

t

EHEL

t

EHQV1

WE # Hold Time from CE# High 0 0 0 ns
CE# Pulse Width High 20 10 20 ns
Duration of Word/Byte

Programming Operation

t

EHQV2

t

EHQV3

t

EHQV4

t

QVVL

t

QVPH

t

PHBR

Erase Duration (Boot)
Erase Duration (Param)
Erase Duration(Main)
VPP Hold from Valid SRD

RP# V

Hold from

HH

Valid SRD
Boot-Block Lock Delay 7,8 200 100 100 ns

3.3 ± 0.3 V

CC

Load 50 pF 30 pF 100 pF
Note Min Max Min Max Min Max

0.8 0.45 0.45

6,8 200 100 100 ns

5,8 200 100 100 ns

3905050ns

3000ns

2,5 6 6 6 µs

2,5,6 0.3 0.3 0.3 s

2,5 0.3 0.3 0.3 s
2,5 0.6 0.6 0.6 s
5,8 0 0 0 ns
6,8 0 0 0 ns

(9)

5 V ± 5%

(1, 12)

—Commercial

(10)

5 V ± 10%

(11)

Unit

µs

40

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.7 AC Characteristics—CE#-Controlled Write Operations

(Continued)

Prod BV-80 BV-120

Sym Parameter VCC3.3 ± 0.3V

Load 50 pF 100 pF 50 pF 100 pF

Notes Min Max Min Max Min Max Min Max

t

AVAV

t

PHEL

t

WLEL

t

PHHEH

t

VPEH

t

AVEH

t

DVEH

t

ELEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

EHQV1

t

EHQV2

t

EHQV3

t

EHQV4

t

QVVL

t

QVPH

t

PHBR

Write Cycle Time
RP# High Recovery to

CE# Going Low
WE# Setup to CE# Going

Low
Boot Block Lock Setup to

CE# Going High
VPP Setup to CE# Going

High
Address Setup to CE#

Going High
Data Setup to CE# Going

High
CE# Pulse Width
Data Hold Time from CE#

High
Address Hold Time from

CE# High
WE # Hold Time from

CE# High
CE# Pulse Width High
Duration of Word/Byte

Programming Operation

Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s
Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s
Erase Duration(Main) 2,5 0.6 0.6 0.6 0.6 s
VPP Hold from Valid SRD 5,8 0 0 0 0 ns

RP# V
Valid SRD

Boot-Block Lock Delay

Hold from

HH

150 80 180 120 ns

0.8 0.45 0.8 0.45 µs

0000ns

6,8 200 100 200 100 ns

5,8 200 100 200 100 ns

3 120 50 150 50 ns

4 120 50 150 50 ns

120 50 150 50 ns

40 0 0 0 ns

30 0 0 0 ns

0000ns

30 30 30 30 ns

2,56666µs

6,8 0 0 0 0 ns

7,8 200 100 200 100 ns

(9)

5V±10%

(11)

3.3 ± 0.3V

(1, 12)

—Commercial

(9)

5V±10%

(11)

Unit

SEE NEW DESIGN RECOMMENDATIONS

41

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

NOTES:

See

AC Characteristics—WE#-Controlled Write Operations

12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.

12 3 4 65

V

WE# (W)

OE# (G)

CE# (E)

IH

V

IL

V

IH

V

IL

t

WLEL

V

IH

V

IL

V

IH

V

IL

A

t

AVAV

IN

t

EHWH

t

EHEL

t

ADDRESSES (A)

t

t

D

IN

V

DATA (D/Q)

V
V

6.5V

V

RP# (P)

V
V

WP#

V
V

V1

V (V)

V

PP

V

IH

IL

HH

IH

IL
IH

IL

PPH
PPH
PPLK

IL

High Z

2

t

PHEL

NOTES:

1. V

Power-Up and Standby.

CC

2. Write program or Erase Set-Up Command.

3. Write Valid Address and Data (Program) or Erase Confirm Command.

4. Automated Program or Erase Delay.

5. Read Status Register Data.

6. Write Read Array Command.

Figure 18. Alternate AC Waveforms for Write Operations (CE#–Controlled Writes)

for notes 1 through 11.

A

IN

t

AVEH

ELEH

DVEH

EHDX

D

IN

t

PHHEH

t

VPEH

t

EHAX

t

EHQV1,2,3,4

Valid
SRD

t

QVPH

t

QVVL

D

IN

0530_18

42

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.8 Erase and Program Timings—Commercial

TA = 0 °C to +70 °C

V

PP

V

CC

Parameter Typ Max Typ Max Typ Max Typ Max Unit

Boot/Parameter Block Erase Time 0.84 7 0.8 7 0.44 7 0.34 7 s
Main Block Erase Time 2.4 14 1.9 14 1.3 14 1.1 14 s
Main Block Program Time (Byte) 1.7 1.8 1.6 1.2 s
Main Block Program Time (Word) 1.1 0.9 0.8 0.6 s
Byte Program Time 10 10 8 8 µs

Word Program Time 13 13 8 8 µs

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value

independent of V

3. Typical conditions are +25 °C with V

V

= 5.0 V, VPP = 12.0 V typically results in a 60% reduction in programming time.

CC

4. Contact your Intel representative for information regarding maximum byte/word program specifications.

and VPP. See Note 3 for typical conditions.

CC

and VPP at the center of the specified voltage range. Production programming using

CC

5 V ± 10% 12 V ± 5%

3.3 ± 0.3 V

5 V ± 10% 3.3 ± 0.3 V 5 V ± 10%

4.9 Extended Operating Conditions

Table 11. Extended Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Units

T

A

V

CC

NOTES:

1. AC specifications are valid at both voltage ranges.

2. 10% V

Operating Temperature –40 +85 °C

3.3 V VCC Supply Voltage (± 0.3 V) 1 3.0 3.6 Volts
5 V VCC Supply Voltage (10%) 2 4.50 5.50 Volts

See

DC Characteristics

specifications apply to 80 ns and 120 ns versions in their standard test configuration.

CC

tables for voltage range-specific specifications.

SEE NEW DESIGN RECOMMENDATIONS

43

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.9.1 APPLYING VCC VOLTAGES

required. If V

ramps faster than 1V/100 µs (0.01

CC

V/µs), then a delay of 2 µs is required before

When applying V
may be required before initiating device operat ion,
depending on the V

slower than 1V/100 µs (0.01 V/µs) t hen no delay is

voltage to the device, a delay

CC

ramp rate. If VCC ramps

CC

initiating device operation. RP# = GND is
recommended during power-up to protect against
spurious write signals when V
and V

CCMIN

.

is between V

CC

VCC Ramp Rate Required Timing

≤ 1V/100 µs No delay required.
> 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read

operations, command writes, program operations, and erase operations. This delay
measured beginning from the time V

reaches V

CC

( 3.0 V for 3.3 ± 0.3 V operation;

CCMIN

and 4.5 V for 5 V operation).

NOTES:

1. These requirements must be strictly followed to guarantee all other read and write specifications.

2. To switch between 3.3 V and 5 V operation, the system should first transition V

and then to the new voltage.
pending or in progress.

3. These guidelines must be followed for any V

Any time the VCC supply drops below V

transition from GND.

CC

CCMIN

from the existing voltage range to GND,

CC

, the chip may be reset, aborting any operations

4.10 Capacitance

TA = 25 °C, f = 1 MHz

Symbol Parameter Note Typ Max Unit Conditions

C

IN

C

OUT

NOTE:

1. Sampled, not 100% tested.

Input Capacitance 1 6 8 pF VIN = 0V
Output Capacitance 1 10 12 pF V

OUT

= 0V

LKO

is

44

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

CC

4.11 DC Characteristics—Extended Temperature Operations

Prod TBV-80 TBV-80

TBE-120

Sym Parameter V

Notes Typ Max Typ Max

I

Input Load Current 1 ± 1.0 ± 1.0 µA

IL

I

Output Leakage Current 1 ± 10 ± 10 µA

LO

V

I

CCS

I

CCD

I

CCR

Standby Current

VCC Deep Power-Down
Current

VCC Read Current for
Word or Byte

1,5,6 15 30 50 65 mA

3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions

CC

V

CC

V

IN

V

CC

V

IN

1,3 60 110 70 150 µA

0.4 1.5 0.8 2.5 mA

1 0.2 8 0.2 8 µA

15 30 55 70 mA

CMOS Levels

V

CC

CE# = RP# = WP# =

TTL Levels

V

CC

CE# = RP# = BYTE#

VCC = V
V

IN

RP# = GND ± 0.2 V

CMOS INPUTS

V

CC

CE = V
f = 10 MHz (5 V)

I

OUT

Inputs = GND ± 0.2 V

TTL INPUTS

V

CC

CE# = V
f = 10 MHz (5 V)

I

OUT

Inputs = V

= VCCMax

= VCC or GND

= V

Max

CC

= VCC or GND

= V

Max

CC

V

± 0.2 V

CC

= V

Max

CC

= V

IH

Max

CC

= VCC or GND

= V

Max

CC

IL

5 MHz (3.3 V)

= 0 mA

± 0.2 V

or V

CC

= V

Max

CC

IL

5 MHz (3.3 V)

= 0 mA

or V

IL

IH

SEE NEW DESIGN RECOMMENDATIONS

45

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

PP

PP

PP

4.11 DC Characteristics—Extended Temperature Operations (Continued)

Prod TBV-80 TBV-80

TBE-120

Sym Parameter V

I

I

I

I

I

I
I

I

I

I

VCC Program Current

CCW

for Word or Byte

VCC Erase Current

CCE

VCC Erase Suspend

CCES

Current

V

Standby Current

PPS

PPD

PPR

PPW

PPE

PPES

RP#

PP

VPP Deep Power-Down
Current
VPP Read Current

VPP Program Current
for Word or Byte

VPP Erase Current

VPP Erase Suspend
Current

RP# Boot Block Unlock
Current

I

A9 Intelligent Identifier

ID

Current

Note Typ Max Typ Max

3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions

CC

V

= V

1 (at 5 V)

1,4 13 30 30 50 mA

10 25 30 45 mA

1,4 13 30 22 45 mA

PPH

Program in Progress

= V

= V

2 (at 12 V)

PPH

1 (at 5 V)

PPH

V
Program in Progress

V
Block Erase in

Progress

= V

10 25 18 40 mA

V
Block Erase in

2 (at 12 V)

PPH

Progress

1,2 3 8.0 5 12.0 mA

1 ± 5 ± 15 ± 5 ± 15 µA V

CE# = V
Block Erase Suspend
V

PP

PP

= V

< V

IH

PPH
PPH

1 (at 5 V)

2

1 0.2 10 0.2 10 µA RP# = GND ± 0.2 V

1 50 200 50 200 µA V

1,4 13 30 13 30 mA

8 25 8 25 mA

1,4 13 30 15 25 mA

≥ V

2

PPH

PP

V

= V

= V
= V

1 (at 5 V)

PPH

2 (at 12 V)

PPH

1 (at 5 V)

PPH

PP

V

PP

V
Block Erase in

Progress

= V

8251020mA

V
Block Erase in

2 (at 12 V)

PPH

Progress

V

= V

PP

1 50 200 50 200 µA

PPH

Block Erase Suspend

in Progress

1,4 500 500 µA

1,4 500 500 µA A

RP# = V
V

9

= V

HH

= 12 V

ID

46

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

CC

PP

4.11 DC Characteristics—Extended Temperature Operations (Continued)

Prod TBV-80 TBV-80

TBE-120

Sym Parameter V

Notes Typ Max Typ Max

A9 Intelligent Identifier

V

ID

Voltage

V

Input Low Voltage –0.5 0.8 –0.5 0.8 V

IL

V

Input High Voltage 2.0

IH

V

Output Low Voltage 0.45 0.45 V

OL

VOH1 Output High Voltage (TTL) 2.4 2.4 V

VOH2 Output High Voltage

(CMOS)

V

Lock-Out Voltage

V

V
V
V

V

PP

PPLK

1VPP during Program/Erase 4.5 5.5 4.5 5.5 V VPP at 5 V

PPH

Operations

2

PPH

V

LKO

HH

Program/Erase

Lock Voltage
RP# Unlock Voltage 11.4 12.6 11.4 12.6 V

3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions

CC

11.4 12.6 11.4 12.6 V

V

CC

±

0.5V

0.85

×

V

CC

V

CC–

0.4V

3 0.0 1.5 0.0 1.5 V Complete Write

11.4 12.6 11.4 12.6 V VPP at 12 V

8 2.0 2.0 V

2.0

0.85

×

V

CC

V

CC–

0.4V

V

CC

±

0.5V

V

= V

V

CC

= 5.8 mA (5 V)

I

OL

2 mA (3.3 V)

= 12V

V

PP

= V

V

CC

= –2.5 mA

I

OH

= V

V

CC

V

V

= –2.5 mA

I

OH

= V

V

CC

= –100 µA

I

OH

Protection

= 12 V

V
Boot Block Program/

Erase

CC

CC

CC

CC

Min

Min

Min

Min

SEE NEW DESIGN RECOMMENDATIONS

47

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

product versions (packages and speeds).

2. I

is specified with device de-selected. If device is read while in erase suspend, current draw is sum of I

CCES

3. Block erases and word/byte programs inhibited when V
V

.

PPLK

= V

PP

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

6. CMOS Inputs are either V

7. For the 28F002B address pin A

8. For all BV/CV parts, V

± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.

CC

follows the C

10

= 2.0 V for 3.3 V and 5.0 V operations.

LKO

to less than 1 mA typical, in static operation.

CCR

capacitance numbers.

OUT

3.0

= 5.0 V, T = +25 °C. These currents are valid for all

CC

, and not guaranteed in the range between V

PPLK

CCES

and I

PPH

1 and

CCR

.

1.5

TEST POINTSINPUT

1.5

OUTPUT

0.0

NOTE:

0530_12

AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.

Figure 19. 3.3 V Input Range and Measurement Points

2.4
INPUT OUTPUT

0.45

NOTE:

AC test inputs are driven at VOH (2.4 V
and VIL (0.8 V

). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.

TTL

2.0
TEST POINTS

0.8 0.8

) for a logic “1” and VOL (0.45 V

TTL

) for a logic “0.” Input timing begins at VIH (2.0 V

TTL

2.0

0530_13

Figure 20. 5 V Input Range and Measurement Points

V

CC

Test Configuration Component Values

Test Configuration CL (pF) R1 (Ω)R2 (Ω)

R

1

3.3 V Standard Test 50 990 770
5 V Standard Test 100 580 390

DEVICE

UNDER

TEST

OUT

C

L

R

2

NOTE: CL includes jig capacitance.

TTL

)

NOTE: See table for component values.

Figure 21. Test Configuration

48

0530_14

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.12 AC Characteristics—Read Only Operations

Prod TBV-80 TBV-80

Symbol Parameter V

CC

Load 50 pF 100 pF

Notes Min Max Min Max

t

AVAV

t

AVQV

t

ELQV

t

PHQV

t

GLQV

t

ELQX

t

EHQZ

t

GLQX

t

GHQZ

t

OH

Read Cycle Time 110 80 ns
Address to Output Delay 110 80 ns
CE# to Output Delay 2 110 80 ns
RP# to Output Delay 0.8 0.45 µs
OE# to Output Delay 2 65 40 ns
CE# to Output in Low Z 3 0 0 ns
CE# to Output in High Z 3 45 25 ns
OE# to Output in Low Z 3 0 0 ns
OE# to Output in High Z 3 45 25 ns
Output Hold from Address, CE#,

30 0 ns
or OE# Change, Whichever
Occurs First

t

ELFL

t

ELFH

t

AVFL

t

FLQV

t

FHQV

t

FLQZ

t

PLPH

t

PLQZ

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t

3. Sampled, but not 100% tested.

4. t

FLQV

5. See

6. See

7. The specification t

CE# Low to BYTE# High or Low 3

Address to BYTE# High or Low 3 5 5 ns
BYTE# to Output Delay 3,4 110 80 ns

BYTE# Low to Output in High Z 3 45 30 ns
Reset Pulse Width 7 150 60

RP# Low to Output High-Z 150 60

after the falling edge of CE# without impact on tCE.

CE–tOE

, BYTE# switching low to valid output delay will be equal to t

Test Configuration
Test Configuration

(Figure 21), 3.6 V and 3.3 ± 0.3 V Standard Test component values.
(Figure 21), 5 V Standard Test component values.

is the minimum time that RP# must be held low in order to product a valid reset of the device.

PLPH

3.3 ± 0.3 V

00

, measured from the time DQ15/A–1 becomes valid.

AVQV

(1)

—Extended Temperature

TBE-120

(5)

5 V ± 10%

(6)

Unit

ns

ns
ns

SEE NEW DESIGN RECOMMENDATIONS

49

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.13 AC Characteristics—WE#-Controlled Write Operations

Extended Temperature

Prod TBV-80 TBV-80

Sym Parameter V

t

AVAV

t

PHWL

t

ELWL

t

PHHWH

t

VPWH

t

AVWH

t

DVWH

t

WLWH

t

WHDX

t

WHAX

t

WHEH

t

WHWL

t

WHQV1

t

WHQV2

t

WHQV3

t

WHQV4

t

QVVL

t

QVPH

t

PHBR

Write Cycle Time 110 80 ns
RP# High Recovery to WE# Going Low 0.8 0.45 µs
CE# Setup to WE# Going Low 0 0 ns
Boot Block Lock Setup to WE# Going High 6,8 200 100 ns
VPP Setup to WE# Going High 5,8 200 100 ns
Address Setup to WE# Going High 3 90 60 ns
Data Setup to WE# Going High 4 70 60 ns
WE# Pulse Width 90 60 ns
Data Hold Time from WE# High 4 0 0 ns
Address Hold Time from WE# High 3 0 0 ns
CE# Hold Time from WE# High 0 0 ns
WE# Pulse Width High 20 20 ns

Word/Byte Program Time

Erase Duration (Boot)
Erase Duration (Param)
Erase Duration (Main)
VPP Hold from Valid SRD
RP# VHH Hold from Valid SRD

Boot-Block Lock Delay 7,8 200 100 ns

Load 50 pF 100 pF

Notes Min Max Min Max

2,5,8 6 6 µs

2,5,6,8 0.3 0.3 s

2,5,8 0.3 0.3 s
2,5,8 0.6 0.6 s

3.3 ±0.3 V

CC

5,8 0 0 ns
6,8 0 0 ns

(1)

(9)

—

TBE-120

5 V±10%

(10)

Unit

50

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

NOTES:

1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to

Characteristics

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.

3. Refer to command definition table for valid A

4. Refer to command definition table for valid D

5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1)

6. For boot block program/erase, RP# should be held at V
successfully.

7. Time t

8. Sampled, but not 100% tested.

9. See

Test Configuration

10. See

Test Configuration

during read mode.

. (Table 7)

IN

. (Table 7)

IN

is required for successful locking of the boot block.

PHBR

(Figure 21), 3.6 V and 3.3 ± 0.3 V Standard Test component values.
(Figure 21), 5 V Standard Test component values.

or WP# should be held at VIH until operation completes

HH

AC

SEE NEW DESIGN RECOMMENDATIONS

51

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

4.14 AC Characteristics—CE#-Controlled Write Operations

(1, 11)

—

Extended Temperature

Prod TBV-80 TBV-80

TBE-120

Sym Parameter V

CC

3.3 ±0.3 V

(9)

5 V±10%

Load 50 pF 100 pF

Notes Min Max Min Max

t

AVAV

t

PHEL

t

WLEL

t

PHHEH

t

VPEH

t

AVEH

t

DVEH

t

ELEH

t

EHDX

t

EHAX

t

EHWH

t

EHEL

t

EHQV1

t

EHQV2

t

EHQV3

t

EHQV4

t

QVVL

t

QVPH

t

PHBR

NOTES:

See

AC Characteristics—WE#-Controlled Write Operations

11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be
measured relative to the CE# waveform.

Write Cycle Time 110 80 ns
RP# High Recovery to CE# Going Low 0.8 0.45 µs
WE# Setup to CE# Going Low 0 0 ns
Boot Block Lock Setup to CE# Going High 6,8 200 100 ns
VPP Setup to CE# Going High 5,8 200 100 ns
Address Setup to CE# Going High 90 60 ns
Data Setup to CE# Going High 3 70 60 ns
CE# Pulse Width 4 90 60 ns
Data Hold Time from CE# High 0 0 ns
Address Hold Time from CE# High 4 0 0 ns
WE# Hold Time from CE# High 3 0 0 ns
CE# Pulse Width High 20 20 ns
Word/Byte Program Time

Erase Duration (Boot)
Erase Duration (Param)
Erase Duration (Main)

2,5 6 6 µs

2,5,6 0.3 0.3 s

2,5 0.3 0.3 s

2,5 0.6 0.6 s
VPP Hold from Valid SRD 5,8 0 0 ns
RP# V

Hold from Valid SRD 6,8 0 0 ns

HH

Boot-Block Lock Delay 7,8 200 100 ns

for notes 1 through 10.

(10)

Unit

52

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

4.15 Erase and Program Timings—Extended Temperature

TA = –40 °C to +85 °C

V

PP

V

CC

Parameter Typ Max Typ Max Typ Max Typ Max Unit

Boot/Parameter Block Erase Time 0.84 7 0.8 7 0.44 7 0.34 7 s
Main Block Erase Time 2.4 14 1.9 14 1.3 14 1.1 14 s
Main Block Program Time (Byte) 1.7 1.4 1.6 1.2 s
Main Block Program Time (Word) 1.1 0.9 0.8 0.6 s
Byte Program Time 10 10 8 8 µs

Word Program Time 13 13 8 8 µs

NOTES:

1. All numbers are sampled, not 100% tested.

2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value
independent of V

3. Typical conditions are +25 °C with V

V

= 5.0 V, VPP = 12.0 V typically results in a 60% reduction in programming time.

CC

4. Contact your Intel representative for information regarding maximum byte/word program specifications.

and VPP. See Note 3 for typical conditions.

CC

and VPP at the center of the specified voltage range. Production programming using

CC

5 V ± 10% 12 V ± 5%

3.3 ± 0.3 V 5 V ± 10% 3.3 ± 0.3 V 5 V ± 10%

SEE NEW DESIGN RECOMMENDATIONS

53

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

= Compact 48-Lead TSO

5.0 ORDERING INFORMATION

E28F2 00 CV- T 08

T

Operating Temperature
T = Extended Temp
Blank = Commercial Temp

Package

= TSOP

E

= 44-Lead PSOP

PA

= Ext. Temp 44-Lead PSOP

TB

Access Speed
BV/CV:

Top Boot

T =

Bottom Boot

B =
Voltage Options

= (5 or 12 / 3.3 or 5)

V

VCC = 5V

(ns)

(V

PP/VCC

Product line designator

for all Intel Flash product s

Architecture

= Boot Block

Density / Organization

= x8-only (X = 1, 2, 4, 8)

00X

= x8/x16 Selectable (X = 2, 4, 8)

X00

VALID COMBINATIONS:

40-Lead TSOP 44-Lead PSOP 48-Lead TSOP 56-Lead TSOP

Commercial E28F002BVT60 PA28F200BVT60 E28F200CVT60 E28F200BVT60

Extended TE28F002BVT80 TB28F200BVT80 TE28F200CVT80 TE28F200BVT80

E28F002BVB60 PA28F200BVB60 E28F200CVB60 E28F200BVB60
E28F002BVT80 PA28F200BVT80 E28F200CVT80 E28F200BVT80
E28F002BVB80 PA28F200BVB80 E28F200CVB80 E28F200BVB80
E28F002BVT120 PA28F200BVT120
E28F002BVB120 PA28F200BVB120

TE28F002BVB80 TB28F200BVB80 TE28F200CVB80 TE28F200BVB80

B
C

Boot Block

0530_23

Summary of Line Items

V

CC

V

PP

40-Ld 44-Ld 48-Ld 56-Ld 0 °C – –40 °C –

Name 2.7 V 3.3 V 5 V 5 V 12 V TSOP PSOP TSOP TSOP +70 °C +85 °C

28F002BV √√√√√ √ √
28F200BV √√√√ √ √ √ √
28F200CV √√√√ √ √ √

)

54

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

6.0 ADDITIONAL INFORMATION

Related Intel Information

Order

Number

290530
290539
290599
290580
292200
292172
292148
292194
297612

NOTES:

1. Please call the Intel Literature Center at [phone] to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.

4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit Datasheet
Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family Datasheet
AP-642 Designing for Upgrade to Smart 3 Advanced Boot Block Flash Memory
AP-617 Additional Flash Data Protection Using VPP, RP#, and WP#

AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM

AB-65 Migrating SmartVoltage Boot Block Flash Designs to Smart 5 Flash

28F200BV/CV 28F002BV Specification Update

(1,2)

Document

SEE NEW DESIGN RECOMMENDATIONS

55