Datasheet DV2005S1, DV2005L1, BQ2005S, BQ2005PN, BQ2005STR Datasheet (Texas Instruments)

Features

➤

Sequential fast charge and con

ditioning of two NiCd or NiMH nickel cadmium or nickel-metal hydride battery packs

➤

Hysteretic PWM switch-mode current regulation or gated con

trol of an external regulator

➤

Easily integrated into systems or used as a stand-alone charger

➤

Pre-charge qualification of tem

perature and voltage

➤

Direct LED outputs display battery and charge status

➤ Fast-charge termination by

∆

temperature/∆ time, -∆V, maximum voltage, maximum temperature, and maximum time

➤ Optional top-off and pulse-

trickle charging

General Description

The bq2005 Fast-Charge IC provides comprehensive fast charge control functions together with high-speed switching power control circuitry on a monolithic CMOS device for sequential charge management in dual battery pack applications.

Integration of closed-loop current control circuitry allows the bq2005 to be the basis of a cost-effective so

lution for stand-alone and systemintegrated chargers for batteries of one or more cells.

Switch-activated discharge-beforecharge allows bq2005-based chargers to support battery conditioning and capacity determination.

High-efficiency power conversion is accomplished using the bq2005 as a hysteretic PWM controller for switch-mode regulation of the charging current. The bq2005 may alterna-

tively be used to gate an externally regulated charging current.

Fast charge may begin on application of the charging supply, replacement of the battery, or switch depression. For safety, fast charge is inhibited unless/until the battery tempera

-

ture and voltage are within config

-

ured limits.

Temperature, voltage, and time are monitored throughout fast charge. Fast charge is terminated by any of the following:

n

Rate of temperature rise (∆T/∆t)

n

Negative delta voltage (-∆V)

n

Maximum voltage

n

Maximum temperature

n

Maximum time

After fast charge, optional top-off and pulsed current maintenance phases are available.

1

Fast-Charge IC

for Dual-Battery Packs

bq2005

Pin Connections

Pin Names

SLUS079–JUNE 1999 F

DCMDADischarge command input,

battery A

DVEN -∆V enable

TM

1

Timer mode select 1

TM

2

Timer mode select 2

TCO Temperature cut-off

TS

A

, Temperature sense input,

TS

B

battery A/B

BAT

A

, Battery voltage input,

BAT

B

battery A/B

SNSA, Sense resistor input , SNSB battery A/B

1

PN200501.eps

20-Pin DIP or SOIC

2 3

4 5 6 7 8

20 19

18

17 16 15 14

13 9 10

12

11

DCMD

A

DVEN

TM

1

TM

2

TCO

TS

A

TS

B

BAT

A

BAT

B

SNS

A

FCC

B

CH

B

MOD

B

MOD

A

V

CC

V

SS

FCC

A

CH

A

DIS

A

SNS

B

DIS

A

Discharge control output, battery A

CH

A

, Charge status output,

CH

B

battery A/B

FCC

A

, Fast charge complete output,

FCC

B

battery A/B

V

SS

System ground

V

CC

5.0V±10% power

MOD

A

, Charge current control

MOD

B

output, battery A/B

Pin Descriptions

DCMD

A

Discharge-before-charge control input, battery A

DCMD

A

controls the discharge-before-charge function of the bq2005. A negative-going pulse on DCMD

A

initiates a discharge to EDV followed by a charge if conditions allow. By tying DCMD

A

to ground, automatic discharge-before-charge is enabled on every new charge cycle start.

DVEN

-∆V enable input

This input enales/disables -∆V charge termina

tion. If DVEN is high, the -∆V test is enabled. If DVEN is low, -∆V test is disabled. The state of DVEN may be changed at any time.

TM

1

–

TM

2

Timer mode inputs

TM

1

and TM2are three-state inputs that con

figure the fast charge safety timer, -∆V holdoff time, and that enhance/disable top-off. See Table 2.

TCO

Temperature cutoff threshold input

Input to set maximum allowable battery temperature. If the potential between TS

A

and SNSAor TSB and SNSBis less than the voltage at the TCO input, then fast charge or top-off charge is terminated for the corresponding battery pack.

TS

A

,

TS

B

Temperature sense inputs

Input, referenced to SNS

A

or SNSB,respec

tively, for an external thermistor monitoring battery temperature.

BAT

A

,

BAT

B

Voltage inputs

The battery voltage sense input, referenced to SNS

A,B

, respectively. This is created by a

high-impedance resistor divider network con

nected between the positive and the negative terminals of the battery.

SNS

A

,

SNS

B

Charging current sense inputs,

SNS

A,B

controls the switching of MOD

A,B

based on the voltage across an external sense resistor in the current path of the bat

tery. SNS is the reference potential for the TS and BAT pins. If SNS is connected to V

SS

, MOD switches high at the beginning of

charge and low at the end of charge.

DIS

A

Discharge control output

Push-pull output used to control an external transistor to discharge battery A before charging.

CH

A

,

CH

B

Charge status outputs

Push-pull outputs indicating charging status for batteries A and B, respectively. See Fig

-

ure 1 and Table 2.

FCC

A

,

FCC

B

Fast charge complete outputs

Open-drain outputs indicating fast charge complete for batteries A and B, respectively. See Figure 1 and Table 2.

MOD

A

,

MOD

B

Charge current control outputs

MOD

A,B

is a push-pull output that is used to control the charging current to the battery. MOD

A,B

switches high to enable charging current to flow and low to inhibit charging current flow to batteries A and B, respectively.

V

CC

VCCsupply input

5.0 V, ±10% power input.

Vss

Ground

2

bq2005

Functional Description

Figure 3 shows a block diagram and Figure 4 shows a state diagram of the bq2005.

Battery Voltage and Temperature Measurements

Battery voltage and temperature are monitored for maxi

-

mum allowable values. The voltage presented on the bat

-

tery sense input, BAT

A,B

, must be divided down to be

-

tween 0.95 ∗ V

CC

and 0.475 ∗ VCCfor proper operation. A

resistor-divider ratio of:

RB1 RB2N2.375

=−1

is recommended to maintain the battery voltage within the valid range, where N is the number of cells, RB1 is the resistor connected to the positive battery terminal, and RB2 is the resistor connected to the negative bat

-

tery terminal. See Figure 1.

Note: This resistor-divider network input impedance to end-to-end should be at least 200kΩ and less than 1MΩ.

A ground-referenced negative temperature coefficient thermistor placed in proximity to the battery may be used as a low-cost temperature-to-voltage transducer. The temperature sense voltage input at TS

A,B

is developed using a

resistor-thermistor network between V

CC

and VSS. See

Figure 1. Both the BAT

A,B

and TS

A,B

inputs are refer-

enced to SNS

A,B

, so the signals used inside the IC are:

V

BAT(A,B)-VSNS(A,B)=VCELL(A,B)

and

V

TS(A,B)-VSNS(A,B)=VTEMP(A,B)

Discharge-Before-Charge

The DCMDAinput is used to command dischargebefore-charge via the DIS

A

output. Once activated,

DIS

A

becomes active (high) until V

CELL

falls below V

EDV

where:

V

EDV

= 0.475 ∗ VCC± 30mV

at which time DIS

A

goes low and a new fast charge cycle

begins.

The DCMD

A

input is internally pulled up to VCC(its in

active state). Leaving the input unconnected, therefore, results in disabling discharge-before-charge. A negative going pulse on DCMD

A

initiates discharge-before-charge at any time regardless of the current state of the bq2005. If DCMD

A

is tied to VSS, discharge-beforecharge will be the first step in all newly started charge cycles.

Starting A Charge Cycle

A new charge cycle is started by (see Figure 2):

1. V

CC

rising above 4.5V

2. V

CELL

falling through the maximum cell voltage,

V

MCV

where:

V

MCV

= 0.95 ∗ VCC± 30mV

If DCMD

A

is tied low, a discharge-before-charge will be executed as the first step of the new charge cycle. Otherwise, pre-charge qualification testing will be the first step.

The battery must be within the configured temperature and voltage limits before fast charging begins.

3

bq2005

Fg2005-1.eps

N T C

bq2005

V

CC

PACK +

PACK -

TS

A,B

SNS

A,B

RT1

RT2

RB2

RB1

bq2005

Negative Temperature

Coefficient Thermister

PACK+

PACK-

BAT

A,B

SNS

A,B

Figure 1. Voltage and Temperature Monitoring

The valid battery voltage range is V

EDV<VBAT<VMCV.

The valid temperature range is V

HTF<VTEMP<VLTF

,

where:

V

LTF

= 0.4 ∗ VCC± 30mV

V

HTF

= [(1/4 ∗ V

LTF

) + (3/4 ∗ V

TCO

)] ± 30mV

V

TCO

is the voltage presented at the TCO input pin, and is

configured by the user with a resistor divider between V

CC

and ground. The allowed range is 0.2 to 0.4 ∗ VCC.

If the temperature of the battery is out of range, or the voltage is too low, the chip enters the charge pending state and waits for both conditions to fall within their al

-

lowed limits. The MOD

A,B

output is modulated to pro

vide the configured trickle charge rate in the charge pending state. There is no time limit on the charge

pending state; the charger remains in this state as long as the voltage or temperature conditons are outside of the allowed limits. If the voltage is too high, the chip goes to the battery absent state and waits until a new charge cycle is started.

Fast charge continues until termination by one or more of the five possible termination conditions:

n

Delta temperature/delta time (∆T/∆t)

n

Negative delta voltage (-∆V)

n

Maximum voltage

n

Maximum temperature

n

Maximum time

4

bq2005

Fast Charging

Top-Off

(Optional)

T200501.eps

Dis-

charge

(Optional Battery A)

Charge

Pending*

(Pulse-Trickle)

DIS

A

MOD

A,B

MOD

A,B

Discharge-Before-Charge started

or

Battery discharged to 0.475 * V

CC.

Battery outside

temperature/voltage limits.

Battery within temperature/voltage limits.

Pulse-Trickle

Switch-mode Configuration

External Regulation

CH

A,B

Status Output

FCC

A,B

Status Output

4s

34s

260 s

Note*

260 s

Note*

*See Table 3 for pulse-trickle period.

Figure 2. Charge Cycle Phases

-∆V Termination

If the DVEN input is high, the bq2005 samples the voltage at the BAT pin once every 34s. If V

CELL

is lower than any previously measured value by 12mV ±4mV, fast charge is terminated. The -∆V test is valid in the range V

MCV

- (0.2 ∗ VCC)<V

CELL<VMCV

.

Voltage Sampling

Each sample is an average of 16 voltage measurements taken 57µs apart. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%.

Voltage Termination Hold-off

A hold-off period occurs at the start of fast charging. During the hold-off period, -∆V termination is disabled. This avoids premature termination on the voltage spikes sometimes produced by older batteries when fast-charge current is first applied. ∆T/∆t, maximum voltage and maximum temperature terminations are not affected by the hold-off period.

∆T/∆t Termination

The bq2005 samples at the voltage at the TS pin every 34s, and compares it to the value measured two samples earlier. If V

TEMP

has fallen 16mV ±4mV or more, fast charge is terminated. The ∆T/∆t termination test is valid only when V

TCO<VTEMP<VLTF

.

Temperature Sampling

Each sample is an average of 16 voltage measurements taken 57µs apart. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%.

Maximum Voltage, Temperature, and Time

Anytime V

CELL

rises above V

MCV,

CHG goes high (the LED goes off) immediately. If the bq2005 is not in the voltage hold-off period, fast charging also ceases immediately. If V

CELL

then falls back below V

MCV

before t

MCV

=1s (maximum), the chip transitions to the Charge Complete state (maximum voltage termination). If V

CELL

remains

above V

MCV

at the expiration of t

MCV,

the bq2005 transi

tions to the Battery Absent state (battery removal). See Figure 4.

Maximum temperature termination occurs anytime the voltage on the TS pin falls below the temperature cut-off threshold V

TCO.

Charge will also be terminated if V

TEMP

rises above the minimum temperature fault threshold, V

LTF,

after fast charge begins.

Maximum charge time is configured using the TM pin. Time settings are available for corresponding charge rates of C/4, C/2, 1C, and 2C. Maximum time-out termi

nation is enforced on the fast-charge phase, then reset, and enforced again on the top-off phase, if selected. There is no time limit on the trickle-charge phase.

Top-off Charge

An optional top-off charge phase may be selected to follow fast charge termination for the C/2 through 4C rates. This phase may be necessary on NiMH or other

5

Corresponding

Fast-Charge Rate TM1 TM2

Typical Fast-Charge

and Top-Off

Time Limits

Typical -∆V/MCV

Hold-Off

Time (seconds)

Top-Off

Rate

C/4 Low Low 360 137 Disabled C/2 Float Low 180 820 Disabled

1C High Low 90 410 Disabled 2C Low Float 45 200 Disabled 4C Float Float 23 100 Disabled

C/2 High Float 180 820 C/16

1C Low High 90 410 C/8 2C Float High 45 200 C/4 4C High High 23 100 C/2

Note: Typical conditions = 25°C, VCC= 5.0V.

Table 1. Fast Charge Safety Time/Hold-Off/Top-Off Table

bq2005

battery chemistries that have a tendency to terminate charge prior to reaching full capacity. With top-off en

abled, charging continues at a reduced rate after fast-charge termination for a period of time selected by the TM

1

and TM2input pins. (See Table 2.) During top-off, the CC pin is modulated at a duty cycle of 4s active for every 30s inactive. This modulation results in an average rate 1/8th that of the fast charge rate. Maximum voltage, time, and temperature are the only termination methods enabled during top-off.

Pulse-Trickle Charge

Pulse-trickle charging follows the fast charge and op

tional top-off charge phases to compensate for selfdischarge of the battery while it is idle in the charger. The configured pulse-trickle rate is also applied in the charge pending state to raise the voltage of an overdischarged battery up to the minimum required before fast charge can begin.

In the pulse-trickle mode, MOD is active for 260µsofa period specified by the settings of TM1 and TM2. See Ta

ble 1. The resulting trickle-charge rate is C/64 when top-off is enabled and C/32 when top-off is disabled. Both pulse trickle and top-off may be disabled by tying TM1 and TM2 to V

SS

.

Charge Status Indication

Charge status is indicated by the CHG output. The state of the CHG output in the various charge cycle phases is shown in Figure 4 and illustrated in Figure 2.

Temperature status is indicated by the TEMP output. TEMP is in the high state whenever V

TEMP

is within the

temperature window defined by the V

LTF

and V

HTF

tem

perature limits, and is low when the battery tempera

ture is outside these limits.

In all cases, if V

CELL

exceeds the voltage at the MCV

pin, both CHG and TEMP outputs are held high regard

less of other conditions. CHG and TEMP may both be used to directly drive an LED.

Pack Sequencing

If both batteries A and B are present when a new charge cycle is started, the charge cycle starts on battery B and B remains the active channel until fast charge termina

tion. Then battery A will be fast charged, followed by a top-off phase on B (if selected), a top-off phase on A (if

selected), and then maintenance charging on both. If only battery A is present, the charge cycle begins on A and continues until fast charge termination even if a battery is inserted in channel B in the meantime. A new battery insertion in channel B while A is in the top-off phase terminates top-off on A and begins a new charge cycle on B. If A is configured for or commanded to discharge-before-charge, the discharge may take place while channel B is the active charging channel. When the discharge is complete, if B is still the active channel battery A enters the Charge Pending state until A becomes the active channel.

Charge Current Control

The bq2005 controls charge current through the MOD

A,B

out

-

put pin. The current control circuitry is designed to sup

-

port implementation of a constant-current switching regu

-

lator or to gate an externally regulated current source.

When used in switch mode configuration, the nominal regulated current is:

I

REG

= 0.225V/R

SNS

Charge current is monitored at the SNS

A,B

input by the

voltage drop across a sense resistor, R

SNS

, between the

low side of the battery pack and ground. R

SNS

is sized to

provide the desired fast charge current.

If the voltage at the SNS

A,B

pin is less than V

SNSLO

, the

MOD

A,B

output is switched high to pass charge current to

the battery.

When the SNS

A,B

voltage is greater than V

SNSHI

, the

MOD

A,B

output is switched low—shutting off charging

current to the battery.

V

SNSLO

= 0.04 ∗ VCC± 25mV

V

SNSHI

= 0.05 ∗ VCC± 25mV

When used to gate an externally regulated current source, the SNS

A,B

pin is connected to VSS, and no sense

resisitor is required.

6

bq2005

7

bq2005

OSC

TIM

ING

CO

NTROL

DISPLAY

CONTROL

LTF

CHECK

TCO

CHECK

DISCHARGE

CO

NTRO

L

M

O

D

CONTROL

EDV

CHECK

M

CV

CHECK

CHARG

E CONTROL STATE

M

ACHINE

A/D

-

DVEN

DCM

D

A

TM1

TM2

DIS

A

M

OD

A

TS

A

BAT

A

SNS

A

TCO

V

CC

V

SS

V

TS

- V SNS

V

BAT

- V SNS

MO

D

B

FCC

A

CH

A

FCC

B

CH

B

LTF

CHECK

TCO

CHECK

EDV

CHECK

M

CV

CHECK

-

TS

B

BAT

B

SNS

B

A/D

BD2005

Figure 3. Block Diagram

8

Battery

Temperature?

V

HTF

<

V

TEMP

< V

LTF

Trickle

CHG = 1/8s

flash

FCC = high

Fast

CHG = low

FCC = high

Charge Pending

Battery Voltage?

V

EDV

< V

CELL

< V

MCV

and V

HTF

< V

TEMP

< V

LTF

V

EDV

< V

CELL

< V

MCV

Top-off

CHG = high

FCC = low

V

TEMP

> V

LTF

or

V

TEMP

< V

HTF

V

TEMP

< V

TCO

or Maximum Time Out

V

CELL

> V

MCV

V

CELL

< V

ED

V

- V or T/ t or V

TEMP

< V

TCO

or

Maximum Time Out

Battery Absent

Discharge

CH

A

= 1/8s

flash

FCC

A

= high

Top-off

selected?

Yes

No

Charge Complete

Trickle

CHG = high

FCC = high

V

CELL

> V

MCV

V

CELL

<

V

MC

V

t > t

MC

V

CELL

> V

MCV

V

CELL

>

V

MCV

V

CELL

>

V

MCV

V

CELL

<

V

EDV

V

CELL

>

V

MCV

Trickle

CHG = high

FCC = low

New Charge Cycle Started by either one of:

rising to valid level

Battery replacement (V

CELL

falling through V

MCV

)

DCMDA tied to

ground?

(channel A only)

No or

Yes

Rising edge

on DCMD

A

channel B

Trickle

CHG = high

FCC = high

V

CC

SD2005

Figure 4. State Diagram

bq2005

9

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

V

CC

VCCrelative to V

SS

-0.3 +7.0 V

V

T

DC voltage applied on any pin ex

-

cluding V

CC

relative to V

SS

-0.3 +7.0 V

T

OPR

Operating ambient temperature -20 +70 °C Commercial

T

STG

Storage temperature -55 +125 °C

T

SOLDER

Soldering temperature - +260 °C 10 sec max.

T

BIAS

Temperature under bias -40 +85 °C

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera

-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo

-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Thresholds (T

A=TOPR;VCC

±

10%)

Symbol Parameter Rating Tolerance Unit Notes

V

SNSHI

High threshold at SNS

A,B

resulting in MOD

A,B

= Low

0.05*V

CC

±

0.025

V

SNSLO

Low threshold at SNS

A,B

re

-

sulting in MOD

A,B

= High

0.04*V

CC

±

0.010

V

LTF

Low-temperature fault

0.4*V

CC

±

0.030

V

TEMP

≥

V

LTF

inhibits/

terminates charge

V

HTF

High-temperature fault

(1/4*V

LTF

) + (3/4*V

TCO

)

±

0.030

V

TEMP

≤

V

HTF

inhibits

charge

V

EDV

End-of-discharge voltage

0.475*V

CC

±

0.030

V

CELL<VEDV

inhibits

fast charge

V

MCV

Maximum cell voltage

0.95*V

CC

±

0.030

V

CELL>VMCV

inhibits/

terminates charge

V

THERM

TS input change for ∆T/∆t detection

16

±4

mV

-∆V

BAT input change for -∆V detection

12

±4

mV

bq2005

10

Recommended DC Operating Conditions (T

A

= 0 to +70°C)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

Supply voltage 4.5 5.0 5.5 V

V

CELL

BAT voltage potential 0 - V

CC

VV

BAT

- V

SNS

V

BAT

Battery input 0 - V

CC

V

TEMP

TS voltage potential 0 - V

CC

VVTS- V

SNS

V

TS

Thermistor input 0 - V

CC

V

TCO

Temperature cutoff 0.2*V

CC

- 0.4*V

CC

V

IH

Logic input high 2.0 - - V DCMDA, DVEN

Logic input high V

CC

- 0.3 - - V TM1,TM

2

V

IL

Logic input low - - 0.8 V DCMDA, DVEN

Logic input low - - 0.3 V TM

1

,TM

2

V

OH

Logic output high VCC- 0.5 - - V DISA, MOD

A,B,IOH

≤

-5mA

V

OL

Logic output low - - 0.5 V

DIS

A

, FCC

A,B

,CH

A,B

, MOD

A,B

,

I

OL

≤

5mA

I

CC

Supply current - 1.0 3.0 mA Outputs unloaded

I

OH

DISA, MOD

A,B

source -5.0 - - mA @VOH= VCC- 0.5V

I

OL

DISA, FCC

A,B

, MOD

A,B

,

CH

A,B

sink

5.0 - - mA

@V

OL

= VSS+ 0.5V

I

L

Input leakage

--±1

µ

A DVEN, V = V

SS

to V

CC

- - -400

µ

A DCMDA, V = V

SS

I

IL

Logic input low source - - 70.0

µ

A

TM

1

,TM2,

V = V

SS

to VSS+ 0.3V

I

IH

Logic input high source -70.0 - -

µ

A

TM

1

,TM2,

V = V

CC

- 0.3V to V

CC

I

IZ

TM1,TM2tri-state open detection

-2.0 - 2.0

µ

A

TM

1

,TM2should be left dis

connected (floating) for Z logic input state.

I

BAT

Input current to BAT

A,B

when battery is removed

- - -20

µ

A

V

CC

= 5.0V; TA= 25°C; input

should be limited to this cur

-

rent when input exceeds V

CC

.

Note: All voltages relative to VSS, except as noted.

bq2005

11

Timing (T

A

= 0 to +70°C; V

CC

±

10%)

Symbol Parameter Minimum Typical Maximum Unit Notes

t

PW

Pulse width for DCMDA, pulse command

1- -

µ

s

Pulse start for discharge-beforecharge

d

FCV

Time base variation -16 - 16 % VCC= 4.5V to 5.5V

t

REG

MOD output regulation frequency

- - 300 kHz

t

MCV

Maximum voltage termination time limit

--1s

Time limit to distinguish battery removed from charge complete

Note: Typical is at TA= 25°C, VCC= 5.0V.

Impedance

Symbol Parameter Minimum Typical Maximum Unit

R

BATA,B

Battery A/B input impedance 50 - - M

Ω

R

TSA,B

TS

A,B

input impedance 50 - - M

Ω

R

TCO

TCO input impedance 50 - - M

Ω

R

SNSA,B

SNS

A,B

input impedance 50 - - M

Ω

bq2005

12

bq2005

PN: 20-Pin DIP

E1

E

e

L

A

A1

B1

B

GS

C

D

20-Pin PN

(DIP)

Dimension Minimum Maximum

A 0.160 0.180

A1 0.015 0.040

B 0.015 0.022

B1 0.055 0.065

C 0.008 0.013 D 1.010 1.060 E 0.300 0.325

E1 0.230 0.280

e 0.300 0.370 G 0.090 0.110 L 0.115 0.135 S 0.055 0.080

All dimensions are in inches.

13

bq2005

S: 20-Pin SOIC

e

D

B

E

H

A1

A

C

L

.004

20-Pin S(SOIC

)

Dimension Minimum Maximum

A 0.095 0.105

A1 0.004 0.012

B 0.013 0.020 C 0.008 0.013 D 0.500 0.515 E 0.290 0.305

e 0.045 0.055 H 0.395 0.415 L 0.020 0.040

All dimensions are in inches.

14

bq2005

Data Sheet Revision History

Change No. Page No. Description Nature of Change

39V

SNSLO

rating Was V

SNSHI

- (0.01 * VCC);

is 0.04 * V

CC

4 5 Corrected sample period Was: 32s;

Is: 34s

45,9

Corrected -∆V threshold

Was: 13mV Is: 12mV

4 All Revised and expanded format of this

data sheet

Clarification

59T

OPR

Deleted industrial temperature range.

Notes: Change 3 = Sept. 1996 D changes from Nov. 1993 C.

Change 4 = Nov. 1997 E changes from Sept. 1996 D. Change 5 = June 1999 F changes from Nov. 1997 E.

15

bq2005

Ordering Information

bq2005

Package Option:

PN = 20-pin narrow plastic DIP S = 20-pin SOIC

Device:

bq2005 Dual-Battery Fast-Charge IC

16

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