Datasheet dsPIC33FJ12GP201, dsPIC33FJ12GP202 Datasheet

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Page 1

dsPIC33FJ12GP201/202

Data Sheet

High-Performance, 16-bit Digital Signal Controllers

Page 2

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and t he lik e is provided only for your convenience and may be su perseded by upda t es . It is y our responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life supp ort and/or safety ap plications is entir ely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless M icrochip from any and all dama ges, claims, suits, or expenses re sulting from such use. No licens es are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PRO MA TE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programmin g , IC SP, ICEPIC, Mindi, MiW i , MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC

logo, PowerCal, PowerInfo, PowerMate, PowerT ool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

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dsPIC33FJ12GP201/202

High-Performance, 16-Bit Digital Signal Controllers

Operating Range:

• Up to 40 MIPS operation (at 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

High-Performance DSC CPU:

• Modified Harvard architecture

• C compiler optimized inst ruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M instruction words

• Linear data memory addressing up to 64 Kbytes

• 83 base instructions, mostly one word/one cycle

• Sixteen 16-bit general purpose registers

• Two 40-bit accumulators with rounding and saturation options

• Flexible and powerful addressing modes:

-Indirect

- Modulo

- Bit-Reversed

• Software stack

• 16 x 16 fractional/integer multiply operations

• 32/16 and 16/16 divide operations

• Single-cycle multiply and accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

• Up to ±16-bit shifts for up to 40-bit data

Interrupt Controller:

• 5-cycle latency

• 118 interrupt vectors

• Up to 21 available interrupt sources

• Up to three external interrupts

• Seven programmable priority levels

• Four processor exceptions

On-Chip Flash and SRAM:

• Flash program memory (12 Kbytes)

• Data SRAM (1024 bytes)

• Boot and General Security for Program Flash

Digital I/O:

• Peripheral Pin Select Functionality

• Up to 21 programmable digital I/O pi ns

• Wake-up/interrupt-on-change for up to 21 pins

• Output pins can drive from 3.0V to 3.6V

• Up to 5V output with open drain configuration

• All digital input pins are 5V tolerant

• 4 mA sink on all I/O pins

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated Phase-Locked Loop (PLL)

- Extremely low jitter P LL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monito r

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare:

• Timer/Counters, up to three 16-bit timers:

- Can pair up to make one 32-bit timer

- One timer runs as Real-Time Clock with external 32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to four channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to two channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM Mode

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dsPIC33FJ12GP201/202

Communication Modules:

• 4-wire SPI:

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

•I

C™:

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

•UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4 character TX and RX FIFO buffers

- LIN bus support

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

encoding and decoding in hardware

Analog-to-Digit al Converters (ADCs):

• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:

- Two and four simultaneous samples (10-bit ADC)

- Up to 10 input channels with auto-scanning

- Conversion start can be manual or synchronized with one of four trigger sources

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

CMOS Flash T echnology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial and extended temperature

• Low power consumption

Packaging:

• 18-pin SDIP/SOIC

• 28-pin SDIP/SOIC/SSOP/QFN Note: See Table 1 for the exact peripheral

features per device.

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dsPIC33FJ12GP201/202

dsPIC33FJ12GP201/202 Product Families

The device names, pin counts, memory sizes, and peripheral availability of each family are listed below, followed by their pinout diagrams.

TABLE 1: dsPIC33FJ12GP201/202 CONTROLLER FAMILIES

Remappable Peripherals

(2)

Device

dsPIC33FJ12GP201 18 12 1 8 3

dsPIC33FJ12GP202 28 12 1

Note 1: Only two out of three timers are remappable.

2: Only two out of three interrupts are remappable.

Pins

Program Flash Memory

(Kbyte)

RAM

(Kbyte)

Remappable

Pins

(1)

UART

16-bit Timer

Input Capture

421311 ADC,

Std. PWM

Output Compare

External Interrupts

SPI

6 ch

10 ch

C™

10-Bit/12-Bit ADC

113SDIP

121SDIP

Packages

I/O Pins (Max)

SOIC

SSOP

QFN

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dsPIC33FJ12GP201/202

18-PIN SDIP, SOIC

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/V

REF-/CN3/RA1

INT0/RP7

(1)

/CN23/RB7

PGD3/EMUD3/SOSCI/RP4

(1)

/CN1/RB4

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2

PGC1/EMUC1/AN3/RP1

(1)

/CN5/RB1

PGD1/EMUD1/AN2/RP0

(1)

/CN4/RB0

AN6/RP15

(1)

/CN11/RB15

AN7/RP14

(1)

/CN12/RB14

SDA1/RP9

(1)

/CN21/RB9

SCL1/RP8

(1)

/CN22/RB8

1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11 10

VSS

VDD

VDDCORE

MCLR

dsPIC33FJ12GP201

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

28-PIN SDIP, SOIC, SSOP

INT0/RP7

(1)

/CN23/RB7

MCLR

AV ss

AN7/RP14

(1)

/CN12/RB14

DDCORE

ASCL1/RP6

(1)

/CN24/RB6

TDO/SDA1/RP9

(1)

/CN21/RB9

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AN4/RP2

(1)

/CN6/RB2

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

OSCO/CLKO/CN29/RA3

AN5/RP3

(1)

/CN7/RB3

PGD3/EMUD3/SOSC/RP4

(1)

/CN1/RB4

AN8/RP13

(1)

/CN13/RB13

AN6/RP15

(1)

/CN11/RB15

AN9/RP12

(1)

/CN14/RB12

ASDA1/RP5

(1)

/CN27/RB5

Vss

OSCI/CLKI/CN30/RA2

TMS/RP11

(1)

/CN15/RB11

TDI/RP10

(1)

/CN16/RB10

Vss

TCK/SCL1/RP8

(1)

/CN22/RB8

PGD2/EMUD2/AN0/V

REF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

PGC1/EMUC1/AN3/RP1

(1)

/CN5/RB1

PGD1/EMUD1/AN2/RP0

(1)

/CN4/RB0

dsPIC33FJ12GP202

Pin Diagrams

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28-Pin QFN

1 2 3 4 5 6 7

21 20 19 18 17 16 15

28 27 26 25 24 23 22

8 9 10 11 12 13 14

PGD1/EMUD1/AN2/RP0

(1)

/CN4/RB0

PGC1/EMUC1/AN3/RP1

(1)

/CN5/RB1

AN4/RP2

(1)

/CN6/RB2

AN5/RP3

(1)

/CN7/RB3

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/RA3

DDCORE

TDI/RP10

(1)

/CN16/RB10

TMS/RP11

(1)

/CN15/RB11

AN9/RP12

(1)

/CN14/RB12

TDO/SDA1/RP9

(1)

/CN21/RB9

AN8/RP13

(1)

/CN13/RB13

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

PGD3/EMUD3/SOSCI/RP4/CN1/RB4

ASDA1/RP5

(1)

/CN27/RB5

ASCL1/RP6

(1)

/CN24/RB6

INT0/RP7

(1)

/CN23/RB7

TCK/SCL1/RP8

(1)

/CN22/RB8

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

MCLR

AN6/RP15

(1)

/CN11/RB15

AN7/RP14

(1)

/CN12/RB14

dsPIC33FJ12GP202

AVSS

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

dsPIC33FJ12GP201/202

Pin Diagrams (Continued)

Page 8

dsPIC33FJ12GP201/202

Table of Contents

1.0 Device Overview ..........................................................................................................................................................................7

2.0 CPU............................................................................................................................................................................................ 11

3.0 Memory Organization. ................................................................................................................................................................ 23

4.0 Flash Program Memory...................................... ........................................................................................................................ 47

5.0 Resets ....................................................................................................................................................................................... 53

6.0 Interrupt Controller ......................................... ............................................................................................................................ 61

7.0 Oscillator Configuration..............................................................................................................................................................89

8.0 Power-Saving Features...................... ........................................................................................................................................ 97

9.0 I/O Ports ................................................................................................................................................................................... 101

10.0 Timer1......................................................................................................................................................................................121

11.0 Timer2/3 Feature................. .............................................................................. .......................................................................123

12.0 Input Capture.............................................................................................................. ..............................................................129

13.0 Output Compare...................................................................... .................................................................................................131

14.0 Serial Peripheral Interface (SPI)...............................................................................................................................................135

15.0 Inter-Integrated Circuit™ (I

16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 147

17.0 10-bit/12-bit Analog-to-Digital Converter (ADC)............................................................ ...........................................................153

18.0 Special Features......................................................................................................................................................................167

19.0 Instruction Set Summary..........................................................................................................................................................173

20.0 Development Support. .............................................................................................................................................................. 181

21.0 Electrical Characteristics.......................................................................................................................................................... 185

22.0 Packaging Information..... .................................................... .....................................................................................................219

Appendix A: Revision History............................................................................................................................................................. 227

Index ...................................................................................................................................................................................... ........... 233

The Microchip Web Site.................. ................................................................................................................................................... 237

Customer Change Notification Service .............................................................................................................................................. 237

Customer Support..............................................................................................................................................................................237

Reader Response..............................................................................................................................................................................238

Product Identification System............................................................................................................................................................. 239

C™).............................................................................................................................................. 139

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or c omm ents r egarding t his publication, p lease c ontact the M arket ing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Page 9

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP20 1/202 devices . It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F Family Reference Manual sections.

This document co nta i ns dev ic e spec if i c in for m at ion fo r the dsPIC33FJ12GP201/202 Digital Signal Controller (DSC) devices. The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture.

Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

dsPIC33FJ12GP201/202

Page 10

OSC1/CLKI

OSC2/CLKO

DD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VDDCORE/VCAP

IC1,2,7,8

I2C1

PORTA

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV & Table Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Address Latch

Program Memory

Data Latch

Address Bus

Literal Data

Data Latch

Address

Latch

X RAM

Y RAM

Y Data Bus

X Data Bus

DSP Engine

Divide Support

Control Signals to Various Blocks

ADC1

Timers

PORTB

Address Generator Units

1-3

CNx

UART1

OC/

PWM1-2

Remappable

Pins

Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features

on each device.

dsPIC33FJ12GP201/202

FIGURE 1-1: dsPIC33FJ12GP201/202 BLOCK DIAGRAM

Page 11

dsPIC33FJ12GP201/202

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin Type

AN0-AN9 I Analog Analog input channels. CLKI

CLKO

OSC1 OSC2

SOSCI SOSCO

CN0-CN7 CN11-CN15 CN21-CN24 CN27 CN29-CN30

IC1-IC2 IC7-IC8

OCFA OC1-OC2

INT0 INT1 INT2

RA0-RA4 I/O ST PORTA is a bidirectional I/O port. RB0-RB15 I/O ST PORTB is a bidirectional I/O port. T1CK

T2CK T3CK

U1CTS U1RTS

U1RX U1TX

SCK1 SDI1 SDO1

SS1 SCL1

SDA1 ASCL1 ASDA1

TMS TCK TDI TDO

PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

I/O

I ST Change notification inputs.

I ST Capture inputs 1/2

I I I

I/O

I/O I/O

I/O I/O I/O

I I I

I/O

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS

ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.

ST—Compare Fault A input (for Compare Channels 1 and 2).

ST ST ST

ST ST

ST ST ST

ST ST ST ST ST ST

Oscillator cryst al outp ut. Conne cts to crys tal or reso nator in Cryst al Oscil lator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin func tion .

otherwise. Oscillator cryst al outp ut. Conne cts to crys tal or reso nator in Cryst al Oscil lator mode. Optionally functions as CLKO in RC and EC modes.

32.768 kHz low-power oscillator crystal output.

Can be software programmed for internal weak pull-ups on all inputs.

Capture inputs 7/8

Compare outputs 1 through 2. External interrupt 0.

External interrupt 1. External interrupt 2.

Timer1 external cl ock input. Timer2 external cl ock input. Timer3 external cl ock input.

UART1 clear to send.

—

UART1 ready to send. UART1 receive.

—

UART1 transmit. Synchronous serial clock input/output for SPI1.

SPI1 data in.

—

SPI1 data out. SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1.

JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin.

—

JTAG test data output pin. Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3.

Description

Page 12

dsPIC33FJ12GP201/202

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Type

VDDCORE P — CPU lo gic filter capacitor connection. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog voltage reference (high) input.

REF- I Analog Analog voltage reference (low) input.

V AVDD P P Positive supply for analog modules. This pin must be connected at all times. MCLR AVSS P P Ground reference for analog modules.

DD P — Positive supply for peripheral logic and I/O pins.

V Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

Buffer

Type

Description

Page 13

dsPIC33FJ12GP201/202

2.0 CPU

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family Reference Manual, “Section 2. CPU” (DS70204), which is available from the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M by 24 bits of user program memory space. The actual amount of program memory implemen ted vari es by devic e. A single-cycle instruction prefetch mechanism is used to help maintain throu ghput and provides predic table execution. All inst ructions execute in a sin gle cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The dsPIC33FJ12GP201/202 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or ad dress offset register. The 16th wo rking register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

The dsPIC33FJ12GP201/202 instruction set has two classes of instructions: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, dsPIC33FJ12GP201/202 devices are capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CP U is shown in Figu re 2-1. The programmer’s model for the dsPIC33FJ12GP201/202 is shown in Figure2-2.

2.1 Data Addressing Overview

The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions

operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific.

Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also support s Bit-Rev ers ed Add r essin g to greatly simplify input or output data reordering for radix-2 FFT algorithms.

The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space.

2.2 DSP Engine Overview

The DSP engine features a high-spee d 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is c apable of shif ting a 40-bit value up to 16 bits right or left, in a single cycle. The DSP instructions operate seamles sly with all other in st ruction s and have been desi gned for o ptimal re al-time p erformanc e. The MAC instruction and other associated instructions can concurrently fetch two dat a operands from mem ory while multiplyin g two W registe rs and accumu lating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.

2.3 Special MCU Features

The dsPIC33FJ12GP201/202 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. T he mul tiplie r can pe rform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17 -bi t mult ip lier for 16-bi t by 16- bit mu lti pli cation not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0).

The dsPIC33FJ12GP201/202 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions.

Page 14

Instruction

Decode &

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Control Signals

to Various Blocks

Address Bus

Literal Data

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Y RAM

Address Generator Units

Y Data Bus

X Data Bus

DSP Engine

Divide Support

PSV & Table Data Access

Control Block

Program Memory

Data Latch

Address Latch

dsPIC33FJ12GP201/202

FIGURE 2-1: dsPIC33FJ12GP201/202 CPU CORE BLOCK DIAGRAM

Page 15

dsPIC33FJ12GP201/202

PC22

PC0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand Registers

W1 W2 W3 W4 W5

W6 W7

W8 W9 W10 W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address Registers

AD39 AD0AD31

DSP Accumulators

ACCA ACCB

Program Space Visibility Page Address

OA OB SA SB

RCOUNT

REPEAT Loop Counter

DCOUNT

DO Loop Counter

DOSTART

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Point er Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

Core Configuration Register

Legend

CORCON

DA DC

RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

FIGURE 2-2: dsPIC33FJ12GP201/202 PROGRAMMER’S MODEL

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dsPIC33FJ12GP201/202

2.4 CPU Control Registers

CPU control registers include:

• SR: CPU Status Register

• CORCON: CORE Control Register

REGISTER 2-1: SR: CPU STATUS REGISTER

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA

(1)

bit 15 bit 8

(1)

OAB SAB DA DC

R/W-0

(2)

IPL<2:0>

R/W-0

(3)

(2)

R/W-0

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit

1 = Accumul ator A overflowed 0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit

1 = Accumul ator B overflowed 0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not satura ted

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not satura ted

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated

This bit can be read or cleared (not set). Clearing this bit will clear SA and SB.

bit 9 DA: DO Loop Active bit

1 = DO loop in progress 0 = DO loop not in progress

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are con caten ated with the IPL<3 > bi t (CO RCON<3>) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

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dsPIC33FJ12GP201/202

bit 8 DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte -sized data) o r 8th low-order bit (for w ord-sized data )

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

bit

(2)

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are con caten ated with the IPL<3 > bi t (CO RCON<3>) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

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dsPIC33FJ12GP201/202

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — —USEDT

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

bit 7 bit 0

Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit

1 = Terminate executing DO loop at end of current loop iteration 0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits

111 = 7 DO loops active

•

001 = 1 DO loop active 000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit

1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit

1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit

1 = Data space write saturation enabled 0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit

1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space 0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit

1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit

1 = Integer mode enabled f or DSP multiply operations 0 = Fractio nal mode enab led for DSP multiply opera tions

(1)

(2)

(1)

(2)

DL<2:0>

PSV RND IF

Note 1: This bit will always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

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dsPIC33FJ12GP201/202

2.5 Arithmetic Logic Unit (ALU)

The dsPIC33FJ12GP201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC S tatus bits op erate as Borrow bits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU ca n be written to the W re gister array or a data memory location.

The dsPIC3 3FJ 12GP2 01/ 202 CPU inco rp orat es h ardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division.

Refer to the dsPIC30F/33F Programmer’s Reference Manual (DS70157) for information on the SR bits affected by each instruction.

2.5.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

2.5.2 DIVIDER

The divide block support s 32-bit/16-bit and 16-b it/16-bit signed and unsigned integer divide op erat ion s w i th th e following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

and Digit Borrow

2.6 DSP Engine

The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic).

The dsPIC33FJ12GP201/202 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by th e sa m e instruction (e.g., ED, EDAC).

The DSP engine can also perform accumulator-to-accumulator operatio ns that require no add itional data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below:

• Fractional or integer DSP multiply (IF)

• Signed or unsigned DSP multiply (US)

• Conventional or convergent rounding (RND)

• Automatic saturation on/off for ACCA (SATA), ACCB (SATB) and writes to data memory (SATDW)

• Accumulator Saturation mode selection (ACCSAT)

A block diagram of the DSP engine is shown in Figure 2-3.

TABLE 2-1: DSP INSTRUCTIONS

SUMMARY

Instruction

CLR ED A = (x – y) EDAC A = A + (x – y) MAC A = A + (x * y) Yes MAC A = A + x MOVSAC No change in A Yes MPY A = x * y No MPY A = x MPY.N A = – x * y No MSC A = A – x * y Yes

Algebraic

Operation

A = 0

ACC Write

Back

Yes

No No

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dsPIC33FJ12GP201/202

Zero Backfill

Sign-Extend

Barrel Shifter

40-bit Accumulator A 40-bit Accumulator B

Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM

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dsPIC33FJ12GP201/202

2.6.1 MULTIPLIER

The 17-bit x 17-bit multiplier is capable of signed or unsigned operati on and can mul tiplex i ts ou tput u sing a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/ scale r is a 33-bit valu e that i s sign -ext ended to 40 bits. Integer data is inherently represented as a signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit.

• The range of an N-bit 2’s complement integer is

N-1

to 2

-2

• For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’.

• For a 32-bit integer, the data range is

-2,147,483,648 (0x80000000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the radix po int is impli ed to lie just af ter the sign bit (QX format). The range of an N-bit 2’s complement fract ion with this im plie d radix point i s -1.0 to (1 – 2 is -1.0 (0x8000) to 0. 999 969 482 (0x 7FF F) including ‘0’ and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte or word-sized operands. Byt e operan ds will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

– 1.

1-N

). For a 16-bit fraction, the Q15 data range

-10

2.6.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/subtracter wi th au tom ati c si gn ex ten si on lo gic . It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For t he ADD and LAC instructions, the da t a to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation.

2.6.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one si de, and either true or comp leme nt data into the other input.

• In the case of addition, the Carry/Borrow

active-high and the other input is true data (not complemented).

• In the case of subtraction, the Carry/Borrow

is active-low and the ot her inpu t is comple mente d.

The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously, and the SAT<A:B> (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when, and to what value to saturate.

Six STATUS register bits have been provided to support saturation and overflow:

• OA: ACCA overflowed into guard bits

• OB: ACCB overflowed into guard bits

• SA: ACCA saturated (bit 31 overflow and

saturation)

ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and

saturation)

ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB

• SAB: Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overfl ow Tra p Flag Enable bit s (OV A TE, OVBTE) in the INTCON1 register are set (refer to Section 6.0 “Interrupt Controller”). This allows the user application to t ake imme diate ac tion, for ex ampl e, to correct system gain.

input is

input

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dsPIC33FJ12GP201/202

The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the u ser applic ation. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow, and therefore, in dic ate that a catastrophic overflow has occurred. If the COVTE bit i n the INTCON1 register is set, the SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The Overfl ow and Saturation Status bits c an optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programs can che ck one bi t in the ST A TUS register to determine if eith er accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which ty pically uses both accum ulators.

The device supports three Saturation and Overflow modes:

• Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations).

• Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect , the guard bit s are not used, so the OA, OB or OAB bits are never set.

• Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user applic ation. No sa turation operation is performed and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic ov erfl ow ca n i nitiate a trap excep tio n.

2.6.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded ver sion of the hi gh word (bits 31 t hroug h 16) of the accumulator tha t is not targeted by the instructio n

into data spac e memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

• W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a

1.15 fraction.

• [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.6.2.3 Round Logic

The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function durin g an ac cumulat or write (store). Th e Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 dat a val ue is store d and the least significant word (lsw) is simply discarded.

Conventional rounding will zero-extend bit 15 of the accumulator and will add it to the ACCxH word (bits 16 through 31 of the accumulator).

• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x 8000 included), ACCxH is incremented.

• If ACCxL is between 0x0 000 and 0x 7FFF, ACCxH is left unchanged.

A consequence of this algorithm is that over a succession of random rou nding operations, th e value tends to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined.

• If it is ‘1’, ACCxH is incremented.

• If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 2.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instruc tions, the data is always subject to rounding.

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dsPIC33FJ12GP201/202

2.6.2.4 Data Sp ace Write Saturation

In addition to adder/subtrac ter saturation, writes to dat a space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 1 6-bit round adde r . These in puts are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncat ion ) is tested for overflow and adjusted accordingly:

• For input data greater than 0x007FFF, data written to memory is forced to the maximum positive

1.15 value, 0x7FFF.

• For input dat a les s tha n 0x FF8000, dat a w ritten to memory is forced to the maximum negative 1.15 value, 0x8000.

The Most Significant bit of the sourc e (bit 39) is used to determine the sign of the operand being tested.

If the SA TDW bi t in the CORCON regis ter is not set , the input data is always passed through unmodified under all conditions.

2.6.3 BARREL SHIFTER

The barrel shifter ca n perform up to 1 6-bit arithme tic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to su pport multi-bit shif t s of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (num ber of bits) and direction of the shift operation. A positive value shif ts the operand right. A negative v alue shi fts the opera nd left. A va lue of ‘ 0’ does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result fo r DSP shif t o peratio ns a nd a 16-bit re sult for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts.

Page 24

dsPIC33FJ12GP201/202

NOTES:

Page 25

dsPIC33FJ12GP201/202

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program Flash Memory

0x002000

0x001FFE

(4K instructions)

0x800000

0xF80000

Registers

0xF80017 0xF80018

DEVID (2)

0xFEFFFE 0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO

Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC33FJ12GP201/202

Configuration Memory Space

User Memory Space

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family

Reference Manual, “Section 4. Program Memory” (DS70202), which is available

from the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 architecture features separate program and data memory spaces and buses. This ar chitecture also allows th e direct ac cess of program memory from the data space during code execution.

3.1 Program Address Space

The program address memory space of the dsPIC33FJ12GP201/202 devices is 4M instructions. The space is addressable by a 24-bit value derived either fro m the 23- bit P C during program execution, or from table operation or data space remapping as described in Section 3.6 “Interfacing Program and Data Memory Spaces”.

User application acces s to the progr am mem ory sp ace is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space.

The memory map for the dsPIC33FJ12GP201/202 family of devices is shown in Figure3-1.

FIGURE 3-1: PROGRAM MEMORY FOR dsPIC33FJ1 2GP2 01/202 DEVICES

Page 26

dsPIC33FJ12GP201/202

0816

PC Address

0x000000 0x000002 0x000004 0x000006

00000000 00000000

00000000

Program Memor y

‘Phantom’ Byte

(read as ‘0’)

least significant word (lsw)

most significant word (msw)

Instruction Width

0x000001 0x000003 0x000005 0x000007

msw

Address (lsw Address)

3.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2).

Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible.

3.1.2 INTERRUPT AND TRAP VECTORS

All dsPIC33FJ12GP201/202 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on de vice Re set to th e actual start of code . A GOTO in st ruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.

dsPIC33FJ12GP201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the ma ny dev ic e interrupt sources to be handle d by separate In terrupt Serv ice Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt

Vector Table”.

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

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dsPIC33FJ12GP201/202

3.2 Data Address S pace

The dsPIC33FJ12GP201/202 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory map is shown in Figure 3-3.

All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data mem ory space (that is, when EA<15> =

0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section3.6.3 “Read-

ing Data From Program Memory Using Program Space Visibility”).

dsPIC33FJ12GP201/202 devices implement up to 30 Kbytes o f data memory. Should an EA poi nt to a location outside of this area, an all-zero word or byte will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte addressable, 16-bit-wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even ad dresses, whil e the Most Significant Bytes (MSBs) have odd addresses.

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC devices and improve data space memory usage efficiency, the dsPIC33FJ12GP201/202 instruction set supports both word and byte operations. As a consequence of byte a ccessibility, all effective address ca lculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. D at a by te writ es only wri te to t he co rresponding side of the array or register that matches the byte address.

MCU

All word accesses m ust be al igned to an even a ddress. Misaligned word data fetches are not supported, so care must be ta ken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the instruction occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the Least Significan t B yte . T he Most Significant By te is n ot modified.

A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

3.2.3 SFR SPACE

The first 2 Kbytes of the near data space, from 0x000 0 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ12GP201/202 c ore and p erip he ral m odu le s for controlling the operation of the device.

SFRs are distributed among the modules that they control, and are generall y grouped together by mod ule. Much of the SFR space contains unused addresses; these are read as ‘0’. A co mplete listing o f implemented SFRs, including their addresses, is shown in Table 3-1 through Table 3-21.

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.

3.2.4 NEAR DATA SPACE

The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the who le data s pace is ad dressable us ing MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer.

Page 28

dsPIC33FJ12GP201/202

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally Mapped into Program Memory

0x0801

0x0800

0x0C00

2 Kbyte SFR Space

1 Kbyte SRAM Space

0x8001

0x8000

SFR Space

X Data RAM (X)

X Data

Unimplemented (X)

Y Data RAM (Y)

0x09FE 0x0A00

0x09FF 0x0A01

0x0BFF 0x0C01

0x1FFF

0x1FFFF

0x2001

0x2000

8 Kbyte Near Data Space

FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ12GP201/202 DEVICES WITH 1 KB RAM

Page 29

dsPIC33FJ12GP201/202

3.2.5 X AND Y DATA SPACES

The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concu rrently fe tch two w ords from RAM , thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT).

The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X dat a prefe tch p ath for the dual operand DSP instructions (MAC class).

The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide two concurrent data read paths.

Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space.

All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable.

All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device.

Page 30

TABLE 3-1: CPU CORE REGISTERS MAP

SFR Name

WREG0 0000 Working Re gister 0 WREG1 0002 Working Re gister 1 WREG2 0004 Working Re gister 2 WREG3 0006 Working Re gister 3 WREG4 0008 Working Re gister 4 WREG5 000A Working Re gis ter 5 WREG6 000C Wo rk ing R egi ster 6 WREG7 000E Working Re gis ter 7 WREG8 0010 Working Re gister 8 WREG9 0012 Working Re gister 9 WREG10 0014 Working Register 10 WREG11 0016 Working Register 11 WREG12 0018 Working Register 12 WREG13 001A Working Register 13 WREG14 001C Working Register 14 WREG15 001E Working Register 15 SPLIM 0020 Stack Pointer Limit Register ACCAL 0022 Accumulator A Low Word Register ACCAH 0024 Accumulator A Hi gh Word Re gister ACCAU 0026 Accumulato r A Upp er W ord Re giste r ACCBL 0028 Accumulator B Low Word Register ACCBH 002A Accumul ator B Hi gh Word Regi ster ACCBU 002C Accu mula tor B U pper W o rd Reg ister PCL 002E Program Counter Low Word Register PCH 0030 — — — — — — — — Program Co unte r Hi gh B yte Re gist er TBLP A G 0032 — — — — — — — — T able Page Address Pointer Register PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register RCOUNT 0036 Repeat Loop Counter Register DCOUNT 0038 DCOUNT<15:0> xxxx DOSTARTL 003A DOSTARTL<15:1> 0xxxx DOSTARTH 003C DOENDL 003E DOENDL<15:1> 0xxxx DOENDH 0040 SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C CORCON 0044 — — — US EDT DL<2:0> MODCON 0046 XMODEN YMODEN

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — — — — — — — —

— —

All

Resets

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx

DOSTARTH<5:0> 00xx

DOENDH 00xx

0000

SATA SATB SATDW ACCSA T IPL3 PSV RND IF

BWM<3:0> YWM<3:0> XWM<3:0> 0000

0020

dsPIC33FJ12GP201/202

Page 31

TABLE 3-1: CPU CORE REGISTERS MAP (CONTINUED)

SFR Name

XMODSRT 0048 XS<15:1> 0xxxx XMODEND 004A XE<15:1> 1xxxx YMODSRT 004C YS<15:1> 0xxxx YMODEND 004E YE<15:1> 1xxxx XBREV 0050 BREN XB<14:0> xxxx DISICNT 0052 —

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— Disable Interrupts Counter

All

Resets

xxxx

TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP202

SFR

Name

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CNEN2 0062 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12P UE CN1 1PUE CNPU2 006A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

CN30IE CN29IE

—

CN30PUE CN29PUE

—

—- — —

CN27IE

—

CN27PUE

—

— — — — — — —

CN24IE CN23IE CN22IE CN21IE

CN24PUE CN23PUE CN22PUE CN21PUE

— — — —

CN16IE

CN16PUE

All

Resets

0000 0000 0000 0000

TABLE 3-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP201

SFR

Name

CNEN1 0060 CNEN2 0062 — CNPU1 0068 CNPU2 006A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

— — —

CN30IE CN29IE — — — —

CN30PUE CN29PUE

CN12IE CN11IE

— — — — —

CN12PUE CN11PUE

— — — — —

CN23IE CN22IE CN21IE

— — — — —

CN23PUE CN22PUE CN21PUE

CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

— — — — —

CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

— — — — —

All

Resets

0000

dsPIC33FJ12GP201/202

Page 32

dsPIC33FJ12GP201/202

TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OV ATE OVBTE COVTE SFTACERR DIV0ERR INTCON2 0082 ALTIVT DISI IFS0 0084 IFS1 0086 IFS4 008C IEC0 0094 IEC1 0096 IEC4 009C IPC0 00A4 IPC1 00A6 IPC2 00A8 IPC3 00AA IPC4 00AC IPC5 00AE IPC7 00B2 IPC16 00C4 INTTREG 00E0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

— MAT HERR ADDRERR STKERR OSCFAIL — 0000

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 — —INT2IF — — — — — IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF 0000 — — — — — — — — — — — — — —U1EIF— 0000 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 — —INT2IE— — — — — IC8IE IC7IE — INT1IE CNIE — MI2C1IE SI2C1IE 0000 — — — — — — — — — — — — — —U1EIE— 0000 — T1IP<2:0> —OC1IP<2:0>—IC1IP<2:0>— INT0IP<2:0> 4444 — T2IP<2:0> —OC2IP<2:0>—IC2IP<2:0>— — — — 4440 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 — — — — — — — — — AD1IP<2:0> — U1TXIP<2:0> 0044 — CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044 — IC8IP<2:0> —IC7IP<2:0>— — — — — INT1IP<2:0> 4404 — — — — — — — — — INT2IP<2:0> — — — — 0040 — — — — — — — — — U1EIP<2:0> — — — — 0040 — — — — ILR<3:0>> — VECNUM<6:0> 0000

All

Resets

Page 33

TABLE 3-5: TIMER REGISTER MAP

SFR Name

TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TON TMR2 0106 Timer2 Register TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) TMR3 010A Timer3 Register PR2 010C Period Register 2 PR3 010E Period Register 3 T2CON 0110 TON T3CON 0112 TON

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

—

TSIDL

—

TSIDL

—

TSIDL

— — — — — —

— — — — — — — — — — — —

TGATE TCKPS<1:0>

TGATE TCKPS<1:0> T32 TGATE TCKPS<1:0>

TABLE 3-6: INPUT CAPTURE REGISTER MAP

SFR Name

IC1BUF 0140 Input 1 Capture Re gister IC1CON 0142 IC2BUF 0144 Input 2 Capture Re gister IC2CON 0146 IC7BUF 0158 Input 7 Capture Re gister IC7CON 015A IC8BUF 015C Input 8Ca p tu re R e g iste r IC8CON 015E

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

ICSIDL

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

—

TSYNC TCS

— —

All

Resets

xxxx FFFF

—

0000 xxxx xxxx xxxx FFFF FFFF

—

TCS TCS

—

0000

—

0000

All

Resets

xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000

dsPIC33FJ12GP201/202

TABLE 3-7: OUTPUT COMPARE REGISTER MAP

SFR Name

OC1RS 0180 Output Comp ar e 1 S ec ond ary Reg ister OC1R 0182 Output Compare 1 Register OC1CON 0184 OC2RS 0186 Output Comp ar e 2 S ec ond ary Reg ister OC2R 0188 Output Compare 2 Register OC2CON 018A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

OCSIDL

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

All

Resets

xxxx xxxx 0000 xxxx xxxx 0000

Page 34

dsPIC33FJ12GP201/202

TABLE 3-8: I2C1 REGISTER MAP

SFR Name

I2C1RCV 0200 — — — — — — — — Receive Register I2C1TRN 0202 — — — — — — — —Transmit Register I2C1BRG 0204 — — — — — — — Baud Rate Generat or Registe r I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF I2C1ADD 020A — — — — — — Address Register I2C1MSK 020C — — — — — — Address M as k Re gi ste r

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

0000 00FF 0000 1000 0000 0000 0000

TABLE 3-9: UART1 REGISTER MAP

SFR Name

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA U1TXREG 0224 — — — — — — — UART T r an sm it Re g ist er U1RXREG 0226 — — — — — — — UART Receive Register U1BRG 0228 Baud R a te G en era to r P r es ca le r

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

0000 0110 xxxx 0000 0000

TABLE 3-10: SPI1 REGISTER MAP

SFR

Name

SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

All

Resets

0000 0000 0000 0000

Page 35

TABLE 3-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP

File

Name

RPINR0 0680 RPINR1 0682 RPINR3 0686 RPINR7 068E RPINR10 0694 RPINR11 0696 RPINR18 06A4 RPINR20 06A8 RPINR21 06AA

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — INT1R<4:0> — — — — — — — — — — — — — — — — — — —INT2R<4:0> — — —T3CKR<4:0>— — —T2CKR<4:0> — — — IC2R<4:0> — — — IC1R<4:0> — — — IC8R<4:0> — — — IC7R<4:0> — — — — — — — — — — —OCFAR<4:0> — — — U1CTSR<4:0> — — —U1RXR<4:0> — — —SCK1R<4:0>— — —SDI1R<4:0> — — — — — — — — — — —SS1R<4:0>

TABLE 3-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12GP202

File

Name

RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> RPOR1 0 6C2 RPOR2 0 6C4 RPOR3 0 6C6 RPOR4 0 6C8 RPOR5 06CA RPOR6 06CC RPOR7 06CE

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — —RP3R<4:0>— — — RP2R<4:0> — — —RP5R<4:0>— — — RP4R<4:0> — — —RP7R<4:0>— — — RP6R<4:0> — — —RP9R<4:0>— — — RP8R<4:0> — — —RP11R<4:0>— — —RP10R<4:0> — — —RP13R<4:0>— — —RP12R<4:0> — — —RP15R<4:0>— — —RP14R<4:0>

All

Resets

1F00 001F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 001F

All

Resets

0000 0000 0000 0000 0000 0000 0000 0000

dsPIC33FJ12GP201/202

TABLE 3-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12GP201

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0> RPOR2 06C4 RPOR3 06C6 RPOR4 06C8 RPOR7 06CE

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — — — — — — — RP4R<4:0> — — —RP7R<4:0>— — — — — — — — — — —RP9R<4:0>— — — RP8R<4:0> — — —RP15R<4:0>— — —RP14R<4:0>

All

Resets

0000 0000 0000 0000 0000

Page 36

TABLE 3-14: ADC1 REGISTER MAP FOR dsPIC33FJ12GP201

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306

ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD 031A ADC1BUFE 031C ADC1BUFE 031E AD1CON1 0320 ADON AD1CON2 0322 VCFG<2:0> AD1CON3 0324 ADRC AD1CHS123 0326 AD1CHS0 0328 CH0NB AD1PCFGL 032C AD1CSSL 0330 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

— — — — — — — —PCFG7PCFG6— — PCFG3 PCFG2 PCFG1 PCFG0 0000 — — — — — — — — CSS7 CSS6 — — CSS3 CSS2 CSS1 CSS0 0000

—ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— — SAMC<4:0> ADCS<7:0> 0000

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

ADC Data Buffer 1 xxxx ADC Data Buffer 2 xxxx ADC Data Buffer 3 xxxx ADC Data Buffer 4 xxxx ADC Data Buffer 5 xxxx ADC Data Buffer 6 xxxx ADC Data Buffer 7 xxxx ADC Data Buffer 8 xxxx

ADC Data Buffer 9 xxxx ADC Data Buffer 10 xxxx ADC Data Buffer 11 xxxx ADC Data Buffer 12 xxxx ADC Data Buffer 13 xxxx ADC Data Buffer 14 xxxx ADC Data Buffer 15 xxxx

Resets

All

dsPIC33FJ12GP201/202

Page 37

TABLE 3-15: ADC1 REGISTER MAP FOR dsPIC33FJ12GP202

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC1BUF2 0304

ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD 031A ADC1BUFE 031C ADC1BUFF 031E AD1CON1 0320 ADON AD1CON2 0322 VCFG<2:0> AD1CON3 0324 ADRC AD1CHS123 0326 AD1CHS0 0328 CH0NB AD1PCFGL 032C AD1CSSL 0330 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

— — — — — — PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 — — — — — — CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

—ADSIDL— — AD12B FO RM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— — SAMC<4:0> ADCS<7:0> 0000

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

ADC Data Buffer 1 xxxx ADC Data Buffer 2 xxxx ADC Data Buffer 3 xxxx ADC Data Buffer 4 xxxx ADC Data Buffer 5 xxxx ADC Data Buffer 6 xxxx ADC Data Buffer 7 xxxx ADC Data Buffer 8 xxxx

ADC Data Buffer 9 xxxx ADC Data Buffer 10 xxxx ADC Data Buffer 11 xxxx ADC Data Buffer 12 xxxx ADC Data Buffer 13 xxxx ADC Data Buffer 14 xxxx ADC Data Buffer 15 xxxx

Resets

All

dsPIC33FJ12GP201/202

Page 38

dsPIC33FJ12GP201/202

TABLE 3-16: PORTA REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISA 02C0 PORTA 02C2 LATA 02C4 ODCA 02C6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — — — — — — — — — — — — — — — — — — RA4 RA3 R A2 RA1 RA0 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 — — — — — — — — — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

All

Resets

001F xxxx xxxx xxxx

TABLE 3-17: PORTB REGISTER MAP FOR dsPIC33FJ12GP202

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 ODCB 02CE Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

ODCB15 ODCB14 ODCB13 ODCB12 ODCB1 1 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0

All

Resets

FFFF xxxx xxxx xxxx

TABLE 3-18: PORTB REGISTER MAP FOR dsPIC33FJ12GP201

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TRISB PORTB LATB ODCB Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

02C8 TRISB15 TRISB14 02CA RB15 RB14 02CC LATB15 LATB14 02CE ODCB15 ODCB14

— — — — TRISB9 TRISB8 TRISB7 — — TRISB4 — — TRISB1 T RISB0 — — — —RB9RB8RB7— —RB4— —RB1RB0 — — — — LATB9 LATB8 LATB7 — —LATB4— —LATB1LATB0 — — — — ODCB9 ODCB8 ODCB7 — — ODCB4 — — ODCB1 ODCB0

All

Resets

C393 xxxx xxxx xxxx

TABLE 3-19: SY STEM CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK IOLOCK LOCK —CF— LPOSCEN OSWEN 0300 CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040 PLLFBD 0746 OSCTUN 0748

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: RCON register Reset values dependent on the type of Reset.

2: OSCCON register Reset values dependent on the FOSC Configuration bits and by the type of Reset.

— — — — — — — PLLDIV<8:0> 0030 — — — — — — — — — — TUN<5:0> 0000

All

Resets

xxxx

(1)

(2)

Page 39

TABLE 3-20: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NVMCON 0760 WR WREN WRERR — — — — — — ERASE — —NVMOP<3:0> NVMKEY 0766

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

— — — — — — — — NVMKEY<7:0>

TABLE 3-21: PMD REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PMD1 0770 PMD2 0772 IC8MD IC7MD Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— —

T3MD T2MD T1MD

— — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000

— — —

I2C1MD

—

U1MD

—

SPI1MD

— —

AD1MD 0000

All

Resets

0000 0000

All

Resets

(1)

dsPIC33FJ12GP201/202

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dsPIC33FJ12GP201/202

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward

Higher Address

0x0000

PC<22:16>

POP : [--W15] PUSH : [W15++]

3.2.6 SOFTWARE STACK

In addition to its use as a working register, the W15 register in the dsPIC33FJ 12GP201/2 02 device s is also used as a software Stack Pointer. The Stack Pointer always points to the firs t avai lable fre e word and gro ws from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. For a PC push during any CALL instruction, the M SB o f t he PC i s zero-extended before the push, ensuring that the MSB is always clear.

Note: A PC push during exception processing

concatenates the SRL regis ter to th e MSB of the PC prior to the push.

The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer set s an upper ad dress bounda ry for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word-aligned.

When an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error tra p will occ ur on a subs equen t push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE.

Similarly, a St ac k Point er underflow (sta ck error) tra p is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space.

A write to the SPLIM regis ter should not be immediately followed by an indirect read operation using W15.

FIGURE 3-4: CALL STACK FRAME

3.2.7 DATA RAM PROTECTION FEATURE

The dsPIC33F product family supports Data RAM protection features that enable segme nt s of RAM to be protected when used in conjunction with Boot and Secure Code Segm ent Secu rity. BS RAM (Secure RAM segment for BS) is accessible only from the Boot Segment Fl ash code when en abled. SSR AM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 3-1 for an overview of the BSRAM and SSRAM SFRs.

3.3 Instruction Addressing Modes

The addressing modes shown in Table 3-22 form the basis of the addressi ng modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types.

3.3.1 FILE REGISTER INSTRUCTIONS

Most file register ins truc tio ns us e a 1 3-bi t ad dres s field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is de noted as WREG i n these instr uctions . The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the re sult t o a re gister or regi ster p air. The MOV instruction allows additional flexibility and can access the entire data space.

3.3.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (that is,

the addressing mode can only be register direct ), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal Note: Not all instructions support all the

addressing modes given above. Individual instructions can support different subsets of these addressing modes.

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dsPIC33FJ12GP201/202

TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA.) Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

to form the EA.

The sum of Wn and Wb forms the EA.

3.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS

Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one).

In summary, the following addressing modes are supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modifi ed

• Register Indirect Pre-modif ied

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note: Not all instructions suppo rt all the add ress-

ing modes given abo ve. In divid ual ins tructions may support different subsets of these addressing modes.

The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W 9 are always direc ted to the X RAG U, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, ther efore, be valid address es within X data spa ce for W 8 and W9 and Y d ata sp ace for W10 and W11.

Note: Register Indirect with Register Offset

Addressing mode is available only for W9 (in X space) and W11 (in Y space).

In summary, the following addressing modes are supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

3.3.5 OTHER INSTRUCTIONS

Besides the addressing modes outlined previously, some instructio ns use li teral con stant s of va rious siz es. For example, BRA (branch) instructions use 16-bit signed literals to spe cify the branc h destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is im plied by the opcod e itself. Cert ain opera tions, su ch as NOP, do not have any operands.

3.3.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC, and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tabl es .

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dsPIC33FJ12GP201/202

0x1100

0x1163

Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words

Byte

Address

MOV #0x1100, W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo

MOV #0x0000, W0 ;W0 holds buffer fill value

MOV #0x1110, W1 ;point W1 to buffer

DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value

3.4 Modulo Addressing

Modulo Addressing mode is a method of providing an automated means to support ci rcular dat a buf fers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms.

Modulo Addressi ng can operate in eith er data or program space (since the data pointer mechanism is essentially the same for both). On e circ ular bu ff er can be suppo rted in each of the X (whi ch also provides the po inters into program space) and Y da ta space s. Modu lo Addr e ssi ng can operate on an y W reg is te r po in te r. Howev er, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively.

In general, any particular circular buffer can be configured to operate in only one direction, as there are certain restrictio ns on the buff er start addres s (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer.

The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries).

3.4.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 3-1).

Note: Y space Modulo Addressing EA calcula-

tions assume word-sized data (LSB of every EA is always clear).

The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes).

3.4.2 W ADDRESS REGISTER SELECTION

The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register f ield t o s pe cify th e W Ad dr es s re gi st ers. The XWM and YWM fields select the registers that will operate with Modulo Addressing:

• If XWM = 15, X RAGU and X WAGU Modulo

Addressing is disabled.

• If YWM = 15, Y AGU Modulo Addressing is

disabled.

The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 3-1). Modulo Addre ssing i s enabled for X dat a space when XWM is set to any v alue other than ‘15’ and the XMODEN bit is set at MODCON<15>.

The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 3-5: MODULO ADDRESSING OPERATION EXAMPLE

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dsPIC33FJ12GP201/202

3.4.3 MODULO ADDRESSING APPLICABILITY

Modulo Addressing can be applied to the EA calculation associated with any W register.

Address boundaries check for addresses equal to:

• The upper boundary addresses for incrementing

buffers

• The lower boundary addresses for decrementing

buffers

It is important to realize that the address boundaries also check for addresses less than or greater than these addresses. Address changes can, therefore, jump beyond bo undaries and stil l be a djusted c orrectly.

Note: The modulo corrected effecti ve add res s i s

written back to the register only when Pre-Modify or Post-Modify Addressing mode is used to compute the effective address. When an addres s offs et (such a s [W7+W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged.

3.5 Bit-Reversed Addressing

Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.

The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier.

3.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-Reversed Addressing mode is enabled in any of these situations:

• BWM bits (W register selection) in the MODCON

• The BREN bit is set in the XBREV register

• The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment

If the length of a bi t-reversed buffer is M = 2 the last ‘N’ bits of the da ta buffer start address must be zeros.

XB<14:0> is the Bit-Reversed Address modifier, or ‘pivot point,’ which is typically a const ant. In th e case of an FFT computa tion, its v alue is equal to half of the FFT data buffer size.

Note: All bit-reversed EA calculations assume

word-sized data (LSB of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses.

When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or Post-Increment Addressing and word-sized data writes. It will not function for any other addressing mode or for byte-sized d ata, and norma l addresses a re generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear).

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU.

If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be im mediate ly follo wed b y an indirect read operation using the W reg ister that ha s been designated as the bit-rev ersed poi nter.

bytes,

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dsPIC33FJ12GP201/202

b3 b2 b1 0

b2 b3 b4

Bit Locations Swapped Left-to-Right Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-Word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4b11 b10 b9 b8

b11 b10 b9 b8

b15 b14 b13 b12

Sequenti al Address

Pivot Point

FIGU R E 3-6 : BIT-REVERSED ADDRESS EXAMPLE

TABLE 3-23: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15

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dsPIC33FJ12GP201/202

3.6 Interfacing Program and Data Memory Spaces

The dsPIC33FJ12GP201/202 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, mean ing t hat data ca n als o be prese nt in t he program space. To use this data successfully, it must be accessed in a way that preserve s the alig nment of information in both spaces.

Aside from normal execution, the dsPIC33FJ12GP201/202 architecture provides two methods by which program space can be accessed during operation:

• Using table in stru ctions to ac cess indiv idual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be upd ated perio dically. It also all ows access to all bytes of the program word. The remapping method allows an applicat ion to ac cess a l arge bloc k of data on a read-only basis, which is ideal for lookups from a large table of static data. The application can only access the least significant word of the program word.

3.6.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data regist ers. The solution de pends on the interface method to be used.

For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of th e EA is ‘1’, PSVPAG is concaten ated with the lower 15 b its of t he EA to form a 23-bit program space address. Unlike table operations, this limits remapping operati ons stric tly to the u ser m emory area.

T abl e 3-24 and Figure 3-7 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word.

TABLE 3-24: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access (Code Execution)

TBLRD/TBLWT

(Byte/Word Read/Write)

Program Space Visibility (Block Remap/Read)

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calc ulati ng the pro gram s pac e addre ss. Bit 15 of

the address is PSVPAG<0>.

Access

Space

User 0 PC<22:1> 0

User TBLPAG<7:0> Data EA<15:0>

Configuration TBLPAG<7:0> Data EA<15:0>

User 0 PSVPAG<7:0> Data EA<14:0>

<23> <22:16> <15> <14:1> <0>

0xx xxxx xxxx xxxx xxxx xxx0

0xxx xxxx xxxx xxxx xxxx xxxx

1xxx xxxx xxxx xxxx xxxx xxxx

0 xxxx xxxx xxx xxxx xxxx xxxx

Program Spa ce Addr ess

(1)

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dsPIC33FJ12GP201/202

0Program Counter

23 bits

PSVPAG

8 bits

15 bits

Program Counter

(1)

Select

TBLPAG 8 bits

16 bits

Byte Select

1/0

User/Configuration

Table Operations

(2)

Program Space Visibility

(1)

Space Select

24 bits

23 bits

(Remapping)

1/0

Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to

maintain word alignment of data in the program and data spaces.

2: Table op erat ion s are not required to be word-align ed . Table read operations ar e p erm itt ed

in the configuration memory space.

FIGURE 3-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

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dsPIC33FJ12GP201/202

081623

00000000 00000000

00000000

‘Phantom’ By te

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0)

23 15 0

TBLPAG

0x000000

0x800000

0x020000 0x030000

Program Space

The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.

3.6.2 DATA ACCESS FROM PROGRAM

MEMORY USING TABLE INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit-wide word ad dress space s, residing side b y side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte.

Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations.

• TBLRDL (Table Read Low): In Word mode, this

instruction maps the lower word of the program space location (P<15:0> ) to a data addre ss (D<15:0>).

In Byte mode, either the upper or lo wer byte of th e lower program word is mapped to th e lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’.

• TBLRDH (Table Read High): In W o r d m od e , th i s instruction maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’.

In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, as in the TBLRDL instruction. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1).

In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operati on are explained in Section 4.0 “Flash Program Memory”.

For all table operations, the area of program memory space to be access ed is de termine d by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of t he device, in cluding use r and confi guration spaces. W hen TBL PAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.

FIGURE 3-8: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

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dsPIC33FJ12GP201/202

23 15 0

PSVPAG

Data Space

Program Space

0x0000

0x8000

0xFFFF

0x000000

0x800000

0x010000 0x018000

When CORCON<2> = 1 and EA<15> = 1:

The data in the page designated by PSVPAG is mapped into the upper half of the data memory space...

Data EA<14:0>

...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.

PSV Area

3.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 1 6K word page of the progra m sp ace. This option provides tran sparent access to stored constant data from the data space without the need to us e special instructions (such as TBLRDL or TBLRDH).

Program space access through the data space occurs if the Most Significan t bit of the dat a space EA i s ‘1’ and program spac e visibil ity is enabl ed by se tting t he PSV bit in the Core Control register (CORCON<2>). The location of th e program memory spac e to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the low e r 15 bits of data sp ac e addresses directly map to the lower 15 bits in the corresponding program space addresses.

Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required.

Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 3-9), only the lower 16 bits of the

24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed.

Note: PSV access is temporarily disabled durin g

table reads/writes.

For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instructio n cycle in additi on to the sp ecified execution time. All other instructions require two instruction cycles in addition to the specified execution time.

For operations that use PSV, and are executed inside a REPEAT loop, the se in stances require t wo i ns truc tion cycles in addition to the spe ci fie d ex ec uti on time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an interrupt

• Execution upon re-entering the loop after an interrupt is serviced

Any other iteration of the REPEAT loop will allow the instruction using PSV to access data to execute in a single cycle.

FIGURE 3-9: PROGRAM SPACE VISIBILITY OPERATION

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dsPIC33FJ12GP201/202

Program Counter

24 bits

Program Counter

TBLPAG Reg

8 bits

Working Reg E A

16 bits

Byte

24-bit EA

1/0

Select

Using Table Instruction

Using

User/Configuration Space Select

4.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family

Reference Manual, “Section 5. Flash Programming” (DS70191), which is

available from the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 devices contain internal Flash program memory for storing an d executi ng application code. The memory is readable, writable, and erasable during normal operation over the entire V range.

Flash memory can be programmed in two ways:

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Run-Time Self-Programming (RTSP)

ICSP allows a dsPIC33FJ12GP201/202 device to be serially programme d while in the en d application circuit. This is done with two lines for programming clock and programming data (one of the alt ernate pro gramming pin pairs: PGC1/PGD1, PGC2/ PGD2 or PGC3/PGD3), and three other lines fo r power (V Master Clear (MCLR

). This allows customers to

DD), ground (VSS) and

manufacture boards with unprogrammed devices and

then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time.

4.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of Flash mem ory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bit s <7:0> of the TBLP AG re gister and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1.

The TBLRDL and the TBLWTL instructions are used to read or write to bits <15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes.

The TBLRDH and TBLWTH i nstructio ns are used to rea d or write to bits <23:16> of program memory. TBLRDH and TBLWTH can also access prog ram memory in W ord or Byte mode.

FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS

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dsPIC33FJ12GP201/202

7.37 MHz FRC Accuracy()% FRC Tuning()%××

--------------------------------------------------------------------------------------------------------------------------

11064 Cycles

7.37 MHz 10.05+()1 0.00375–()××

---------------------------------------------------------------------------------------------- 1. 4 3 5 ms==

11064 Cycles

7.37 MHz 10.05–()1 0.00375–()××

----------------------------------------------------------------------------------------------1.586ms==

4.2 RTSP Operation

The dsPIC33FJ12GP201/202 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.

The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary.

The basic sequence f or RTSP program ming is to set up a Table Pointer, and then perform a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions.

All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row.

4.3 Programming Operations

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished.

The programming time depends on the FRC accuracy (see Table 21-18) and the value of the FRC Oscillator Tuning register (see Register 7-4). Use the following formula to calcul ate the minim um and maxim um values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 21-12).

EQUATION 4-1: PROGRAMMING TIME

For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 7-4) are set to ‘b111111, the Minimum Row Write Time is:

and, the Maximum Row Write Time is:

Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

4.4 Control Registers

Two SFRs are used to read and write the program Flash memory:

• NVMCON: Flash Memory Control Register

• NVMKEY: NonVolatile Memory Key Register

The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed, and the start of the programming cycle.

NVMKEY (Register 4-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 4.3 “Programming Operations” for further details.

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dsPIC33FJ12GP201/202

REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER

(1)

R/SO-0

WR WREN WRERR — — — — —

bit 15 bit 8

R/W-0

(1)

R/W-0

(1)

U-0 U-0 U-0 U-0 U-0

U-0 R/W-0

(1)

U-0 U-0 R/W-0

— ERASE — —NVMOP<3:0>

(1)

R/W-0

(1)

R/W-0

(2)

(1)

R/W-0

(1)

bit 7 bit 0

Legend: SO = Satiable-only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command

0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’

(2)

bit 3-0 NVMOP<3:0>: NVM Operation Select bits

If ERASE =

1: 1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte

If ERASE =

0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte

Note 1: These bits can only be Reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

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dsPIC33FJ12GP201/202

REGISTER 4-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

bit 7 bit 0

Legend: SO = Satiable-only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits

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dsPIC33FJ12GP201/202

; Set up NVMCON for block erase operation

MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase th e block (see Example 4-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits.

b) Write the starti ng add res s o f th e page to be

erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU s t al l s fo r t he d u r a-

tion of the erase cycle. When the erase is

done, the WR bit is clear ed automatically.

4. Write the first 64 instruction s from dat a RAM in to the program memory b uffers (see Example 4-2).

5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle

begins and th e CPU stalls for the duration of

the write cycl e. When the wr ite to Flash mem -

ory is done, the WR bit is cleared

automatically.

6. Repeat steps 4 and 5, using the next available 64 instructi ons from the block in data R AM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.

For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.

EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE

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dsPIC33FJ12GP201/202

; Set up NVMCON for row programming operations

MOV #0x4001, W0 ;

MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled

MOV #0x0000, W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word

MOV #LOW_WORD_0, W2 ;

MOV #HIGH_BYTE_0, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word

MOV #LOW_WORD_1, W2 ;

MOV #HIGH_BYTE_1, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word

MOV #LOW_WORD_2, W2 ;

MOV #HIGH_BYTE_2, W3 ;

TBLWTL W2,

[W0] ; Write PM low word into program latch

TBLWTH W3,

[W0++] ; Write PM high byte into program latch

•

; 63rd_program_word

MOV #LOW_WORD_31, W2 ;

MOV #HIGH_BYTE_31, W3 ;

TBLWTL W2,

[W0] ; Write PM low word into program latch

TBLWTH W3,

[W0++] ; Write PM high byte into program latch

DISI #5 ; Block all interrupts with priority <7

EXAMPLE 4-2: LOADING THE WRITE BUFFERS

EXAMPLE 4-3: INITIATIN G A PROGRAMMING SE QUENCE

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dsPIC33FJ12GP201/202

MCLR

VDD

Internal

Regulator

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illega l Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect

POR

Configuration Mismatch

5.0 RESETS

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family Reference Manual, “Section 8. Reset” (DS70192), which is available from the Microchip website (www.microchip.com).

The Reset module combines all reset sources and controls the device Master Reset Signa l, SYSRST. The following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR

•SWR: RESET Instruction

• WDTO: Watchdog Timer Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

: Master Clear Pin Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

A simplified block diagram of the Reset module is shown in Figure 5-1.

Any active source of reset will make the SYSRST signal active. On system Rese t, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected.

Note: Refer to the specific peripheral section or

Section 2.0 “CPU” of this manual for

All types of devi ce Res et set a corres pondi ng st atus bit in the RCON register to indicate the typ e o f Res et (se e Register 5-1).

All bits that are set, with the exception of the POR bit (RCON<0>), are clear ed during a POR event. The us er application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur.

The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bit s is discusse d in other section s of this data sheet.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset is meaningful.

FIGURE 5-1: RESET SYSTEM BLOCK DIAGRAM

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dsPIC33FJ12GP201/202

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

TRAPR IOPUWR

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

EXTR SWR SWDTEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit

1 = A configuration mismatch Reset has occurred.

0 = A configuration mismatch Reset has NOT occurred.

bit 8 VREGS: Voltage Regulator Standby During Sleep bit

1 = Voltage regulator is active during Sleep

0 = Voltage regulator goes into Standby mode during Sleep

bit 7 EXTR: External Reset (MCLR

1 = A Master Clear (pin) Reset has occurred

0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset (Instruction) Flag bit

1 = A RESET instruction has been executed

0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit

1 = WDT is enabled

0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred

0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode

0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit

1 = Device was in Idle mode

0 = Device was not in Idle mode

— — — —CMVREGS

(2)

WDTO SLEEP IDLE BOR POR

) Pin bit

(1)

(2)

Note 1: All of the Reset st atus bit s can be set o r cleare d in so ftw are. Set tin g one of t hese b its in sof tw are does no t

cause a device Reset.

2: If the FWDTE N Configura tion bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

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dsPIC33FJ12GP201/202

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred

Note 1: All of the Reset st atus bit s can be set o r cleare d in so ftw are. Set tin g one of t hese b its in sof tw are does no t

cause a device Reset.

2: If the FWDTE N Configura tion bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

(1)

(CONTINUED)

Page 58

dsPIC33FJ12GP201/202

5.1 System Reset

The dsPIC33FJ12GP201/202 family of devices have two types of Reset:

•Cold Reset

•Warm Reset A cold Reset is the result of a Power-on Reset (POR)

or a Brown-out Reset (BOR). On a cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source.

A warm Reset is the result of all other reset sources, including th e RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the C urre nt Osc ill ato r Select io n (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register.

The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is detailed below and is shown in Figure 5-2.

1. POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active un til V threshold and the delay TPOR has elapsed.

DD crosses the VPOR

2. BOR Re set: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay T

BOR has elapsed. The delay TBOR

ensures that the voltage regulator output becomes stable.

3. PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (T BOR. The delay T

PWRT ensures that the system

PWRT) after a

power supplies have stabilized at the appropriate level for full-spe ed ope ration . Afte r the de lay

PWRT has elapsed, the SYSRST becomes

T inactive, which in turn enables the selected oscillator to start generating clock cycles.

4. Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in Table5-1. Refer to Section 7.0 “Oscillator Configuration” for more information.

5. When the oscillator clock is ready, the pro cessor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine.

6. The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T

FSCM

elapsed.

TABLE 5-1: OSCILLATOR DELAY

Oscillator Mode

FRC, FRCDIV16,

Oscillator

Startup Delay

OSCD ——TOSCD

FRCDIVN FRCPLL TOSCD —TLOCK TOSCD + TLOCK XT TOSCD TOST —TOSCD + T OST HS TOSCD TOST —TOSCD + TOST EC ———— XTPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK HSPLL TOSCD TOST TLOCK TOSCD + TOST + TLOCK ECPLL — — TLOCK TLOCK SOSC TOSCD TOST —TOSCD + TOST LPRC TOSCD ——TOSCD Note 1: TOSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up

times vary with crystal char acteristics, load capacitance, etc.

OST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a

2: T

10 MHz crystal and T

3: T

LOCK = PLL lock time (1.5ms nominal), if PLL is enabled.

OST = 32 ms for a 32 kHz crystal.

Oscillator Startup

Timer

PLL Lock Time Total Delay

Page 59

FIGURE 5-2: SYSTEM RESET TIMING

Reset

Run

Device Status

VPOR

Vbor

VBOR

POR Reset

BOR Reset

SYSRST

TPWRT

TPOR

TBOR

Oscillator Clock

OSCD TOST

TLOCK

Time

FSCM

1. POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V

DD crosses

the V

POR threshold and the delay TPOR has elapsed.

2. BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V

DD crosses the VBOR threshold

and the delay T

BOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable.

3. PWRT Timer: The programmable power-up time r continues t o hold th e processor in Reset for a sp ecific perio d of time (T

PWRT)

after a BOR. The delay T

PWRT ensures that the system p ower supplies have stabilized at the appropriate leve l for full-speed

operation. After the delay T

PWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start

generating clock cycles.

4. Oscillator Delay: The total dela y for the clock to be ready for various clock source selections a re given in Table 5-1. Refer to Section 7.0 “Oscillator Configuration” for more information.

5. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine.

6. The Fail-safe clock monitor (FSCM), if enabled, be gins to monito r the system clock when the system clock is rea dy and the de l ay T

FSCM elapsed.

dsPIC33FJ12GP201/202

TABLE 5-2: OSCILLATOR DELAY

Symbol Parameter Value

POR POR threshold 1.8V nominal

POR POR extension

time

BOR BOR threshold 2.5V nominal

BOR BOR extension

time

PWRT Programmable

power-up time

TFSCM Fail-safe Clock

delay

Monitor Delay

30 μs maximum

100 μs maximum

0-128 ms nominal

900 μs maximum

Note: When the device exits the Re set condi-

tion (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST becomes i nactive, is long enough to get all operating parameters within specification.

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dsPIC33FJ12GP201/202

VDD

SYSRST

VBOR

SYSRST

VBOR

SYSRST

VBOR

BOR + TPWRT

VDD dips before PWRT expires

BOR + TPWRT

TBOR + TPWRT

5.2 Power-on Reset (POR)

A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until

DD crosses the VPOR threshold and the delay TPOR

V has elapsed. The delay TPOR ensures the internal device bias circuits become stable.

The device supp ly voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 21.0 “Electrical Characteristics” for details.

The POR status (POR) bit in the Reset Control (RCON<0>) register is set to indicate the Power-on Reset.

5.3 Brown-out Reset (BOR) and Power-up timer (PWRT)

The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the V

DD < VBOR) for proper devi ce operation. Th e BOR cir-

(V cuit keeps the device in Reset until V

FIGURE 5-3: BROWN-OUT SITUATIONS

DD is too low

DD crosses VBOR

threshold and the delay TBOR has elapsed. The delay

BOR ensures the voltage regulator output becomes

T stable.

The BOR status (BOR) bit in the Reset Control (RCON<1>) register is set to indicate the Brown-out Reset.

The device will not run at full speed af ter a BOR a s th e

DD should rise to acceptable levels for full-speed

V operation. The PWRT provides power-up time delay

PWRT) to ensure that the syst em power supplies have

(T stabilized at the appropriate levels for full-speed operation before the SYSRST is released.

The power-up timer delay (T

PWRT) is programmed by

the Power-on Reset Timer Value Select (FPWRT<2:0>) bits in the POR Configuration (FPOR<2:0>) register, which provides eight settings (from 0 ms to 128 ms). Refer to Section 18.0 “Special Features” for further details.

Figure 5-3 shows the typical brown-out scenarios. The reset delay (T

BOR + TPWRT) is initiat ed eac h time VDD

rises above the VBOR trip point

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dsPIC33FJ12GP201/202

5.4 External Reset (EXTR)

The external Reset is generated by driving the MCLR pin low . Th e MCLR pin is a Schm itt trigge r input wit h an additional glit ch fi lter. Rese t puls es t hat ar e lon ger than the minimum pulse width will generate a Reset. Refer to Section 21.0 “Electrical Characteristics” for minimum pulse width specifications. The External Reset (MCLR (RCON) register is set to indicate the MCLR

5.4.0.1 EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits that generate reset signals to Reset multiple devices in the system. This external Res et signa l can be dire ctly co nnected to the MCLR rest of system is Reset.

5.4.0.2 INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to Reset the device, t he externa l reset pin (MCLR be tied dire ctly or resisti vely to V

pin will not be used to generate a Reset. The

MCLR external re set pin (MCLR pull-up and must not be left unconnected.

) Pin (EXTR) bit in the Reset Control

Reset.

pin to Reset the device when the

) should

DD. In this case, the

) does not ha ve an internal

level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category.

The Trap Reset Flag (TRAPR) bit in the Reset Control (RCON<15>) register is set to indicate the T rap Conf lict Reset. Refer to Section 6.0 “Interrupt Controller” for more information on trap conflict Resets.

5.8 Configuration Mismatch Reset

To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset occurs.

The Configuration Mismatch Flag (CM) bit in the Reset Control (RCON<9>) register is set to indicate the configuration mismatch Reset. Refer to Section 9.0 “I/O Ports” for more information on the configuration mism atc h Re set .

Note: The configuration mismatch feature and

associated reset flag is not availa ble on all devices.

5.5 Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the device will assert SYSRST special Reset state. This Reset state will not reinitialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST the next instruction cycle, and the reset v ector fetch will commence.

The Software Reset (Instruction) Flag (SWR) bit in the Reset Control (RCON<6>) register is set to indicate the software Reset.

, placing the device in a

is releas ed at

5.6 Watchdog T ime-out Reset (WDTO)

Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST remain unchanged. A WDT time-out during Sleep or Idle mode will w a ke- up the processor, but will not res et the processor.

The Watchdog Timer Time-out Fla g (WDTO) bit in t he Reset Control (RCON<4>) register is set to indicate the Watchdog Reset. Refer to Section 1 8.4 “Watchdog Timer (WDT)” for more information on Watchdog Reset.

. The clock sourc e will

5.7 Trap Conflict Reset

If a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority

5.9 Illegal Condition Device Reset

An illegal condition device Reset occurs due to the following sources:

• Illegal Opcode Re se t

• Uninitialized W Register Reset

• Security Reset The Illegal Opcode or Uninitialized W Access Reset

Flag (IOPUWR) bit in the Reset Control (RCON<14>) register is set to indicate the illegal condition device Reset.

5.9.0.1 ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory.

The illegal opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the illegal opcode Reset, use only the lower 16 bits of each program memory s ection to sto re the dat a values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value.

5.9.0.2 UNINITIALIZED W REGISTER RESET

Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register array (with the exception of W15) is cleared during all resets and is considered uninitialized until written to.

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5.9.0.3 SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected se gment (Boot and Secure Se gment), that operation will cause a security Reset.

The PFC occurs when the Program Counter is reloaded as a result of a Call, Jump, Computed Jump, Return, Return from Subroutine, or other form of branch instruction.

The VFC occurs when the Program Counter is reloaded with an Interrupt or Trap vector.

Refer to Section 18.8 “Code Protection and CodeGuard™ Security” for more information on Security Reset.

5.10 Using the RCON Status Bits

The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the reset.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.

Table 5-3 provides a summary of the reset flag bit operation.

TABLE 5-3: RES E T FLAG BIT OPERATION

Flag Bit Set by: Cleared by:

TRAPR (RCON<15>) Trap conflict event POR, BOR IOPWR (RCON<14>) Illegal opcode or uninitialized

W register access or Security Reset

CM (RCON<9>) EXTR (RCON<7>) MCLR

SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction,

SLEEP (RCON<3>) PWRSAV #SLEEP instruction P OR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) POR, BOR POR (RCON<0>) POR

Note: All Reset flag bits can be set or cleared by user sof tw are .

Configuration Mismatch POR, BOR

Reset POR

POR, BOR

CLRWDT instruction, POR, BOR

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6.0 INTERRUPT CONTROLLER

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family

Reference Manual, “Section 29. Interrupts (Part II)” (DS70189), which is

available on the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33FJ12GP201/202 CPU. It has the following features:

• Up to eight processor exceptions and software traps

• Seven user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug support

• Fixed interrupt entry and return latencies

6.1 Interrupt Vector Table

The Interrupt Vector Table is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of eight nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector . Each interrupt ve ctor cont ains a 24 -bit wide address. The value programmed into each interrupt vector location is th e starti ng address of th e assoc iated Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural priority; this priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address.

dsPIC33FJ12GP201/202 devices implement up to 21 unique interrupts and four nonmaskable traps. These are summarized in Table 6-1 and Table 6-2.

6.1.1 ALTERNATE INTERRUPT VECTOR TABLE

The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the defa ult vecto rs. The altern ate vector s are organized in the same manner as the default vectors.

The AIVT support s deb ugg ing by providing a m ean s to switch between an application and a support environmen t without requ iring the int errupt vectors t o be reprogrammed. This featu re als o ena bl es s w itching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.

6.2 Reset Sequence

A device Reset is not a true exception because the interrupt controller is not inv olved in the Reset pr ocess. The dsPIC33FJ12GP201/202 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. The user application can use a GOTO instruction at the Reset address which redirects program execution to the appropriate start-up routine.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.

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Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002

Reserved 0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved

Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1

~ ~

~ Interrupt Vector 52 0x00007C Interrupt Vector 53 0x00007E Interrupt Vector 54 0x000080

Interrupt Vector 1 16 0x0000FC Interrupt Vector 1 17 0x0000FE

Reserved

0x000100 Reserved 0x000102 Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved Reserved

Interrupt Vector 0 0x000114 Interrupt Vector 1

~ ~

~ Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180

Interrupt Vector 116 Interrupt Vector 1 17 0x0001FE

Start of Code 0x000200

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)

(1)

Alternate Interrupt Vector Table (AIVT)

(1)

Note 1: See Table6-1 for the list of implemented interrupt vectors.

FIGURE 6-1: dsPIC33FJ12GP201/202 INTERRUPT VECTOR TABLE

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TABLE 6-1: INTERRUPT VECTORS

Vector

Number

8 0 0x000014 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Compare 1

10 2 0x000018 0x000118 OC1 – Output Compare 1

11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C Reserved 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 – ADC1 22 14 0x000030 0x000130 Reserved 23 15 0x000032 0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 18 0x000038 0x000138 Reserved 27 19 0x00003A 0x00013A Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29 21 0x00003E 0x00013E Reserved 30 22 0x000040 0x000140 IC7 – Input Capture 7 31 23 0x000042 0x000142 IC8 – Input Capture 8 32 24 0x000044 0x000144 Reserved 33 25 0x000046 0x000146 Reserved 34 26 0x000048 0x000148 Reserved 35 27 0x00004A 0x00014A Reserved 36 28 0x00004C 0x00014C Reserved 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38 30 0x000050 0x000150 Reserved 39 31 0x000052 0x000152 Reserved 40 32 0x000054 0x000154 Reserved 41 33 0x000056 0x000156 Reserved 42 34 0x000058 0x000158 Reserved 43 35 0x00005A 0x00015A Reserved 44 36 0x00005C 0x00015C Reserved 45 37 0x00005E 0x00015E Reserved 46 38 0x000060 0x000160 Reserved 47 39 0x000062 0x000162 Reserved 48 40 0x000064 0x000164 Reserved 49 41 0x000066 0x000166 Reserved 50 42 0x000068 0x000168 Reserved 51 43 0x00006A 0x00016A Reserved 52 44 0x00006C 0x00016C Reserved 53 45 0x00006E 0x00016E Reserved

Interrupt

Request (IRQ)

Number

IVT Address AIVT Address Interrupt Source

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TABLE 6-1: INTERRUPT VECTORS (CONTINUED)

Vector

Number

54 46 0x000070 0x000170 Reserved 55 47 0x000072 0x000172 Reserved 56 48 0x000074 0x000174 Reserved 57 49 0x000076 0x000176 Reserved 58 50 0x000078 0x000178 Reserved 59 51 0x00007A 0x00017A Reserved 60 52 0x00007C 0x00017C Reserved 61 53 0x00007E 0x00017E Reserved 62 54 0x000080 0x000180 Reserved 63 55 0x000082 0x000182 Reserved 64 56 0x000084 0x000184 Reserved 65 57 0x000086 0x000186 Reserved 66 58 0x000088 0x000188 Reserved 67 59 0x00008A 0x00018A Reserved 68 60 0x00008C 0x00018C Reserved 69 61 0x00008E 0x00018E Reserved 70 62 0x000090 0x000190 Reserved 71 63 0x000092 0x000192 Reserved 72 64 0x000094 0x000194 Reserved 73 65 0x000096 0x000196 U1E – UART1 Error 74 66 0x000098 0x000198 Reserved 75 67 0x00009A 0x00019A Reserved 76 68 0x00009C 0x00019C Reserved 77 69 0x00009E 0x00019E Reserved 78 70 0x0000A0 0x0001A0 Reserved 79 71 0x0000A2 0x0001A2 Reserved

80-125 72-117 0x0000A4-

Interrupt

Request (IRQ)

Number

IVT Address AIVT Address Interrupt Source

0x0000FE

0x0001A4-

0x0001FE

Reserved

TABLE 6-2: TRAP VECTORS

Vector Number IVT Address AIVT Address Trap Source

0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E Reserved 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved

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6.3 Interrupt Control and Status Registers

dsPIC33FJ12GP201/202 devices implement a total of 17 registers for the interrupt controller:

• Interrupt Control Register 1 (INTCON1)

• Interrupt Control Register 2 (INTCON2)

• Interrupt Flag Status Registers (IFSx)

• Interrupt Enable Control Registers (IECx)

• Interrupt Priority Control Registers (IPCx)

• Interrupt Control and Status Register (INTTREG)

6.3.1 INTCON1 AND INTCON2

Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and stat us f lag s fo r the processor trap sour ces. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table.

6.3.2 IFSx

The IFS registers maintain all of the interrupt request flags. Each source of inte rrupt has a st atus bit, w hich is set by the respect ive periph erals or exter nal si gna l and is cleared v ia software.

6.3.3 IECx

The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals.

6.3.4 IPCx

The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels.

6.3.5 INTTREG

The INTTREG register contains the associated interrupt vector number and the new CPU interrupt priority level, which are latched into vector number (VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt.

The interrupt sources are assigned to the IFSx, IECx and IPCx registers in th e s ame se quence that they are listed in Table 6-1. For example, the INT0 (External Interrupt 0) is shown as having vector number 8 and a natural order priority of 0. Thus, the INT0IF bit is found in IFS0<0>, the INT0IE bit in IEC0< 0>, a nd th e INT0 IP bits in the first position of IPC0 (IPC0<2:0>).

6.3.6 STATUS REGISTERS

Although they are not specifically part of the interrupt control hardware, two of the CPU Control registers contain bits that control interrupt functionality:

• The CPU STATUS register, SR, contains the IPL<2:0> bits (SR<7:5>). These bits indicate the current CPU interrupt priority level. The user can change the current CPU prio rity lev el by wri ting to the IPL bits.

• The CORCON register contains the IPL3 bit which, together with IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit, so that trap event s c ann ot be m as ke d b y t he user software.

All Interrupt registers are described in Register 6-1 through Register6-19 in the following pages.

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(1)

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA SB OAB SAB DA DC

bit 15 bit 8

R/W-0

IPL2

(3)

(2)

R/W-0

IPL1

(2)

(3)

R/W-0

IPL0

(2)

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

(1)

Note 1: For complete register details, see Register 2-1: “SR: CPU Status Register”.

2: The IPL<2:0> bits are con caten ated with the IPL<3 > bi t (CO RCON<3>) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

(1)

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — — US EDT DL<2:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

(2)

PSV RND IF

bit 7 bit 0

Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

(2)

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

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REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled

bit 14 OVAERR: Accumulator A Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A

bit 13 OVBERR: Accumulator B Overflow Trap Flag bit

1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B

bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrop hic overflow of Accumulator A

bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit

1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrop hic overflow of Accumulator B

bit 10 OVATE: Accumulator A Overflow Trap Enable bit

1 = Trap overflow of Accumulator A 0 = Trap disabled

bit 9 OVBTE: Accumulator B Overflow Trap Enable bit

1 = Trap overflow of Accumulator B 0 = Trap disabled

bit 8 COVTE: Catastrophic Overflow Trap Enable bit

1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled

bit 7 SFTACERR: Shift Accumulator Error Status bit

1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift

bit 6 DIV0ERR: Arithmetic Error Status bit

1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero

bit 5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Status bit

1 = Math error trap has occurred 0 = Math error trap has not occurred

bit 3 ADDRERR: Address Error Trap Status bit

1 = Address error trap has occurred 0 = Address error trap has not occurred

— MATHERR ADDRERR STKERR OSCFAIL —

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bit 2 STKERR: Stack Error Trap Status bit

1 = Stack error trap has occurred 0 = Stack error trap has not occurred

bit 1 OSCFAIL: Oscillator Failure Trap Status bit

1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred

bit 0 Unimplemented: Read as ‘0’

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REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0

ALTIVT DISI

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — INT2EP INT1EP INT0EP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit

1 = Use alternate vector table 0 = Use standard (default) vector table

bit 14 DISI: DISI Instruction S t atus bit

1 = DISI instruction is active 0 = DISI instruction is not active

bit 13-3 Unimplemented: Read as ‘0’ bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1 = Interrupt on negative edge 0 = Interrupt on positive edge

— — — — — —

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REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IF OC2IF IC2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 8 T3IF: Timer3 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 7 T2IF: Timer2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

— T1IF OC1IF IC1IF INT0IF

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bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 INT0IF: External Interrupt 0 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

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REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

— —INT2IF— — — — —

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

IC8IF IC7IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 12-8 Unimplemented: Read as ‘0’ bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 3 CNIF: Input Change Notification Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

— INT1IF CNIF — MI2C1IF SI2C1IF

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REGISTER 6-7: IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —U1EIF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIF: UAR T1 Error Interru pt Flag Status bit

1 = Interrupt request has occurred 0 = Interrupt request has not occurred

bit 0 Unimplemented: Read as ‘0’

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REGISTER 6-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

T2IE OC2IE IC2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 10 SPI1IE: SPI1 Event Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 8 T3IE: Timer3 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 7 T2IE: Timer2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

— T1IE OC1IE IC1IE INT0IE

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bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 INT0IE: External Interrupt 0 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

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REGISTER 6-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 0

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

— —INT2IE— — — — —

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

IC8IE IC7IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 12-8 Unimplemented: Read as ‘0’ bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 3 CNIE: Input Change Notification Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

— INT1IE CNIE — MI2C1IE SI2C1IE

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REGISTER 6-10: IEC4: INTERRUPT ENABLE CONTROL REGISTER 0

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — —U1EIE—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit

1 = Interrupt request enabled 0 = Interrupt request not enabled

bit 0 Unimplemented: Read as ‘0’

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REGISTER 6-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T1IP<2:0> — OC1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC1IP<2:0> — INT0IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 6-12: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— T2IP<2:0> — OC2IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— IC2IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bi ts

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 6-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— U1RXIP<2:0> — SPI1IP<2:0>

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— SPI1EIP<2:0> — T3IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiv er Interru pt Priori ty bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 6-14: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— AD1IP<2:0> — U1TXIP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 6-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

—CNIP<2:0>— — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— MI2C1IP<2:0> — SI2C1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 6-16: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0

— IC8IP<2:0> —IC7IP<2:0>

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0

— — — — — INT1IP<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bi ts

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Captur e Channel 7 Interrupt Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

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REGISTER 6-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— INT2IP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 6-18: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0

— U1EIP<2:0> — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bit s

111 = Interrupt is priority 7 (highest priority interrupt)

•

001 = Interrupt is priority 1 000 = Interrupt source is disabled

bit 3-0 Unimplemented: Read as ‘0’

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REGISTER 6-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — —ILR<3:0>

bit 15 bit 8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

— VECNUM<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits

1111 = CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0

bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM: Vector Number of Pending Interrupt bits

0111111 = Interrupt Vector pending is number 135

•

0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8

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6.4 Interrupt Setup Procedures

6.4.1 INITIALIZATION

To configure an interrupt source at initialization:

1. Set the NSTDIS bit (INTCON1<15>) if nested interrup ts are not desired.

2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If m ultiple pri ority leve ls are not desired, the IPCx register control bits for all enabled interrupt sources can be programmed to the same non-zero value.

Note: At a device Reset, the IPCx regist ers are

initialized such that all user interrupt sources are assigned to priority level 4.

3. Clear the interrupt flag status bit associa ted with the peripheral in the associated IFSx register.

4. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx regis ter.

6.4.2 INTERRUPT SERVICE ROUTINE

The method used to d eclare an ISR and ini tialize the IVT with the correct vector address depends on the programming language (C or Assembler) and the language development toolsuite used to develop the application.

In general, the us er a pp lic ati on m ust c le ar the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the program will re-enter the ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level.

6.4.3 TRAP SERVICE ROUTINE

A Trap Service Routine is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avo id re-entry in to the TSR.

6.4.4 INTERRUPT DISABLE

All user interrupts can be disabled using this procedure:

1. Push the current SR value onto the software stack using the PUSH instruction.

2. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL.

To enable user interrupts, the POP instruction can be used to restore the previous SR value.

Note: Only user interrupts with a priority level of

7 or lower can be disabled. Trap sources (level 8-level 15) cannot be disabled.

The DISI instruction provides a convenient way to disable interrupt s of priorit y levels 1-6 for a fi xed p eriod of time. Level 7 interrupt sources are not disabled by the DISI instruction.

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NOTES:

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dsPIC33F

Secondary Oscillator

LPOSCEN

SOSCO

SOSCI

Timer1

OSCI

OSCO

Primary Oscillator

XTPLL, HSPLL,

XT, HS, EC

FRCDIV<2:0>

WDT, PWRT,

FSCM

FRCDIVN

SOSC

FRCDIV16

ECPLL, FRCPLL

NOSC<2:0> FNOSC<2:0>

Reset

FRC

Oscillator

LPRC

Oscillator

DOZE<2:0>

S1/S3

FRC

LPRC

÷16

Clock Switch

Clock Fail

TUN<5:0>

PLL

(1)

FCY

FOSC

FRCDIV

DOZE

Note 1: See Figure 7-2 for PLL details.

7.0 OSCILLATOR CONFIGURATION

• An on-chip PLL to scale the internal operating frequency to the required system clock frequency

• An internal FRC oscillator that can also be used

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family

Reference Manual, “Section 7. Oscillator” (DS70186), which i s av ail abl e

from the Microchip website (www.microchip.com).

with the PLL, thereby allowing full-speed operation without any external clock generation hardware

• Clock switching between various clock sources

• Programmable clock pos t s ca ler f or s ys tem po wer savings

• A Fail-Safe Clock Monitor (FSCM) that detects clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator

The dsPIC33FJ12GP201/202 oscillator system provides:

• External and internal oscillator options as clock

selection.

A simplified diagram of the oscillator system is shown in Figure 7-1.

sources

FIGURE 7-1: dsPIC33FJ12GP201/202 OSCILLATOR SYSTEM DIAGRAM

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FCY = FOSC/2

7.1 CPU Clocking System

The dsPIC33FJ12GP201/202 devices provide seven system clock options:

• Fast RC (FRC) Oscillator

• FRC Oscillator with PLL

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

• Secondary (LP) Oscillator

• Low-Power RC (LPRC) Oscillator

• FRC Oscillator with post s ca ler

7.1.1 SYSTEM CLOCK SOURCES

7.1.1.1 Fast RC

The Fast RC (FRC) inte rnal osci llator runs at a nom inal frequency of 7.37 MHz. User software can tune the FRC frequency. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is div ided. This factor is select ed using the FRCDIV<2:0> (CLKDIV<10:8>) bits.

7.1.1.2 Primary

The primary oscillator can use one of the following as its clock source:

• XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is connected to the OSC1 and OSC2 pins.

• HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. The crystal is connected to the OSC1 and OSC2 pins.

• EC (External Clock): The external clock signal is directly ap plied to the OSC1 pin.

7.1.1.3 Secondary

The secondary (LP) os cillator is design ed for low power and uses a 32.768 kHz crystal or ceramic resonator. The LP oscillator uses the SOSCI and SOSCO pins.

7.1.1.4 Low-Power RC

The Low-Power RC (LPRC) internal oscIllator runs at a nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

7.1.1.5 FRC

The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase-Locked Loop (PLL) to provide a wide range of output frequencies for device operation. PLL configuration is described in Section 7.1.3 “PLL Configuration”.

The FRC frequency depends on the FRC accuracy (see Table21-18) and the value of the FRC Oscillator Tuning register (see Register7-4).

7.1.2 SYSTEM CLOCK SELECTION

The oscillator sourc e used at a dev ice Po wer-on R eset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. (Refer to Section 18.1 “Configuration Bits” for further details.) The Initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator is the default (unprogrammed) selection.

The Configuration bit s allow users to ch oose among 12 different clock modes, shown in Table 7-1.

The output of the oscillator (or the output of the PLL if a PLL mode has bee n select ed) F generate the device instruction clock (F defines the operating speed of the device, and speeds up to 40 MHz are supported by the dsPIC33FJ12GP201/202 arc hit ect ure.

Instruction execution speed or device operating frequency, F

CY , is given by Equation7-1.

OSC is divided by 2 to

CY). FCY

EQUATION 7-1: DEVICE OPERATING

FREQUENCY

7.1.3 PLL CONFIGURATION

The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 7-2.

The output of the p rimary osci llator or FR C, denote d as

IN’, is divided down by a prescale factor (N1) of 2,

‘F 3,..., or 33 before being provided to the PLL’s Voltage Controlled Oscillator (VCO). The input to the VCO must be selected in the range of 0.8 MHz to 8 MHz. The prescale factor ‘N1’ is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>).

The PLL Feedback Divisor, selected using the PLLDIV<8:0> bit s ( PLLFBD< 8: 0>), pro vid es a fa ctor ‘ M,’ by which the input to the VCO is multiplied. This factor must be selected such that the resulting VCO output frequency is i n t he ra nge of 100 MHz to 200 MHz.

The VCO output is fu rther di vided by a post scale f act or ‘N2.’ This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4, or 8, and must be selected such that the PLL output frequency

OSC) is in the range of 12.5 MHz to 80 MHz, which

(F generates device operating speeds of 6.25-40 MIPS.

For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F

OSC’ is given by Equation 7-2.

IN’,

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(

)

N1*N2

FOSC = FIN*

FCY

OSC

= 1

(

10000000*32

) = 40 MIPS

2*2

0.8-8.0 MHz Here

100-200 MHz

Here

Divide by

2, 4, 8

Divide by

2-513

Divide by

2-33

Source (Crystal, External Clock

PLLPRE

VCO

PLLDIV

PLLPOST

or Internal RC)

12.5-80 MHz Here

FOSC

EQUATION 7-2: FOSC CALCULATION

For example, suppose a 10 MHz crystal is being used, with “XT with PLL” being the selected oscillator mode.

• If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz.

• If PLLDIV<8:0> = 0x1 E, then M = 32 . This yie lds a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed.

• If PLLPOST<1:0> = 0, then N2 = 2. This pro vi des a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS.

EQUATION 7-3: XT WITH PLL MODE

FIGURE 7-2: dsPIC33FJ12GP201/202 PLL BLOCK DIAGRAM

EXAMPLE

TABLE 7-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Fast RC Oscillator with Divide-by-N (FRCDIVN) Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1

Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011 Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

Oscillator Mode

Oscillator

Source

Internal xx 110 1

POSCMD<1:0> FNOSC<2:0> Note

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REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y

—COSC<2:0>—NOSC<2:0>

bit 15 bit 8

R/W-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0

CLKLOCK IOLOCK LOCK —CF — LPOSCEN OSWEN

bit 7 bit 0

Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)

000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n

bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits

bit 7 CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled (FOSC<FCKSM> = 0b01)

1 = Clock swit ching is disabled, system clock source is locke d 0 = Clock switching is enabled, system clock source can be modified by clock switching

bit 6 IOLOCK: Peripheral Pin Select Lock bit

1 = Peripherial Pin Select is locked, write to peripheral pin select register is not allowed 0 = Peripherial Pin Select is unlocked, write to peripheral pin select register is allowed

bit 5 LOCK: PLL Lock Sta tus bit (read-o nly)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure

bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit

1 = Enable secondary oscillator 0 = Disable secondary oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete

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REGISTER 7-2: CLKDIV: CLOCK DIVISOR REGISTER

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

ROI DOZE<2:0> DOZEN

(1)

bit 15 bit 8

R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PLLPOST<1:0>

— PLLPRE<4:0>

bit 7 bit 0

Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE<2:0>: Processor Clock Reduct ion Select bits

000 = F 001 = F 010 = F 011 = F 100 = F 101 = F 110 = F 111 = F

bit 11 DOZEN: DOZE Mode Enable bit

CY/1 CY/2 CY/4 CY/8 (default) CY/16 CY/32 CY/64 CY/128

(1)

1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1

bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits

000 = FRC divide by 1 (default) 001 = FRC divide by 2 010 = FRC divide by 4 011 = FRC divide by 8 100 = FRC divide by 16 101 = FRC divide by 32 110 = FRC divide by 64 111 = FRC divide by 256

bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)

00 = Output/2 01 = Output/4 (default) 10 = Reserved 11 = Output/8

bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)

00000 = Input/2 (default) 00001 = Input/3

•

• 11111 = Input/33

FRCDIV<2:0>

Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.

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REGISTER 7-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —PLLDIV<8>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

PLLDIV<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)

000000000 = 2 000000001 = 3 000000010 = 4

•

• 000110000 = 50 (default)

•

• 111111111 = 513

(1)

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REGISTER 7-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN<5:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits

011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz)

•

000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz)

•

100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz)

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7.2 Clock Switching Operation

Applications are free to switch among any of the four clock sources (Primary, LP, FRC, and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ12GP201/202 devices have a safeguard lock built into the switch process.

Note: Primary Oscillator mode has three different

submodes (XT, HS, and EC), which are determined by the POSCMD<1:0> Configuration bits. While an application can switch to and from Primary Oscillator mode in softwa re , it c an no t swi t ch am ong the different primary submodes without reprogramming the device.

7.2.1 ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration bit in the Configuration reg ister must be program med to ‘0’. (Refer to Section 18.1 “Configuration Bits” for further details.) If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting.

The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at ‘0’ at all times.

7.2.2 OSCILLATOR SWITCHING SEQUENCE

Performing a clock switch requires this basic sequence:

1. If desired, read the COSC bits

(OSCCON<14:12>) to determine the current oscillator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NO SC contro l

bits (OSCCON<10:8>) for the new oscillator source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

Once the basic sequence is completed, the system clock hardware responds automatically as follows:

1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted.

2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bit s are cl eare d.

3. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware waits until the Oscillator Start-up Timer (OST) expires. If the new source is usin g the PLL, the ha rdware wait s until a PLL lock is detected (LOCK = 1).

4. The hardware waits for 10 clock cycles from th e new clock source and then performs the clock switch.

5. The hardware clears th e O SWEN bit t o indic ate a successful clock transition. In addition, the NOSC bit values are transf erred to the COSC st atus bit s.

6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set).

Note 1: The processor con tinues to e xecut e cod e

throughout the cloc k switch ing se quence. Timing-sensitive code should not be executed during this time.

2: Direct clock switches between any primary

oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes.

7.3 Fail-Safe Clock Monitor (FSCM)

The Fail-Safe Clock Monito r (FSCM) all ow s the devic e to continue to ope rate eve n in th e even t of an oscil lat or failure. The FSCM fun ction is enab led by programmin g. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer.

In the event of an oscillator failure, the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. Then the application program can either attempt to restart the oscillator or execute a controlled shutdown. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector.

If the PLL multiplier is used to scale the system clock, the internal FRC is also multiplied by the same factor on clock failure. Essentially, the device switches to FRC with PLL on a clock failure.

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PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode

8.0 POWER-SAVING FEATURES

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family

Reference Manual, “Section 9. Watchdog Timer and Power Savings Modes” (DS70196), which is available

from the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequen cy and a reduc tion in th e number of circuits being clocked constitutes lower consumed power. dsPIC33FJ12GP201/202 devices can manage power c onsum ption in fou r dif fe rent ways:

• Clock frequency

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software Combinations of these methods can be used to

selectively tailor an application’s power consumption while still maintaining critical application feature s, suc h as timing-sensitive communications.

8.1 Clock Frequency and Clock Switching

dsPIC33FJ12GP201/202 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON<10: 8 >) . T h e pr oc es s o f chan gi n g a sy stem clock during operation, as well as limitations to the process, are discussed in more detai l in Section 7.0

“Oscillator Configuration”.

8.2 Instruction-Based Power-Saving Modes

dsPIC33FJ12GP201/202 devices have two special power-saving modes that are entered through the execution of a spec ial PWRSAV instru ction. Sleep m ode stops clock op eration and halt s all c ode ex ec uti on. Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The Assembler syntax of the PWRSAV instruction is shown in Example 8-1.

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include file for the selected device.

Sleep and Idle modes can be exit ed as a result of an enabled interrupt, WDT time-out, or a device Reset. When the device exits these modes, it is said to wake-up.

8.2.1 SLEEP MODE

The following occur in Sleep mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing current

• The Fail-Safe Clock Monitor does not operate,

since the system clock sourc e is dis ab led

• The LPRC clock contin ues to run if the WDT is

enabled

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode

• Some device features or peripherals may continu e

to operate. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input.

• Any peripheral that requires the system clock

source for its operation is disab led

The device will wak e-up from Slee p mode on an y of the these events:

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts with the same clock source that was active when Sleep mode was entered.

EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX

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8.2.2 IDLE MODE

The following occur in Idle mode:

• The CPU stops executing instructions

• The WDT is automatically cleared

• The system clock source remains active. By default, all periphera l modules contin ue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “Peripheral Module Disable”).

• If the WDT or FSCM is enabled, the LPRC also remains active.

The device will wake from Idle mode on any of these events:

• Any interrupt that is individually enabled

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to the CPU and instructio n executio n be gins imm ediate ly, starting with the instruction following the PWRSAV instruction, or the first instruction in the ISR.

8.2.3 INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed. The device then wakes up from Sleep or Idle mode.

8.3 Doze Mode

The preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. In some circumstances , thi s may not be practical. For exam pl e, it may be necessary for an application to maintain uninterrupted sync hronou s commun icati on, even whil e it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely.

Doze mode is a simpl e and effecti ve alternative m ethod to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed, while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate.

Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE<2:0> bits (CLKDIV<14:12>). There are eight possible configurations, from 1 :1 to 1:128, with 1:1 being the default setting.

Programs can use Doze mode to selectively reduce power cons umption in event-driv en applicat ions. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU idles, waiting for something to invoke an interrupt routine. An auto matic return to full-speed CPU operation on interrupts can be enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.

For example, suppose the device is operating at 20 MIPS and the UART module has been configured for 500 kbps based on this device operating speed. If the device is placed in Doze mode with a clock frequency ratio of 1:4, the UART module continues to communicat e at the re quired bi t rate o f 500 kbps, bu t the CPU now starts executing instructions at a frequency of 5 MIPS.

8.4 Peripheral Module Disable

The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid.

A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral is supported by the specific dsPIC variant. If the peripheral is present in the device, it is enabled in the PMD register by default.

Note: If a PMD bit is set, the corresponding mod-

ule is disabled after a delay of o ne instruction cycle. Similarly , if a PMD bit is cleared, the corresponding modu le is enable d aft er a delay of one inst ruct io n c ycle (assuming the module control registers are already configured to enable modul e opera tion).

DSC

Datasheet dsPIC33FJ12GP201, dsPIC33FJ12GP202 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC33FJ12GP201/202 BLOCK DIAGRAM

TABLE 1-1: PINOUT I/O DESCRIPTIONS

2.0 CPU

2.1 Data Addressing Overview

2.2 DSP Engine Overview

2.3 Special MCU Features

FIGURE 2-1: dsPIC33FJ12GP201/202 CPU CORE BLOCK DIAGRAM

FIGURE 2-2: dsPIC33FJ12GP201/202 PROGRAMMER’S MODEL

2.4 CPU Control Registers

REGISTER 2-1: SR: CPU STATUS REGISTER

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

2.5 Arithmetic Logic Unit (ALU)

2.5.1 MULTIPLIER

2.5.2 DIVIDER

2.6 DSP Engine

FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM

2.6.1 MULTIPLIER

2.6.3 BARREL SHIFTER

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

FIGURE 3-1: PROGRAM MEMORY FOR dsPIC33FJ1 2GP2 01/202 DEVICES

3.1.1 PROGRAM MEMORY ORGANIZATION

3.1.2 INTERRUPT AND TRAP VECTORS

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

3.2 Data Address S pace

3.2.1 DATA SPACE WIDTH

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

3.2.3 SFR SPACE

3.2.4 NEAR DATA SPACE

FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ12GP201/202 DEVICES WITH 1 KB RAM

3.2.5 X AND Y DATA SPACES

TABLE 3-1: CPU CORE REGISTERS MAP

TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP202

TABLE 3-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP201

TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP

TABLE 3-5: TIMER REGISTER MAP

TABLE 3-6: INPUT CAPTURE REGISTER MAP

TABLE 3-7: OUTPUT COMPARE REGISTER MAP

TABLE 3-8: I2C1 REGISTER MAP

TABLE 3-9: UART1 REGISTER MAP

TABLE 3-10: SPI1 REGISTER MAP

TABLE 3-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP

TABLE 3-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12GP202

TABLE 3-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12GP201

TABLE 3-14: ADC1 REGISTER MAP FOR dsPIC33FJ12GP201

TABLE 3-15: ADC1 REGISTER MAP FOR dsPIC33FJ12GP202

TABLE 3-16: PORTA REGISTER MAP

TABLE 3-17: PORTB REGISTER MAP FOR dsPIC33FJ12GP202

TABLE 3-18: PORTB REGISTER MAP FOR dsPIC33FJ12GP201

TABLE 3-19: SY STEM CONTROL REGISTER MAP

TABLE 3-20: NVM REGISTER MAP

TABLE 3-21: PMD REGISTER MAP

3.2.6 SOFTWARE STACK

FIGURE 3-4: CALL STACK FRAME

3.2.7 DATA RAM PROTECTION FEATURE

3.3 Instruction Addressing Modes

3.3.1 FILE REGISTER INSTRUCTIONS

3.3.2 MCU INSTRUCTIONS

TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED

3.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS

3.3.5 OTHER INSTRUCTIONS

3.3.4 MAC INSTRUCTIONS

3.4 Modulo Addressing

3.4.1 START AND END ADDRESS

3.4.2 W ADDRESS REGISTER SELECTION

FIGURE 3-5: MODULO ADDRESSING OPERATION EXAMPLE

3.4.3 MODULO ADDRESSING APPLICABILITY

3.5 Bit-Reversed Addressing

3.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION

FIGU R E 3-6 : BIT-REVERSED ADDRESS EXAMPLE

TABLE 3-23: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

3.6 Interfacing Program and Data Memory Spaces

3.6.1 ADDRESSING PROGRAM SPACE

TABLE 3-24: PROGRAM SPACE ADDRESS CONSTRUCTION

FIGURE 3-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION