Datasheet dsPIC33FJ06GS102 Datasheet

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Page 1

dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04

Data Sheet

High-Performance,

16-bit Digital Signal Controllers

Page 2

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC

logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

Page 3

dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04

High-Performance, 16-Bit Digital Signal Controllers

Operating Range:

• Up to 40 MIPS Operation (at 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

High-Performance DSC CPU:

• Modified Harvard Architecture

• C Compiler Optimized Instruction Set

• 16-Bit Wide Data Path

• 24-Bit Wide Instructions

• Linear Program Memory Addressing up to 4M Instruction Words

• Linear Data Memory Addressing up to 64 Kbytes

• 83 Base Instructions: Mostly 1 Word/1 Cycle

• Two 40-Bit Accumulators with Rounding and Saturation Options

• Flexible and Powerful Addressing modes:

-Indirect

- Modulo

- Bit-Reversed

• Software Stack

• 16 x 16 Fractional/Integer Multiply Operations

• 32/16 and 16/16 Divide Operations

• Single-Cycle Multiply and Accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

• Up to ±16-Bit Shifts for up to 40-Bit Data

Digital I/O:

• Peripheral Pin Select Functionality

• Up to 35 Programmable Digital I/O Pins

• Wake-up/Interrupt-on-Change for up to 30 Pins

• Output Pins can Drive Voltage from 3.0V to 3.6V

• Up to 5V Output with Open-Drain Configuration

• 5V Tolerant Digital Input Pins (except RB5)

• 16 mA Source/Sink on All PWM pins

On-Chip Flash and SRAM:

• Flash Program Memory (up to 16 Kbytes)

• Data SRAM (up to 2 Kbytes)

• Boot and General Security for Program Flash

Peripheral Features:

• Timer/Counters, up to Three 16-Bit Timers:

- Can pair up to make one 32-bit timer

• Input Capture (up to two channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to two channels):

- Single or Dual 16-Bit Compare mode

- 16-Bit Glitchless PWM mode

• 4-Wire SPI:

- Framing supports I/O interface to simple codecs

- 1-deep FIFO Buffer.

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

•I

C™:

- Supports Full Multi-Master Slave mode

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

•UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

encoding and decoding in hardware

Interrupt Controller:

• 5-Cycle Latency

• Up to 35 Available Interrupt Sources

• Up to Three External Interrupts

• Seven Programmable Priority Levels

• Four Processor Exceptions

Page 4

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

High-Speed PWM Module Features:

• Up to Four PWM Generators with Four to Eight Outputs

• Individual Time Base and Duty Cycle for each of the Eight PWM Outputs

• Dead Time for Rising and Falling Edges

• Duty Cycle Resolution of 1.04 ns

• Dead-Time Resolution of 1.04 ns

• Phase Shift Resolution of 1.04 ns

• Frequency Resolution of 1.04 ns

• PWM modes Supported:

- Standard Edge-Aligned

- True Independent Output

- Complementary

- Center-Aligned

- Push-Pull

-Multi-Phase

- Variable Phase

- Fixed Off-Time

- Current Reset

- Current-Limit

• Independent Fault/Current-Limit Inputs for 8 PWM Outputs

• Output Override Control

• Special Event Trigger

• PWM Capture Feature

• Prescaler for Input Clock

• Dual Trigger from PWM to ADC

• PWMxL, PWMxH Output Pin Swapping

• PWM4H, PWM4L Pins Remappable

• On-the-Fly PWM Frequency, Duty Cycle and Phase Shift Changes

• Disabling of Individual PWM Generators

• Leading-Edge Blanking (LEB) Functionality

High-Speed Analog Comparator

• Up to Four Analog Comparators:

- 20 ns response time

- 10-bit DAC for each analog comparator

- DACOUT pin to provide DAC output

- Programmable output polarity

- Selectable input source

- ADC sample and convert capability

• PWM Module Interface:

- PWM duty cycle control

- PWM period control

- PWM Fault detect

High-Speed 10-Bit ADC

• 10-Bit Resolution

• Up to 12 Input Channels Grouped into Six Conversion Pairs

• Two Internal Reference Monitoring Inputs Grouped into a Pair

• Successive Approximation Register (SAR) Converters for Parallel Conversions of Analog Pairs:

- 4 Msps for devices with two SARs

- 2 Msps for devices with one SAR

• Dedicated Result Buffer for each Analog Channel

• Independent Trigger Source Section for each Analog Input Conversion Pair

Power Management:

• On-Chip 2.5V Voltage Regulator

• Switch between Clock Sources in Real Time

• Idle, Sleep, and Doze modes with Fast Wake-up

CMOS Flash T echnology:

• Low-Power, High-Speed Flash Technology

• Fully Static Design

• 3.3V (±10%) Operating Voltage

• Industrial and Extended Temperature

• Low-Power Consumption

System Management:

• Flexible Clock Options:

- External, crystal, resonator, internal RC

- Phase-Locked Loop (PLL) with 120 MHz VCO

- Primary Crystal Oscillator (OSC) in the range

of 3 MHz to 40 MHz

- Internal Low-Power RC (LPRC) oscillator at a

frequency of 32 kHz

- Internal Fast RC (FRC) oscillator at a

frequency of 7.37 MHz

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• Watchdog Timer with its RC Oscillator

• Fail-Safe Clock Monitor (FSCM)

• Reset by Multiple Sources

• In-Circuit Serial Programming™ (ICSP™)

• Reference Oscillator Output

Page 5

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Application Examples

• AC-to-DC Converters

• Automotive HID

• Battery Chargers

• DC-to-DC Converters

• Digital Lighting

• Induction Cooking

• LED Ballast

• Renewable Power/Pure Sine Wave Inverters

• Uninterruptible Power Supply (UPS)

Packaging:

• 18-Pin SOIC

• 28-Pin SPDIP/SOIC/QFN-S

• 44-Pin TQFP/QFN

Note: See the dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families table for the exact peripheral features per device.

Page 6

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES

The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families

Remappable Peripherals

(3)

Device

dsPIC33FJ06GS101 18 6 256 8 2 0 1 1 1 2x2

dsPIC33FJ06GS102 28 6 256 16 2 0 1 1 1 2x2 0 3 0 1 1 3 6 21 SPDIP

dsPIC33FJ06GS202 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 SPDIP

dsPIC33FJ16GS402 28 16 2K 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 SPDIP

dsPIC33FJ16GS404 44 16 2K 30 3 2 2 1 1 3x2 0 3 0 1 1 4 8 35 QFN

dsPIC33FJ16GS502 28 16 2K 16 3 2 2 1 1 4x2

dsPIC33FJ16GS504 44 16 2K 30 3 2 2 1 1 4x2

Pins

RAM (Bytes)

Program Flash Memory (Kbytes)

16-bit Timer

Remappable Pins

Input Cap tur e

UART

Output Compare

(2)

SPI

PWM

Analog Compara tor

(1)

0 3 011 3 613SOIC

(1)

431126821SPDIP

(1)

4 3 1 1 2 6 12 35 QFN

DAC Output

External Interrupts

C™ I

SARs

ADC

I/O Pins

Packages

Analog-to-Digital Inputs

Sample and Hold (S&H) Circuit

SOIC

QFN-S

SOIC

QFN-S

SOIC

QFN-S

TQFP

SOIC

QFN-S

TQFP

Note 1: The PWM4H:PWM4L pins are remappable.

2: The PWM Fault pins and PWM synchronization pins are remappable. 3: Only two out of three interrupts are remappable.

Page 7

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

18-Pin SOIC

28-Pin SOIC, SPDIP

dsPIC33FJ06GS101

MCLR

AN0/RA0

AN1/RA1

VSS

AN2/RA2

TDO/RP5

(1)

/CN5/RB5

TMS/PGEC2/RP4

(1)

/CN4/RB4

TCK/PGED2/INT0/RP3

(1)

/CN3/RB3

CAP/VDDCORE

OSC2/CLKO/AN7/RP2

(1)

/CN2/RB2

OSC1/CLKI/AN6/RP1

(1)

/CN1/RB1 VSS

PGEC1/SDA1/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL1/RP6

(1)

/CN6/RB6

AN3/RP0

(1)

/CN0/RB0

7 8

12 11

PWM1L/RA3

PWM1H/RA4

dsPIC33FJ06GS102

MCLR

PWM1L/RA3 PWM1H/RA4 PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

RP12

(1)

/CN12/RB12

RP11

(1)

/CN11/RB11VSS

VDD

AN0/RA0 AN1/RA1

AVSS

AN2/RA2

PGED3/RP8

(1)

/CN8/RB8

PGEC3/RP15

(1)

/CN15/RB15

TMS/PGEC2/RP4

(1)

/CN4/RB4

TCK/PGED2/INT0/RP3

(1)

/CN3/RB3

CAP/VDDCORE

OSC2/CLKO/RP2

(1)

/CN2/RB2

OSC1/CLKIN/RP1

(1)

/CN1/RB1

TDO/RP5

(1)

/CN5/RB5

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

AN5/RP10

(1)

/CN10/RB10

AN4/RP9

(1)

/CN9/RB9

AN3/RP0

(1)

/CN0/RB0

1 2 3 4 5 6 7

8 9 10 11 12 13 14

28 27 26 25 24 23 22

21 20 19 18 17 16 15

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals

28-Pin SPDIP, SOIC

dsPIC33FJ06GS202

MCLR

PWM1L/RA3 PWM1H/RA4 PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/RP12

(1)

/CN12/RB12

TMS/RP11

(1)

/CN11/RB11VSS

VDD

AN0/CMP1A/RA0 AN1/CMP1B/RA1

AVSS

AN2/CMP1C/CMP2A/RA2

PGED3/RP8

(1)

/CN8/RB8

PGEC3/RP15

(1)

/CN15/RB15

PGEC2/EXTREF/RP4

(1)

/CN4/RB4

PGED2/DACOUT/INT0/RP3

(1)

/CN3/RB3

CAP/VDDCORE

OSC2/CLKO/RP2

(1)

/CN2/RB2

OSC1/CLKIN/RP1

(1)

/CN1/RB1

TDO/RP5

(1)

/CN5/RB5

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

AN5/CMP2D/RP10

(1)

/CN10/RB10

AN4/CMP2C/RP9

(1)

/CN9/RB9

AN3/CMP1D/CMP2B/RP0

(1)

/CN0/RB0

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

= Pins are up to 5V tolerant

Pin Diagrams

Page 8

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

28-Pin SPDIP, SOIC

dsPIC33FJ16GS402

MCLR

PWM1L/RA3 PWM1H/RA4 PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM 3H/RP11

(1)

/CN11/RB11VSS

VDD

AN0/RA0 AN1/RA1

AVSS

AN2/RA2

PGED3/RP8

(1)

/CN8/RB8

PGEC3/RP15/CN15/RB15

PGEC2/RP4

(1)

/CN4/RB4

PGED2/INT0/RP3

(1)

/CN3/RB3

CAP/VDDCORE

OSC2/CLKO/AN7/RP2

(1)

/CN2/RB2

OSC1/CLKIN/AN6/RP1

(1)

/CN1/RB1

TDO/RP5

(1)

/CN5/RB5

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

AN5/RP10

(1)

/CN10/RB10

AN4/RP9

(1)

/CN9/RB9

AN3/RP0

(1)

/CN0/RB0

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals

dsPIC33FJ16GS502

MCLR

PWM1L/RA3 PWM1H/RA4 PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11VSS

VDD

AN0/CMP1A/RA0 AN1/CMP1B/RA1

AVSS

AN2/CMP1C/CMP2A/RA2

CN8/RB8/PGED3/RP8

(1)

/CN8/RB8

PGEC3/RP15

(1)

/CN15/RB15

PGEC2/EXTREF/RP4

(1)

/CN4/RB4

PGED2/DACOUT/INT0/RP3

(1)

/CN3/RB3

CAP/VDDCORE

OSC2/CLKO/AN7/CMP3D/CMP4B/RP2

(1)

/CN2/RB2

OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1

(1)

/CN1/RB1

TDO/RP5

(1)

/CN6/RB5

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

AN5/CMP2D/CMP3B/RP10

(1)

/CN10/RB10

AN4/CMP2C/CMP3A/RP9

(1)

/CN9/RB9

AN3/CMP1D/CMP2B/RP0

(1)

/CN0/RB0

1 2 3 4 5 6 7

8 9 10 11 12 13 14

28 27 26 25 24 23 22

21 20 19 18 17 16 15

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 9

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

28-Pin QFN-S

(2)

10 11

2 3

12 13 14

232425262728

dsPIC33FJ06GS102

PGED2/INT0/RP3

(1)

/CN3/RB3

AVDD

AVSS

PWM1L/RA3

PWM1H/RA4

PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/RP12

(1)

/CN12/RB12

TMS/RP11

(1)

/CN11/RB11

VCAP/VDDCORE

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

TDO/RP5

(1)

/CN5/RB5

PGEC3/RP15

(1)

/CN15/RB15

MCLR

AN0/RA0

AN1/RA1

AN2/RA2

AN3/RP0

(1)

/CN0/RB0

AN4/RP9

(1)

/CN9/RB9

AN5/RP10

(1)

/CN10/RB10

OSC1/CLKIN/RP1

(1)

/CN1/RB1

OSC2/CLKO/RP2

(1)

/CN2/RB2

PGEC2/RP4

(1)

/CN4/RB4

PGED3/RP8

(1)

/CN8/RB8

10 11

2 3

12 13 14

232425262728

dsPIC33FJ06GS202

PGED2/DACOUT/INT0/RP3

(1)

/CN3/RB3

AVDD

AVSS

PWM1L/RA3

PWM1H/RA4

PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/RP12

(1)

/CN12/RB12

TMS/RP11

(1)

/CN11/RB11

VCAP/VDDCORE

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

TDO/RP5

(1)

/CN5/RB5

PGEC3/RP15

(1)

/CN15/RB15

MCLR

AN0/CMP1A/RA0

AN1/CMP1B/RA1

AN2/CMP1C/CMP2A/RA2

AN3/CMP1D/CMP2B/RP0

(1)

/CN0/RB0

AN4/CMP2C/RP9

(1)

/CN9/RB9

AN5/CMP2D/RP10

(1)

/CN10/RB10

OSC1/CLKIN/RP1

(1)

/CN1/RB1

OSC2/CLKO/RP2

(1)

/CN2/RB2

PGEC2/EXTREF/RP4

(1)

/CN4/RB4

PGED3/RP8

(1)

/CN8/RB8

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

SS externally.

= Pins are up to 5V tolerant

28-Pin QFN-S

(2)

Pin Diagrams (Continued)

Page 10

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

28-Pin QFN-S

(2)

10 11

2 3

12 13 14

232425262728

dsPIC33FJ16GS402

PGED2/INT0/RP3

(1)

/CN3/RB3

AVDD

AVSS

PWM1L/RA3

PWM1H/RA4

PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11

VCAP/VDDCORE

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

TDO/RP5

(1)

/CN5/RB5

PGEC3/RP15

(1)

/CN15/RB15

MCLR

AN0/RA0

AN1/RA1

AN2/RA2

AN3/RP0

(1)

/CN0/RB0

AN4/RP9

(1)

/CN9/RB9

AN5/RP10

(1)

/CN10/RB10

OSC1/CLKIN/AN6/RP1

(1)

/CN1/RB1

OSC2/CLKO/AN7/RP2

(1)

/CN2/RB2

PGEC2/RP4

(1)

/CN4/RB4

PGED3/RP8

(1)

/CN8/RB8

10 11

2 3

12 13 14

232425262728

dsPIC33FJ16GS502

PGED2/DACOUT/INT0/RP3

(1)

/CN3/RB3

AVDD

AVSS

PWM1L/RA3

PWM1H/RA4

PWM2L/RP14

(1)

/CN14/RB14

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11

VCAP/VDDCORE

PGEC1/SDA/RP7

(1)

/CN7/RB7

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

TDO/RP5

(1)

/CN5/RB5

PGEC3/RP15

(1)

/CN15/RB15

MCLR

AN0/CMP1A/RA0

AN1/CMP1B/RA1

AN2/CMP1C/CMP2A/RA2

AN3/CMP1D/CMP2B/RP0

(1)

/CN0/RB0

AN4/CMP2C/CMP3A/RP9

(1)

/CN9/RB9

AN5/CMP2D/CMP3B/RP10

(1)

/CN10/RB10

OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1

(1)

/CN1/RB1

OSC2/CLKO/AN7/CMP3D/CMP4B/RP2

(1)

/CN2/RB2

PGEC2/EXTREF/RP4

(1)

/CN4/RB4

PGED3/RP8

(1)

/CN8/RB8

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

SS externally.

28-Pin QFN-S

(2)

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 11

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

44-Pin QFN

(2)

dsPIC33FJ16GS404

43 42 41 40 39 38 37 36 35

12 13 14 15 16 17 18 19 20 21

2 32

AN4/RP9

(1)

/CN9/RB9

AN5/RP10

(1)

/CN10/RB10

OSC1/CLKI/AN6/RP1

(1)

/CN1/RB1

OSC2/CLKO/AN7/RP2

(1)

/CN2/RB2

AN8/CMP4C/RP17

(1)

/CN17/RC1

RP26

(1)

/CN26/RC10

RP25

(1)

/CN25/RC9

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

RP18

(1)

/CN18/RC2

PGEC3/RP15

(1)

/CN15/RB15

PGEC2/RP4

(1)

/CN4/RB4

RP24

(1)

/CN24/RC8

TDO/RP5

(1)

/CN5/RB5

PGED3/RP8

(1)

/CN8/RB8

RP23

(1)

/CN23/RC7

PGED2/INT0/RP3

(1)

/CN3/RB3

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11

CAP/VDDCORE

VSS

RP20

(1)

/CN20/RC4

RP19

(1)

/CN19/RC3

RP22

(1)

/CN22/RC6

RP21

(1)

/CN21/RC5

PGEC1/SDA/RP7

(1)

/CN7/RB7

PWM2L/RP14

(1)

/CN14/RB14

AN3/RP0

(1)

/CN0/RB0

AN2/RA2

AN1/RA1

AN0/RA0

MCLR

RP29

(1)

/CN29/RC13

AVSS

PWM1L/RA3

PWM1H/RA4

RP16

(1)

/CN16/RC0

RP28

(1)

/CN28/RC12

RP27

(1)

/CN27/RC11

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to

SS externally.

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 12

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

44-Pin QFN

(2)

dsPIC33FJ16GS504

43 42 41 40 39 38 37 36 35

12 13 14 15 16 17 18 19 20 21

2 32

AN4/CMP2C/CMP3A/RP9

(1)

/CN9/RB9

AN5/CMP2D/CMP3B/RP10

(1)

/CN10/RB10

OSC1/CLKI/AN6/CMP3C/CMP4A/RP1

(1)

/CN1/RB1

OSC2/CLKO/AN7/CMP3D/CMP4B/RP2

(1)

/CN2/RB2

AN8/CMP4C/RP17

(1)

/CN17/RC1

AN10/RP26

(1)

/CN26/RC10

AN11/RP25

(1)

/CN25/RC9

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

AN9/EXTREF/CMP4D/RP18

(1)

/CN18/RC2

PGEC3/RP15

(1)

/CN15/RB15

PGEC2/RP4

(1)

/CN4/RB4

RP24

(1)

/CN24/RC8

TDO/RP5

(1)

/CN5/RB5

PGED3/RP8

(1)

/CN8/RB8

RP23

(1)

/CN23/RC7

PGED2/DACOUT/INT0/RP3

(1)

/CN3/RB3

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11

CAP/VDDCORE

VSS

RP20

(1)

/CN20/RC4

RP19

(1)

/CN19/RC3

RP22

(1)

/RN22/RC6

RP21

(1)

/CN21/RC5

PGEC1/SDA/RP7

(1)

/CN7/RB7

PWM2L/RP14

(1)

/CN14/RB14

AN3/CMP1D/CMP2B/RP0

(1)

/CN0/RB0

AN2/CMP1C/CMP2A/RA2

AN1/CMP1B/RA1

AN0/CMP1A/RA0

MCLR

RP29

(1)

/CN29/RC13

AVSS

PWM1L/RA3

PWM1H/RA4

RP16

(1)

/CN16/RC0

RP28

(1)

/CN28/RC12

RP27

(1)

/CN27/RC11

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to connect to V

externally.

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 13

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

44-Pin TQFP

10 11

3 4 5

1819202122

121314

4443424140

363435

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

RP18

(1)

/CN18/RC2

PGEC3/RP15

(1)

/CN15/RB15

PGEC2/RP4

(1)

/CN4/RB4

RP16

(1)

/CN16/RC0

TDO/RP5

(1)

/CN5/RB5

PGED3/RP8

(1)

/CN8/RB8

RP23

(1)

/CN23/RC7

AN3/RP0

(1)

/CN0/RB0

AN2/RA2

AN1/RA1

AN0/RA0

MCLR

RP29

(1)

/CN29/RC13

AVSS

PWM1L/RA3

PWM1H/RA4

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11

VCAP/VDDCORE

RP19

(1)

/CN19/RC3

RP22

(1)

/CN22/RC6

RP21

(1)

/CN21/RC5

PGEC1/SDA/RP7

(1)

/CN7/RB7

AN4/RP9

(1)

/CN9/RB9

AN5/RP10

(1)

/CN10/RB10

OSC1/CLKI/AN6/RP1

(1)

/CN1/RB1

OSC2/CLKO/AN7/RP2

(1)

/CN2/RB2

RP17

(1)

/CN17/RC1

RP20

(1)

/CN20/RC4

VSS

RP27

(1)

/CN27/RC11

RP28

(1)

/CN28/RC12

PGED2/INT0/RP3

(1)

/CN3/RB3

dsPIC33FJ16GS404

PWM2L/RP14

(1)

/CN14/RB14

RP24

(1)

/CN24/RC8

RP25

(1)

/CN25/RC9

RP26

(1)

/CN26/RC10

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Con tro ller Fam ilie s” table for the list of available peripherals

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 14

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

44-Pin TQFP

10 11

3 4 5

1819202122

121314

4443424140

363435

PGED1/TDI/SCL/RP6

(1)

/CN6/RB6

AN9/EXTREF/CMP4D/RP18

(1)

/CN18/RC2

PGEC3/RP15

(1)

/CN15/RB15

PGEC2/RP4

(1)

/CN4/RB4

RP16

(1)

/CN16/RC0

TDO/RP5

(1)

/CN5/RB5

PGED3/RP8

(1)

/CN8/RB8

RP23

(1)

/CN23/RC7

AN3/CMP1D/CMP2B/RP0

(1)

/CN0/RB0

AN2/CMP1C/CMP2A/RA2

AN1/CMP1B/RA1

AN0/CMP1A/RA0

MCLR

RP29

(1)

/CN29/RC13

AVSS

PWM1L/RA3

PWM1H/RA4

PWM2H/RP13

(1)

/CN13/RB13

TCK/PWM3L/RP12

(1)

/CN12/RB12

TMS/PWM3H/RP11

(1)

/CN11/RB11

VCAP/VDDCORE

RP19

(1)

/CN19/RC3

RP22

(1)

/CN22/RC6

RP21

(1)

/CN21/RC5

PGEC1/SDA/RP7

(1)

/CN7/RB7

AN4/CMP2C/CMP3A/RP9

(1)

/CN9/RB9

AN5/CMP2D/CMP3B/RP10

(1)

/CN10/RB10

OSC1/CLKI/AN6/CMP3C/CMP4A/RP1

(1)

/CN1/RB1

OSC2/CLKO/AN7/CMP3D/CMP4B/RP2

(1)

/CN2/RB2

AN8/CMP4C/RP17

(1)

/CN17/RC1

RP20

(1)

/CN20/RC4

VSS

RP27

(1)

/CN27/RC11

RP28

(1)

/CN28/RC12

PGED2/DACOUT/INT0/RP3

(1)

/CN3/RB3

dsPIC33FJ16GS504

PWM2L/RP14

(1)

/CN14/RB14

RP24

(1)

/CN24/RC8

AN11/RP25

(1)

/CN25/RC9

AN10/RP26

(1)

/CN26/RC10

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals

= Pins are up to 5V tolerant

Pin Diagrams (Continued)

Page 15

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Product Families .......................................................................................... 4

1.0 Device Overview ........................................................................................................................................................................ 15

2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 19

3.0 CPU............................................................................................................................................................................................ 29

4.0 Memory Organization ................................................................................................................................................................. 41

5.0 Flash Program Memory.............................................................................................................................................................. 81

6.0 Resets ....................................................................................................................................................................................... 87

7.0 Interrupt Controller ..................................................................................................................................................................... 95

8.0 Oscillator Configuration ......................................................................................................................................................... 135

9.0 Power-Saving Features............................................................................................................................................................ 147

10.0 I/O Ports .................................................................................................................................................................................. 155

11.0 Timer1 ...................................................................................................................................................................................... 183

12.0 Timer2/3 features .................................................................................................................................................................... 185

13.0 Input Capture............................................................................................................................................................................ 191

14.0 Output Compare....................................................................................................................................................................... 193

15.0 High-Speed PWM..................................................................................................................................................................... 197

16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 217

17.0 Inter-Integrated Circuit (I

18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 231

19.0 High-Speed 10-bit Analog-to-Digital Converter (ADC)............................................................................................................. 237

20.0 High-Speed Analog Comparator .............................................................................................................................................. 259

21.0 Special Features ...................................................................................................................................................................... 263

22.0 Instruction Set Summary .......................................................................................................................................................... 271

23.0 Development Support............................................................................................................................................................... 279

24.0 Electrical Characteristics.......................................................................................................................................................... 283

25.0 Packaging Information.............................................................................................................................................................. 317

Appendix A: Revision History............................................................................................................................................................. 329

Index ................................................................................................................................................................................................. 337

The Microchip Web Site..................................................................................................................................................................... 341

Customer Change Notification Service .............................................................................................................................................. 341

Customer Support .............................................................................................................................................................................. 341

Reader Response .............................................................................................................................................................................. 342

Product Identification System ............................................................................................................................................................ 343

C™) ................................................................................................................................................. 223

Page 16

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Page 17

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the

Microchip web site (www.microchip.com)

for the latest “dsPIC33F F amily Refer ence Manual” sections.

This document contains device-specific information for the following dsPIC33F Digital Signal Controller (DSC) devices:

• dsPIC33FJ06GS101

• dsPIC33FJ06GS102

• dsPIC33FJ06GS202

• dsPIC33FJ16GS402

• dsPIC33FJ16GS404

• dsPIC33FJ16GS502

• dsPIC33FJ16GS504

PIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/

devices contain extensive Digital Signal Processor

X04 (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture.

Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

Page 18

OSC1/CLKI

OSC2/CLKO

DD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VCAP/VDDCORE

IC1,2

I2C1

PORTA

Instruction

Decode &

Control

PCH PCL

Program Counter

16-Bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV & Table Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Address Latch

Program Memory

Data Latch

Literal Data

Data Latch

Address

Latch

X RAM

Y RAM

Y Data Bus

X Data Bus

DSP Engine

Divide Support

Control Signals to Various Blocks

ADC1

Timers

PORTB

Address Generator Units

1-3

CNx

UART1

PWM

4 x 2

Remappable

Pins

PORTC

SPI1

OC1 OC2

Analog

Comparators 1-4

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features

present on each device.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM

Page 19

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN11 I Analog No Analog input channels

CLKI

CLKO

OSC1

OSC2

CN0-CN29 I ST No Change notification inputs. Can be software programmed for

IC1-IC2 I ST Yes Capture inputs 1/2

OCFA OC1-OC2

INT0 INT1 INT2

RA0-RA4 I/O ST No PORTA is a bidirectional I/O port

RB0-RB15 I/O ST No PORTB is a bidirectional I/O port

RC0-RC13 I/O ST No PORTC is a bidirectional I/O port

RP0-RP29 I/O ST No

T1CK T2CK T3CK

U1CTS U1RTS U1RX U1TX

SCK1 SDI1 SDO1 SS1

SCL1 SDA1

TMS TCK TDI TDO

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input

ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select

Type

I/O

I/O I/O

Buffer

Type

IOST/CMOS—NoNoExternal clock source input. Always associated with OSC1 pin

ST/CMOS—NoNoOscillator crystal input. ST buffer when configured in RC mode;

I I I

—

ST ST ST

—

ST ST

—

ST ST

TTL TTL TTL

—

PPS

Capable

function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

internal weak pull-ups on all inputs.

Yes

Compare Fault A input (for Compare Channels 1 and 2)

Yes

Compare Outputs 1 through 2

External Interrupt 0

Yes

External Interrupt 1

Yes

External Interrupt 2

Remappable I/O pins

Yes

Timer1 external clock input

Yes

Timer2 external clock input

Yes

Timer3 external clock input

Yes

UART1 clear to send

Yes

UART1 ready to send

Yes

UART1 receive

Yes

UART1 transmit

Yes

Synchronous serial clock input/output for SPI1

Yes

SPI1 data in

Yes

SPI1 data out

Yes

SPI1 slave synchronization or frame pulse I/O

NoNoSynchronous serial clock input/output for I2C1

Synchronous serial data input/output for I2C1

JTAG Test mode select pin

JTAG test clock input pin

JTAG test data input pin

JTAG test data output pin

Description

Page 20

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Type

CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B CMP4C CMP4D

DACOUT O — No DAC output voltage

ACMP1-ACMP4 O — Yes DAC trigger to PWM module

EXTREF I Analog No External voltage reference input for the reference DACs

REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system

FLT1-FLT8 SYNCI1-SYNCI2 SYNCO1 PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H PWM4L PWM4H

PGED1

O O O O O O O O O

I/O

PGEC1

PGED2

I/O

PGEC2

PGED3

I/O

PGEC3

MCLR

DD P P No Positive supply for analog modules. This pin must be connected at

SS P P No Ground reference for analog modules

DD P — No Positive supply for peripheral logic and I/O pins

CAP/VDDCORE P — No CPU logic filter capacitor connection

SS P — No Ground reference for logic and I/O pins

I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input

ST = Schmitt Trigger input with CMOS levels P = Power O = Output TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select

Buffer

Type

Analog

PPS

Capable

No No No No No No No No No No No No No No No No

Description

Comparator 1 Channel A Comparator 1 Channel B Comparator 1 Channel C Comparator 1 Channel D Comparator 2 Channel A Comparator 2 Channel B Comparator 2 Channel C Comparator 2 Channel D Comparator 3 Channel A Comparator 3 Channel B Comparator 3 Channel C Comparator 3 Channel D Comparator 4 Channel A Comparator 4 Channel B Comparator 4 Channel C Comparator 4 Channel D

clock

I I

ST ST

— — — — — — — — —

ST ST

Yes

Fault Inputs to PWM module

Yes

External synchronization signal to PWM Master Time Base

Yes

PWM master time base for external device synchronization

PWM1 low output

PWM1 high output

PWM2 low output

PWM2 high output

PWM3 low output

PWM3 high output

Yes

PWM4 low output

Yes

PWM4 high output

Data I/O pin for programming/debugging communication Channel 1

Clock input pin for programming/debugging communication Channel 1

Data I/O pin for programming/debugging communication Channel 2

Clock input pin for programming/debugging communication Channel 2

Data I/O pin for programming/debugging communication Channel 3

Clock input pin for programming/debugging communication Channel 3

device.

all times.

Page 21

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the dsPIC33F Family Reference Manual, which is available from

the Microchip website (www.microchip.com).

2.1 Basic Connection Requirements

Getting started with the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of 16-bit Digital Signal Controllers (DSC) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

DD and VSS pins

•All V

(see Section 2.2 “Decoupling Capacitors”)

•All AV

•VCAP/VDDCORE

•MCLR pin

• PGECx/PGEDx pins used for In-Circuit Serial

• OSC1 and OSC2 pins when external oscillator

DD and AVSS pins (regardless if ADC module

is not used)

(see Section 2.2 “Decoupling Capacitors”)

(see Section 2.3 “Capacitor on Internal Voltage

Regulator (V

(see Section 2.4 “Master Clear (MCLR) Pin”)

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

source is used

(see Section 2.6 “External Oscillator Pins”)

CAP/VDDCORE)”)

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of power supply pins, such as V

SS is required.

Consider the following criteria when using decoupling capacitors:

• Value and type of cap a cito r: Recommendation

of 0.1 μF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

• Handlin g high frequency noise: If the board is

experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 μF in parallel with 0.001 μF.

• Maximizing performance: On the board layout

from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

DD, VSS, AVDD and

Page 22

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

dsPIC33F

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 μF

Ceramic

0.1 μF

Ceramic

0.1 μF

Ceramic

0.1 μF

Ceramic

MCLR

0.1 μF Ceramic

VCAP/VDDCORE

10 Ω

Note 1: R ≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the MCLR

pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR

from the external capacitor C, in the

event of MCLR

pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR

IH and VIL specifications are met.

MCLR

dsPIC33F

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

2.2.1 TANK CAPACITORS

On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 μF to 47 μF.

2.4 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device functions:

• Device Reset

• Device programming and debugging.

During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR specific voltage levels (V transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR

pin during programming and debugging

operations.

Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

pin. Consequently,

IH and VIL) and fast signal

pin.

2.3 Capacitor on Internal Voltage Regulator (V

A low-ESR (< 5 Ohms) capacitor is required on the

CAP/VDDCORE pin, which is used to stabilize the

V voltage regulator output voltage. The V pin must not be connected to VDD, and must have a capacitor between 4.7 μF and 10 μF, 16V connected to ground. The type can be ceramic or tantalum. Refer to

Section 24.0 “Electrical Characteristics” for

additional information.

The placement of this capacitor should be close to the

CAP/VDDCORE. It is recommended that the trace

V length not exceed one-quarter inch (6 mm). Refer to

Section 21.2 “On-Chip Voltage Regulator” for

details.

CAP/VDDCORE)

CAP/VDDCORE

Page 23

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Main Oscillator

Guard Ring

Guard Trace

Secondary Oscillator

2.5 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (V

Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB ICE™.

For more information on ICD 2, ICD 3, and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website.

•“MPLAB

Guide” DS51331

•“Using MPLAB

•“MPLAB® ICD 2 Design Advisory” DS51566

•“Using MPLAB® ICD 3” (poster) DS51765

•“MPLAB

•“MPLAB® REAL ICE™ In-Circuit Debugger User's Guide” DS51616

•“Using MPLAB

IH) and input low (VIL) requirements.

ICD 2, MPLAB® ICD 3, or MPLAB® REAL

ICD 2 In-Circuit Debugger User's

ICD 2” (poster) DS51265

ICD 3 Design Advisory” DS51764

REAL ICE™” (poster) DS51749

2.6 External Oscillator Pins

Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency

secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR CIRCUIT

Page 24

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

2.7 Oscillator Value Conditions on Device Start-up

If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < F start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed.

Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV, and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word.

IN < 8 MHz to comply with device PLL

2.8 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the ADPCFG register.

The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device.

If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module.

When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of these registers is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality.

2.9 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor to V unused pins and drive the output to logic low.

SS on

2.10 Typical Application Connection Examples

Examples of typical application connections are shown in Figure 2-4 through Figure 2-11.

Page 25

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

VAC

IPFC

VHV_BUS

ADC Channel

PWM Output

AC|

FET

dsPIC33FJ06GS101

Driver

IPFC

VOUTPUT

ADC Channel

ADC

ADC Channel

PWM

FET

dsPIC33FJ06GS101

VINPUT

Channel Output

Driver

FIGURE 2-4: DIGITAL PFC

FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION

Page 26

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

Analog

Comp.

PWM

ADC

Channel

ADC

Channel

5V Output

12V Input

FET

Driver

dsPIC33FJ06GS202

Analog Comparator

ADC Channel

Analog Comparator

ADC

Channel

PWM

3.3V Output

12V Input

FET

Driver

FET

Driver

FET

Driver

dsPIC33FJ06GS502

FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER

FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER

Page 27

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

ADC

PWM PWMPWM

dsPIC33FJ16GS504

PWM PWM PWM

FET

Driver

FET

Driver

FET

Driver

FET

Driver

FET

Driver

FET

Driver

VBAT

GND

VOUT+

OUT-

Full-Bridge Inverter

Push-Pull Converter

GND

FET

Driver

ADC

PWM

Analog Comp.

Battery Charger

FIGURE 2-8: OFF-LINE UPS

Page 28

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

VAC

VOUT+

ADC Channel

PWM

ADC

PWM

AC|

FET

dsPIC33FJ06GS202

Driver

OUT-

ADC Channel

FET

Driver

ADC

Channel

ADC

Channel

FIGURE 2-9: INTERLEAVED PFC

Page 29

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

VIN+

IN-

Gate 4

Gate 2

Gate 3

Gate 1

Analog Ground

VOUT+

OUT-

dsPIC33FJ06GS202

PWM

PWM ADC

Channel

PWM ADC

Channel

FET

Driver

FET

Driver

FET

Driver

Gate 1

Gate 2

Gate 3

Gate 4

Gate 6

Gate 5

Gate 6

Gate 5

FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER

Page 30

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

ADC

Channel

PWM

UART

PWM

IZVT

VHV_BUS

VOUT

Isolation

Barrier

ADC

Channel

PWM

FET

Driver

FET

Driver

FET

Driver

dsPIC33FJ16GS504

Analog

Comp.

UART

PWM

ADC

Channel

Analog Comparator

ADC Channel

Analog Comparator

ADC

Channel

PWM

3.3V Output

5V Output

12V Input

FET

Driver

FET

Driver

FET

Driver

FET

Driver

3.3V_3

3.3V_2

3.3V_1

dsPIC33FJ16GS504

VAC

IPFC

VHV_BUS

|VAC|

FET Driver

ADC

Ch.

ADC

Ch.

PWM

Output

ADC

Ch.

PFC Stage

3.3V Multi-Phase Buck Stage

ZVT with Current Doubler Synchronous Rectifier

5V Buck Stage

Secondary Controller

Primary Controller

FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V)

Page 31

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

3.0 CPU

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the “dsPIC33F Family Reference Manual”, Section 2. “CPU”

(DS70204), which is available from the Microchip web site (www.microchip.com).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies from device to device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The sixteenth working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

There are two classes of instruction in the ds

PIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/

X04

devices: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 is shown in Figure 3-2.

3.1 Data Addressing Overview

The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific.

Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms.

The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data space mapping feature lets any instruction access program space as if it were data space.

3.2 DSP Engine Overview

The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits, right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.

Page 32

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Instruction Decode &

Control

PCH PCL

Program Counter

16-Bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stac k

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Control Signals

to Various Blocks

Literal Data

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Y RAM

Address Generator Units

Y Data Bus

X Data Bus

DSP Engine

Divide Support

PSV & Table Data Access

Control Block

Program Memory

Data Latch

Address Latch

3.3 Special MCU Features

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions.

FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE

BLOCK DIAGRAM

Page 33

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

PC22

PC0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand Registers

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address Registers

AD39 AD0AD31

DSP Accumulators

ACCA

ACCB

Program Space Visibility Page Address

OA OB SA SB

RCOUNT

REPEAT Loop Counter

DCOUNT

DO Loop Counter

DOSTART

DO Loop Start Address

IPL2 IPL1

SPLIM

Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

Core Configuration Register

Legend

CORCON

DA DC

RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL

Page 34

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

3.4 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA

(1)

bit 15 bit 8

(1)

OAB SAB

(1,4)

DA DC

R/W-0

(2)

IPL<2:0>

R/W-0

(3)

(2)

R/W-0

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit 7 bit 0

Legend:

C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’

S = Settable bit W = Writable bit -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit

1 = Accumulator A overflowed 0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit

1 = Accumulator B overflowed 0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

(1,4)

1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated

bit 9 DA: DO Loop Active bit

1 = DO loop in progress 0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry/Borrow

bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB.

Page 35

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

bit

(2)

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). 4: Clearing this bit will clear SA and SB.

Page 36

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — —USEDT

(1)

DL<2:0>

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

(2)

PSV RND IF

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set

0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit

(1)

1 = Terminate executing DO loop at end of current loop iteration 0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits

111 = 7 DO loops active

•

001 = 1 DO loop active 000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit

1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit

1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit

1 = Data space write saturation enabled 0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit

1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

(2)

1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space 0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit

1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit

1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops

Note 1: This bit will always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

Page 37

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

3.5 Arithmetic Logic Unit (ALU)

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.

Refer to the “dsPIC30F/33F Programmer ’s Reference Manual” (DS70157) for information on the SR bits

affected by each instruction.

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division.

3.5.1 MULTIPLIER

Using the high-speed, 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed sign operation in several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

and Digit Borrow bits, respectively, for

3.5.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

3.6 DSP Engine

The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (for example, ED, EDAC).

The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below:

• Fractional or integer DSP multiply (IF)

• Signed or unsigned DSP multiply (US)

• Conventional or convergent rounding (RND)

• Automatic saturation on/off for ACCA (SATA)

• Automatic saturation on/off for ACCB (SATB)

• Automatic saturation on/off for writes to data memory (SATDW)

• Accumulator Saturation mode selection (ACCSAT)

A block diagram of the DSP engine is shown in Figure 3-3.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Zero Backfill

Sign-Extend

Barrel

Shifter

40-bit Accumulator A 40-bit Accumulator B

Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-Bit

TABLE 3-1: DSP INSTRUCTIONS SUMMARY

Instruction Algebraic Operation ACC Write Back

CLR A = 0 ED A = (x – y)2 No

EDAC A = A + (x – y)2 No MAC A = A + (x * y) Yes MAC A = A + x2 No MOVSAC No change in A Yes MPY A = x * y No MPY A = x 2 No MPY.N A = – x * y No MSC A = A – x * y Yes

FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM

Yes

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

3.6.1 MULTIPLIER

The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit 2’s complement integer is -2

• For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0.

• For a 32-bit integer, the data range is

-2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit 2’s complement fraction with this implied radix point is -1.0 to (1 – 2 is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a

1.31 product that has a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte or word-sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

1-N

). For a 16-bit fraction, the Q15 data range

N-1

to 2

N-1

– 1.

-10

3.6.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation.

3.6.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input.

• In the case of addition, the Carry/B

active-high and the other input is true data (not complemented).

• In the case of subtraction, the Carry/Borrow input

is active-low and the other input is complemented.

The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits, 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT<A:B> (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate.

Six STATUS register bits support saturation and overflow:

• OA: ACCA overflowed into guard bits

• OB: ACCB overflowed into guard bits

• SA: ACCA saturated (bit 31 overflow and

saturation)

ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and

saturation)

ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB

• SAB: Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in

the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user applica-

tion to take immediate action, for example, to correct system gain.

orrow input is

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators.

The device supports three Saturation and Overflow modes:

• Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive

9.31 (0x7FFFFFFFFF) or maximally negative

9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations).

• Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set.

• Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.

3.6.3 ACCUMULATOR ‘WRITE BACK’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

• W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a

1.15 fraction.

• [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

3.6.3.1 Round Logic

The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit,

1.15 data value that is passed to the data space write

saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded.

Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator).

• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented.

• If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged.

A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined:

• If it is ‘1’, ACCxH is incremented.

• If it is ‘0’, ACCxH is not modified.

Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see

Section 3.6.3.2 “Data Space Write Saturation”). For

the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

3.6.3.2 Data Space Write Saturation

In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate

1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly:

• For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF.

• For input data less than 0xFF8000, data written to memory is forced to the maximum negative

1.15 value, 0x8000.

The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested.

If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.

3.6.4 BARREL SHIFTER

The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

NOTES:

Page 43

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program Flash Memory

0x001000

0x000FFE

(1792 instructions)

0x800000

0xF80000

Registers

0xF80017 0xF80018

DEVID (2)

0xFEFFFE 0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC33FJ06GS101/102/202

Configuration Memory Space

User Memory Space

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program Flash Memory

0x002C00

0x002BFE

(5376 instructions)

0x800000

0xF80000

Registers

0xF80017 0xF80018

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC33FJ16GS402/404/502/504

Configuration Memory Space

User Memory Space

Reserved

0xFF0002

DEVID (2)

Reserved

0xFEFFFE

0xFF0000

0xFFFFFE

0xFF0002

4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference Manual”, Section 4. “Program Memory” (DS70202), which is available

from the Microchip web site (www.microchip.com).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access to program memory from the data space during code execution.

4.1 Program Address Space

The program address memory space of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as

described in Section 4.6 “Interfacing Program and Data Memory Spaces”.

User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space.

The memory maps for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices are shown in Figure 4-1.

FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ06GS101/X02 and

dsPIC33FJ16GSX02/X04 DEVICES

Page 44

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

0816

PC Address

0x000000 0x000002

0x000004 0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

least significant word

most significant word

Instruction Width

0x000001 0x000003

0x000005 0x000007

msw

Address (lsw Address)

4.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (see Figure 4-2).

Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during the code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible.

4.1.2 INTERRUPT AND TRAP VECTORS

All dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is

programmed by the user application at 0x000000, with

the actual address for the start of code at 0x000002.

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the

interrupt vector tables is provided in Section 7.1

“Interrupt Vector Table”.

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

4.2 Data Address Space

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU has a separate, 16-bitwide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3.

All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 4.6.3 “Reading Data From Program Memory Using Program Space Visibility”).

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement up to 30 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.

4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC devices and improve data space memory usage efficiency, the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] that results in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.

MCU

All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified.

A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

4.2.3 SFR SPACE

The first 2 Kbytes of the near data space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 core and peripheral modules for controlling the operation of the device.

SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’.

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.

4.2.4 NEAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

0x0000

0x07FE

0x08FE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally Mapped into Program Memory

0x0801

0x0800

0x0900

2-Kbyte SFR Space

256 bytes

SRAM Space

0x8001

0x8000

SFR Space

X Data

Unimplemented (X)

0x087E 0x0880

0x087F 0x0881

0x08FF 0x0901

0x1FFF

0x1FFE

0x2001

0x2000

8-Kbyte Near Data Space

X Data RAM (X)

Y Data RAM (Y)

FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS101/102 DEVICES WITH 256 BYTES

OF RAM

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally Mapped into Program Memory

0x0801

0x0800

0x0C00

2-Kbyte SFR Space

1-Kbyte

SRAM Space

0x8001

0x8000

SFR Space

X Data

Unimplemented (X)

0x09FE 0x0A00

0x09FF 0x0A01

0x0BFF 0x0C01

0x1FFF

0x1FFE

0x2001

0x2000

8-Kbyte Near Data Space

X Data RAM (X)

Y Data RAM (Y)

FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1-Kbyte RAM

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

0x0000

0x07FE

0x0FFE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally Mapped into Program Memory

0x0801

0x0800

0x1000

2-Kbyte SFR Space

2-Kbyte

SRAM Space

0x8001

0x8000

SFR Space

X Data

Unimplemented (X)

0x0BFE 0x0C00

0x0BFF 0x0C01

0x0FFF 0x1001

0x1FFF

0x1FFE

0x2001

0x2000

8-Kbyte Near Data Space

X Data RAM (X)

Y Data RAM (Y)

FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH

2-Kbyte RAM

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

4.2.5 X AND Y DATA SPACES

The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms, such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT).

The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class).

The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths.

Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space.

All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable.

All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

ACCSAT IPL3 PSV RND IF 0020

— — BWM<3:0> YWM<3:0> XWM<3:0> 0000

— — — — — — — — Program Counter High Byte Register 0000

— — — — — — — — Table Page Address Pointer Register 0000

PCH 0030

TBLPAG 0032

— — — — — — — — Program Memory Visibility Page Address Pointer Register 0000

PSVPAG 0034

RCOUNT 0036 Repeat Loop Counter Register xxxx

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

WREG0 0000 Working Register 0 0000

WREG1 0002 Working Register 1 0000

WREG2 0004 Working Register 2 0000

WREG3 0006 Working Register 3 0000

WREG4 0008 Working Register 4 0000

WREG5 000A Working Register 5 0000

WREG6 000C Working Register 6 0000

WREG7 000E Working Register 7 0000

WREG8 0010 Working Register 8 0000

WREG9 0012 Working Register 9 0000

WREG10 0014 Working Register 10 0000

WREG11 0016 Working Register 11 0000

WREG12 0018 Working Register 12 0000

WREG13 001A Working Register 13 0000

WREG14 001C Working Register 14 0000

WREG15 001E Working Register 15 0800

SPLIM 0020 Stack Pointer Limit Register xxxx

ACCAL 0022 ACCAL xxxx

ACCAH 0024 ACCAH xxxx

ACCAU 0026 ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCA<39> ACCAU xxxx

ACCBL 0028 ACCBL xxxx

ACCBH 002A ACCBH xxxx

ACCBU 002C ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCB<39> ACCBU xxxx

TABLE 4-1: CPU CORE REGISTER MAP

PCL 002E Program Counter Low Word Register 0000

DCOUNT 0038 DCOUNT<15:0> xxxx

DOSTARTL 003A DOSTARTL<15:1> 0 xxxx

— — — — — — — — — —DOSTARTH<5:0>00xx

DOSTARTH 003C

DOENDL 003E DOENDL<15:1> 0 xxxx

— — — — — — — — — — DOENDH 00xx

DOENDH 0040

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000

— — — U S E DT DL <2 :0> SATA S ATB SAT D

CORCON 0044

MODCON 0046 XMODEN YMODEN

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

All

0000

Resets

All

Resets

All

Resets

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

— — Disable Interrupts Counter Register xxxx

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

— — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

— — — — — — — —

dsPIC33FJ16GS502

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

SFR

Addr

SFR

— — CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

— — CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000

SFR Name

XMODSRT 0048 XS<15:1> 0 xxxx

XMODEND 004A XE<15:1> 1 xxxx

YMODSRT 004C YS<15:1> 0 xxxx

TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)

YMODEND 004E YE<15:1> 1 xxxx

XBREV 0050 BREN XB<14:0> xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

DISICNT 0052

TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS101

File Name

CNPU1 0068

CNEN1 0060

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File

TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPI C33FJ1 6GS4 02 AND

Name

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504

File

Name

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

CNPU2 006A

CNEN2 0062

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 52

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

0040

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

File

TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF —T2IF — — —T1IFOC1IF—INT0IF0000

— —INT2IF— — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000

— — — — — —PSEMIF— — — — — — — — — 0000

Addr.

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

INTCON2 0082 ALTIVT DISI

IFS0 0084

IFS1 0086

IFS3 008A

— — — — — — — — — — — — — —U1EIF— 0000

IFS4 008C

—PWM1IF — — — — — — — — — — — — — — 0000

IFS5 008E

— — — — — — — — — — — —PWM4IF— 0000

IFS6 0090 ADCP1IF ADCP0IF

— — — — — — — — — — — — — —ADCP3IF— 0000

IFS7 0092

— — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE —T2IE — — —T1IEOC1IE—INT0IE0000

IEC0 0094

— —INT2IE— — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000

IEC1 0096

— — — — — — — — — — — — — — — — 0000

IEC2 0098

— — — — — — PSEMIE — — — — — — — — — 0000

IEC3 009A

— — — — — — — — — — — — — —U1EIE— 0000

IEC4 009C

—PWM1IE — — — — — — — — — — — — — — 0000

IEC5 009E

— — — — — — — — — — — —PWM4IE— 0000

IEC6 00A0 ADCP1IE ADCP0IE

— — — — — — — — — — — — — — ADCP3IE — 0000

IEC7 00A2

— T1IP<2:0> — OC1IP<2:0> — — — — — INT0IP<2:0> 4404

IPC0 00A4

— T2IP<2:0> — — — — — — — — — — — — 4000

IPC1 00A6

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — — — — 4440

IPC2 00A8

— — — — — — — — -— ADIP<2:0> — U1TXIP<2:0> 0044

IPC3 00AA

— CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044

IPC4 00AC

— — — — — — — — — — — — — INT1IP<2:0> 0004

IPC5 00AE

— — — — — — — — — INT2IP<2:0> — — — — 0040

IPC7 00B2

— — — — — — — — — PSEMIP<2:0> — — — —

IPC14 00C0

— — — — — — — — — U1EIP<2:0> — — — — 0400

IPC16 00C4

— — — — — PWM1IP<2:0> — — — — — — — — 0040

IPC23 00D2

— — — — — — — — — PWM4IP<2:0> — — — — 4400

IPC24 00D4

— ADCP1IP<2:0> — ADCP0IP<2:0> — — — — — — — — 0040

IPC27 00DA

— — — — — — — — — ADCP3IP<2:0> — — — — 0000

IPC28 00DC

— — — —ILR<3:0> — VECNUM<6:0> 0000

INTTREG 00E0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 53

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

0040

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

File

TABLE 4-6: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF —T2IF — — —T1IFOC1IF—INT0IF0000

— —INT2IF — — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000

Addr.

Name

INTCON2 0082 ALTIVT DISI

IFS0 0084

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

IFS1 0086

— — — — — — PSEMIF — — — — — — — — — 0000

IFS3 008A

— — — — — — — — — — — — — —U1EIF— 0000

IFS4 008C

— — — — — — — — — — — — — — 0000

IFS5 008E PWM2IF PWM1IF

— — — — — — — — — — — — — — 0000

IFS6 0090 ADCP1IF ADCP0IF

— — — — — — — — — — — — — — — ADCP2IF 0000

IFS7 0092

— — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE —T2IE — — —T1IEOC1IE—INT0IE0000

IEC0 0094

— —INT2IE— — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000

IEC1 0096

— — — — — — PSEMIE — — — — — — — — — 0000

IEC3 009A

— — — — — — — — — — — — — —U1EIE— 0000

IEC4 009C

— — — — — — — — — — — — — — 0000

IEC5 009E PWM2IE PWM1IE

— — — — — — — — — — — — — — 0000

IEC6 00A0 ADCP1IE ADCP0IE

— — — — — — — — — — — — — — — ADCP2IE 0000

IEC7 00A2

— T1IP<2:0> — OC1IP<2:0> — — — — — INT0IP<2:0> 4404

IPC0 00A4

— T2IP<2:0> — — — — — — — — — — — — 4000

IPC1 00A6

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — — — — 4440

IPC2 00A8

— — — — — — — — -— ADIP<2:0> — U1TXIP<2:0> 0044

IPC3 00AA

— CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044

IPC4 00AC

— — — — — — — — — — — — — INT1IP<2:0> 0004

IPC5 00AE

— — — — — — — — — INT2IP<2:0> — — — — 0040

IPC7 00B2

— — — — — — — — — PSEMIP<2:0> — — — —

— — — — — — — — — U1EIP<2:0> — — — — 0040

— PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400

— ADCP1IP<2:0> — ADCP0IP<2:0> — — — — — — — — 4400

— — — — — — — — — — — — — ADCP2IP<2:0> 0004

— — — —ILR<3:0> — VECNUM<6:0> 0000

IPC14 00C0

IPC16 00C4

IPC23 00D2

IPC27 00DA

IPC28 00DC

INTTREG 00E0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 54

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

0040

TABLE 4-7: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06G202 DEVICES ONLY

SFR

File

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF —T2IF — — — T1IF OC1IF IC1IF INT0IF 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr.

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

— —INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000

IFS1 0086

IFS0 0084

INTCON2 0082 ALTIVT DISI

— — — — — —PSEMIF— — — — — — — — — 0000

IFS3 008A

— — — — — — — — — — — — — —U1EIF— 0000

IFS4 008C

— — — — — — — — — — — — — — 0000

IFS5 008E PWM2IF PWM1IF

— — — — — —AC2IF — — — — — — — 0000

IFS6 0090 ADCP1IF ADCP0IF

— — — — — — — — — — — ADCP6IF — — — ADCP2IF 0000

IFS7 0092

— — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE —T2IE — — — T1IE OC1IE IC1IE INT0IE 0000

IEC0 0094

— —INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000

IEC1 0096

— — — — — — PSEMIE — — — — — — — — — 0000

IEC3 009A

— — — — — — — — — — — — — —U1EIE— 0000

IEC4 009C

— — — — — — — — — — — — — — 0000

IEC5 009E PWM2IE PWM1IE

— — — — — —AC2IE — — — — — — — 0000

IEC6 00A0 ADCP1IE ADCP0IE

— — — — — — — — — — — ADCP6IE — — — ADCP2IE 0000

IEC7 00A2

— T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444

IPC0 00A4

— T2IP<2:0> — — — — — — — — — — — — 4000

IPC1 00A6

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — — — — 4440

IPC2 00A8

— — — — — — — — -— ADIP<2:0> — U1TXIP<2:0> 0044

IPC3 00AA

— CNIP<2:0> — AC1IP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444

IPC4 00AC

— — — — — — — — — — — — — INT1IP<2:0> 0004

IPC5 00AE

— — — — — — — — — INT2IP<2:0> — — — — 0040

IPC7 00B2

— — — — — — — — — PSEMIP<2:0> — — — —

— — — — — — — — — U1EIP<2:0> — — — — 0040

— PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400

— AC2IP<2:0> — — — — — — — — — — — — 4000

— ADCP1IP<2:0> — ADCP0IP<2:0> — — — — — — — — 4400

— — — — — — — — — — — — — ADCP2IP<2:0> 0004

— — — — — — — — — — — — — ADCP6IP<2:0> 0004

— — — —ILR<3:0> — VECNUM<6:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

IPC29 00DE

IPC14 00C0

IPC16 00C4

IPC23 00D2

IPC25 00D6

IPC27 00DA

IPC28 00DC

INTTREG 00E0

Page 55

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

0040

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

File

TABLE 4-8: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

— —INT2IF — — — — — — — — INT1IF CNIF — MI2C1IF SI2C1IF 0000

Addr.

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

IFS1 0086

INTCON2 0082 ALTIVT DISI

IFS0 0084

— — — — — — PSEMIF — — — — — — — — — 0000

IFS3 008A

— — — — — — — — — — — — — —U1EIF— 0000

IFS4 008C

— — — — — — — — — — — — — — 0000

IFS5 008E PWM2IF PWM1IF

— — — — — — — — — — — — —PWM3IF0000

IFS6 0090 ADCP1IF ADCP0IF

— — — — — — — — — — — — — — ADCP3IF ADCP2IF 0000

IFS7 0092

— — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

IEC0 0094

— —INT2IE — — — — — — — — INT1IE CNIE — MI2C1IE SI2C1IE 0000

IEC1 0096

— — — — — — PSEMIE — — — — — — — — — 0000

IEC3 009A

— — — — — — — — — — — — — —U1EIE— 0000

IEC4 009C

— — — — — — — — — — — — — — 0000

IEC5 009E PWM2IE PWM1IE

— — — — — — — — — — — — —PWM3IE0000

IEC6 00A0 ADCP1IE ADCP0IE

— — — — — — — — — — — — — — ADCP3IE ADCP2IE 0000

IEC7 00A2

— T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444

IPC0 00A4

— T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — — — — 4440

IPC1 00A6

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

IPC2 00A8

— — — — — — — — -— ADIP<2:0> — U1TXIP<2:0> 0044

IPC3 00AA

— CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044

IPC4 00AC

— — — — — — — — — — — — — INT1IP<2:0> 0004

IPC5 00AE

— — — — — — — — — INT2IP<2:0> — — — — 0040

IPC7 00B2

— — — — — — — — — PSEMIP<2:0> — — — —

— — — — — — — — — U1EIP<2:0> — — — — 0040

— PWM2IP<2:0> — PWM1IP<2:0> -— — — — — — 4400

— — — — — — — — — — — — — PWM3IP<2:0> 0004

— ADCP1IP<2:0> — ADCP0IP<2:0> -— — — — — — 4400

— — — — — — — — — ADCP3IP<2:0> — ADCP2IP<2:0> 0044

— — — —ILR<3:0> — VECNUM<6:0> 0000

IPC14 00C0

IPC16 00C4

IPC23 00D2

IPC24 00D4

IPC28 00DC

IPC27 00DA

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

INTTREG 00E0

Page 56

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

0040

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

File

TABLE 4-9: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

— —INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000

Addr.

Name

INTCON2 0082 ALTIVT DISI

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

IFS0 0084

IFS1 0086

— — — — — — PSEMIF — — — — — — — — — 0000

IFS3 008A

— — — — — — — — — — — — — —U1EIF— 0000

IFS4 008C

— — — — — — — — — — — — — — 0000

IFS5 008E PWM2IF PWM1IF

— — — — AC4IF AC3IF AC2IF — — — — — PWM4IF PWM3IF 0000

IFS6 0090 ADCP1IF ADCP0IF

— — — — — — — — — — — ADCP6IF — — ADCP3IF ADCP2IF 0000

IFS7 0092

— — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

IEC0 0094

— —INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000

IEC1 0096

— — — — — —PSEMIE— — — — — — — — — 0000

IEC3 009A

— — — — — — — — — — — — — —U1EIE— 0000

IEC4 009C

— — — — — — — — — — — — — — 0000

IEC5 009E PWM2IE PWM1IE

— — — — AC4IE AC3IE AC2IE — — — — — PWM4IE PWM3IE 0000

IEC6 00A0 ADCP1IE ADCP0IE

— — — — — — — — — — —ADCP6IE — — ADCP3IE ADCP2IE 0000

IEC7 00A2

— T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444

IPC0 00A4

— T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> -— — — — 4440

IPC1 00A6

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

IPC2 00A8

— — — — -— — -— ADIP<2:0> — U1TXIP<2:0> 0044

IPC3 00AA

— CNIP<2:0> — AC1IP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444

IPC4 00AC

— — — — — — — — — — — — — INT1IP<2:0> 0004

IPC5 00AE

— — — — — — — — — INT2IP<2:0> — — — — 0040

IPC7 00B2

— — — — — — — — — PSEMIP<2:0> — — — —

— — — — — — — — — U1EIP<2:0> — — — — 0040

— PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400

— — — — — — — — — PWM4IP<2:0> — PWM3IP<2:0> 0044

— AC2IP<2:0> — — — — — — — — — — — — 4000

— — — — — — — — — AC4IP<2:0> — AC3IP<2:0> 0044

— ADCP1IP<2:0> — ADCP0IP<2:0> -— — — — — — 4400

— — — — — — — — — ADCP3IP<2:0> — ADCP2IP<2:0> 0044

— — — — — — — — — — — — — ADCP6IP<2:0> 0004

— — — —ILR<3:0> — VECNUM<6:0> 0000

IPC14 00C0

IPC16 00C4

IPC23 00D2

IPC24 00D4

IPC26 00D8

IPC25 00D6

IPC28 00DC

IPC27 00DA

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

IPC29 00DE

INTTREG 00E0

Page 57

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

0040

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

File

TABLE 4-10: INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000

— — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000

— —INT2IF — — — — — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000

Addr.

Name

INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR

INTCON2 0082 ALTIVT DISI

IFS0 0084

IFS1 0086

— — — — — — — — — — — — — — 0000

— — — — AC4IF AC3IF AC2IF — — — — — PWM4IF PWM3IF 0000

— — — — — —PSEMIF— — — — — — — — — 0000

— — — — — — — — — — — — — —U1EIF— 0000

IFS3 008A

IFS4 008C

IFS5 008E PWM2IF PWM1IF

— — — — — — — — — — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF 0000

— — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000

— —INT2IE — — — — — — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE 0000

IFS7 0092

IEC0 0094

IFS6 0090 ADCP1IF ADCP0IF

IEC1 0096

— — — — — — — — — — — — — — 0000

— — — — AC4IE AC3IE AC2IE — — — — — PWM4IE PWM3IE 0000

— — — — — — PSEMIE — — — — — — — — — 0000

— — — — — — — — — — — — — —U1EIE— 0000

IEC3 009A

IEC4 009C

— — — — — — — — — — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE 0000

— T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444

— T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — — — — 4440

— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444

— — — — — — — — -— ADIP<2:0> — U1TXIP<2:0> 0044

— CNIP<2:0> — AC1IP<2:0> — MI2C1IP<2:0> — SI2C1IP<2:0> 4444

— — — — — — — — — — — — — INT1IP<2:0> 0004

— — — — — — — — — INT2IP<2:0> — — — — 0040

— — — — — — — — — PSEMIP<2:0> — — — —

— — — — — — — — — U1EIP<2:0> — — — — 0040

— PWM2IP<2:0> — PWM1IP<2:0> — — — — — — — — 4400

— — — — — — — — — PWM4IP<2:0> — PWM3IP<2:0> 0044

— AC2IP<2:0> — — — — — — — — — — — — 4000

— — — — — — — — — AC4IP<2:0> — AC3IP<2:0> 0440

— ADCP1IP<2:0> — ADCP0IP<2:0> — — — — — — — — 4400

— ADCP5IP<2:0> — ADCP4IP<2:0> — ADCP3IP<2:0> — ADCP2IP<2:0> 4444

— — — — — — — — — — — — — ADCP6IP<2:0> 0004

— — — —ILR<3:0> — VECNUM<6:0> 0000

IEC7 00A2

IEC5 009E PWM2IE PWM1IE

IPC0 00A4

IEC6 00A0 ADCP1IE ADCP0IE

IPC2 00A8

IPC1 00A6

IPC3 00AA

IPC4 00AC

IPC14 00C0

IPC16 00C4

IPC23 00D2

IPC24 00D4

IPC26 00D8

IPC5 00AE

IPC7 00B2

IPC25 00D6

IPC28 00DC

IPC27 00DA

IPC29 00DE

INTTREG 00E0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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All

Resets

All

Resets

All

Resets

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

Timer2 Register xxxx

Period Register 1 FFFF

0102

Period Register 2 FFFF

—TSIDL— — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000

TON

0104

—TSIDL— — — — — — TGATE TCKPS<1:0> — —TCS— 0000

TON

0110

0106

010C

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Period Register 1 FFFF

—TSIDL— — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000

TON

0102

Addr

0104

Timer3 Register xxxx

Timer2 Register xxxx

0106

Period Register 2 FFFF

Period Register 3 FFFF

Timer3 Holding Register (for 32-bit timer operations only) xxxx

—TSIDL— — — — — — TGATE TCKPS<1:0> T32 —TCS— 0000

—TSIDL— — — — — — TGATE TCKPS<1:0> — —TCS— 0000

TON

0110

0108

010A

010C

010E

0112

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

— —ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

Addr

TABLE 4-13: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ06GS202

SFR

Name

IC1BUF 0140 Input Capture 1 Register xxxx

IC1CON 0142

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Name

PR1

T1CON

TABLE 4-11: TIMER REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02

TMR1 0100 Timer1 Register xxxx

TMR2

PR2

T2CON

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Name

PR1

T1CON

TABLE 4-12: TIMER REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04

TMR1 0100 Timer1 Register xxxx

TMR2

PR2

PR3

TMR3HLD

TMR3

T2CON

T3CON

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 59

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

All

Resets

All

Resets

All

Resets

— — — 0000

— PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN — SYNCSRC<1:0> SEVTPS<3:0> 0000

— —ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

TABLE 4-14: INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04

SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Name

IC1BUF 0140 Input Capture 1 Register xxxx

— —ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

IC2BUF 0144 Input Capture 2 Register xxxx

IC2CON 0146

IC1CON 0142

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Name

TABLE 4-15: OUTPUT COMPARE REGISTER MAP dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02

OC1RS 0180 Output Compare 1 Secondary Register xxxx

OC1R 0182 Output Compare 1 Register xxxx

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000

OC1CON 0184

OC1RS 0180 Output Compare 1 Secondary Register xxxx

OC1R 0182 Output Compare 1 Register xxxx

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000

OC1CON 0184

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Name

TABLE 4-16: OUTPUT COMPARE REGISTER MAP dsPIC33FJ16GSX02 AND dsPIC33FJ06GSX04

OC2RS 0186 Output Compare 2 Secondary Register xxxx

OC2R 0188 Output Compare 2 Register xxxxx

— —OCSIDL— — — — — — — — OCFLT OCTSEL OCM<2:0> 0000

OC2CON 018A

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-17: HIGH-SPEED PWM REGISTER MAP

File Name

— — — — — — — — — — — — —PCLKDIV<2:0>0000

Offset

PTPER 0404 PTPER<15:0> FFF8

PTCON 0400 PTEN

SEVTCMP 0406 SEVTCMP<15:3>

PTCON2 0402

MDC 040A MDC<15:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 60

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

— — — 0000

— — — CAM XPRES IUE 0000

Resets

— — — 0000

— — — CAM XPRES IUE 0000

— — — —DTM—TRGSTRT<5:0>0000

— — DTR1<13:0> 0000

PHASE1 0428 PHASE1<15:0> 0000

— — ALTDTR1<13:0> 0000

ALTDTR1 042C

SDC1 042E SDC1<15:0> 0000

SPHASE1 0430 SPHASE1<15:0> 0000

DTR1 042A

TRIG1 0432 TRGCMP<15:3>

STRIG1 0436 STRGCMP<15:3>

TRGCON1 0434 TRGDIV<3:0>

PWMCAP1 0438 PWMCAP1<15:3>

LEBCON1 043A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3>

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

T ABLE 4-19 : HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33FJ06GS102/202 AND dsPIC33FJ16GSX02/X04 DEVICES ONLY

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

Offset

IOCON2 0442 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

File Name

FCLCON2 0444 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0>

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

Offset

IOCON1 0422 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON1 0424 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

File Name

TABLE 4-18: HIGH-SPEED PWM GENERATOR 1 REGISTER MAP

PWMCON1 0420 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0>

PDC1 0426 PDC1<15:0> 0000

PDC2 0446 PDC2<15:0> 0000

PHASE2 0448 PHASE2<15:0> 0000

— — DTR2<13:0> 0000

DTR2 044A

— — ALTDTR2<13:0> 0000

ALTDTR2 044C

SDC2 044E SDC2<15:0> 0000

SPHASE2 0450 SPHASE2<15:0> 0000

— — — —DTM—TRGSTRT<5:0>0000

TRIG2 0452 TRGCMP<15:3>

STRIG2 0456 STRGCMP<15:3>

TRGCON2 0454 TRGDIV<3:0>

PWMCAP2 0458 PWMCAP2<15:3>

LEBCON2 045A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3>

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 61

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

— — — 0000

— — — CAM XPRES IUE 0000

All

Resets

— — — 0000

— — — CAM XPRES IUE 0000

— — — —DTM—TRGSTRT<5:0>0000

— — DTR3<13:0> 0000

PHASE3 0468 PHASE3<15:0> 0000

— — ALTDTR3<13:0> 0000

DTR3 046C

SPHASE3 0470 SPHASE3<15:0> 0000

TRIG3 0472 TRGCMP<15:3>

STRIG3 0476 STRGCMP<15:3>

TRGCON3 0474 TRGDIV<3:0>

PWMCAP3 0478 PWMCAP3<15:3>

LEBCON3 047A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3>

ALTDTR3 046C

SDC3 046E SDC3<15:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

Offset

IOCON4 0482 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

File Name

TABLE 4-21: HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ16GS50X DEVICES ONLY

FCLCON4 0484 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0>

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

Offset

IOCON3 0462 PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

FCLCON3 0464 IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

File Name

TABLE 4-20: HIGH-SPEED PWM GENERATOR 3 REGISTER MAP FOR dsPIC33FJ16GSX02/X04 DEVICES ONLY

PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0>

PDC3 0466 PDC3<15:0> 0000

PDC4 0486 PDC4<15:0> 0000

PHASE4 0488 PHASE4<15:0> 0000

— — DTR4<13:0> 0000

DTR4 048A

— — ALTDTR4<13:0> 0000

ALTDTR4 048A

SDC4 048E SDC4<15:0> 0000

SPHASE4 0490 SPHASE4<15:0> 0000

— — — —DTM—TRGSTRT<5:0>0000

TRIG4 0492 TRGCMP<15:3>

STRIG4 0496 STRGCMP<15:3>

TRGCON4 0494 TRGDIV<3:0>

PWMCAP4 0498 PWMCAP4<15:3>

LEBCON4 049A PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<9:3>

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 62

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

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Resets

All

Resets

All

Resets

UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110

— SPI SIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000

SPI1STAT 0240 SPIEN

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000

SPI1CON1 0242

— — — — — — — — — — — FRMDLY — 0000

SPI1CON2 0244 FRMEN SPIFSD FRMPOL

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— UTXBRK UTXE

— — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000

— I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

— — — — — — — UART Transmit Register xxxx

— — — — — — — — Receive Register 0000

— — — — — — — — Transmit Register 00FF

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

TABLE 4-22: I2C1 REGISTER MAP

— — — — — — — Baud Rate Generator Register 0000

I2C1TRN 0202

I2C1BRG 0204

I2C1RCV 0200

I2C1CON 0206 I2CEN

— — — — — — Address Register 0000

— — — — — — AMSK<9:0> 0000

I2C1MSK 020C

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

I2C1ADD 020A

I2C1STAT 0208 ACKSTAT TRSTAT

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-23: UART1 REGISTER MAP

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000

U1STA 0222 UTXISEL1 UTXINV UTXISEL0

— — — — — — — UART Receive Register 0000

U1TXREG 0224

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

U1RXREG 0226

U1BRG 0228 Baud Rate Generator Prescaler 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-24: SPI1 REGISTER MAP

Page 63

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

— 0000

— — — — — — — — 0000

Resets

— 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-25: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY

— ADSIDL SLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS<2:0> 0003

ADCON 0300 ADON

— — — — — — — —PCFG7PCFG6 — — PCFG3 PCFG2 PCFG1 PCFG0 0000

ADPCFG 0302

— — — — — — — — — — — — P3RDY — P1RDY P0RDY 0000

ADSTAT 0306

ADBASE 0308 ADBASE<15:1>

ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0>

ADCBUF0 0320 ADC Data Buffer 0 xxxx

ADCBUF1 0322 ADC Data Buffer 1 xxxx

ADCBUF2 0324 ADC Data Buffer 2 xxxx

ADCBUF3 0326 ADC Data Buffer 3 xxxx

ADCBUF6 032C ADC Data Buffer 6 xxxx

ADCBUF7 032E ADC Data Buffer 7 xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-26: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

SFR Name

—ADSIDLSLOWCLK—GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS<2:0> 0003

— — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

— — — — — — — — — — — — — P2RDY P1RDY P0RDY 0000

Addr

ADSTAT 0306

ADPCFG 0302

ADCON 0300 ADON

— — — — — — — — IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000

ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADCPC1 030C

ADBASE 0308 ADBASE<15:1>

ADCBUF0 0320 ADC Data Buffer 0 xxxx

ADCBUF1 0322 ADC Data Buffer 1 xxxx

ADCBUF2 0324 ADC Data Buffer 2 xxxx

ADCBUF3 0326 ADC Data Buffer 3 xxxx

ADCBUF4 0328 ADC Data Buffer 4 xxxx

ADCBUF5 032A ADC Data Buffer 5 xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 64

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

— 0000

All

Resets

— 0000

—ADSIDLSLOWCLK—GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS<2:0> 0003

— — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

ADCON 0300 ADON

— — — — — — — — — — — — P3RDY P2RDY P1RDY P0RDY 0000

ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000

ADCBUF0 0320 ADC Data Buffer 0 xxxx

ADCBUF1 0322 ADC Data Buffer 1 xxxx

ADCBUF2 0324 ADC Data Buffer 2 xxxx

ADCBUF3 0326 ADC Data Buffer 3 xxxx

ADCBUF4 0328 ADC Data Buffer 4 xxxx

ADCBUF5 032A ADC Data Buffer 5 xxxx

ADCBUF6 032C ADC Data Buffer 6 xxxx

ADCBUF7 032E ADC Data Buffer 7 xxxx

ADPCFG 0302

ADBASE 0308 ADBASE<15:1>

ADSTAT 0306

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

SFR Name

TABLE 4-27: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY

—ADSIDLSLOWCLK—GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS<2:0> 0003

— — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

— — — — — — — — — P6RDY — — — P2RDY P1RDY P0RDY 0000

Addr

ADSTAT 0306

ADPCFG 0302

ADCON 0300 ADON

— — — — — — — — IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000

— — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> 0000

ADCPC3 0310

ADCBUF0 0320 ADC Data Buffer 0 xxxx

ADCBUF1 0322 ADC Data Buffer 1 xxxx

ADCBUF2 0324 ADC Data Buffer 2 xxxx

ADCBUF3 0326 ADC Data Buffer 3 xxxx

ADCBUF4 0328 ADC Data Buffer 4 xxxx

ADCBUF5 032A ADC Data Buffer 5 xxxx

ADBASE 0308 ADBASE<15:1>

ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADCPC1 030C

ADCBUF12 0338 ADC Data Buffer 12 xxxx

ADCBUF13 033A ADC Data Buffer13 xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-28: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY

Page 65

dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

— 0000

— ADSIDL SLOWCLK —GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS<2:0> 0003

— — — — — — — — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-29: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY

— — — — — — — — — P6RDY — — P3RDY P2RDY P1RDY P0RDY 0000

ADPCFG 0302

ADBASE 0308 ADBASE<15:1>

ADSTAT 0306

ADCON 0300 ADON

ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000

— — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> 0000

ADCPC3 0310

ADCBUF0 0320 ADC Data Buffer 0 xxxx

ADCBUF1 0322 ADC Data Buffer 1 xxxx

ADCBUF2 0324 ADC Data Buffer 2 xxxx

ADCBUF3 0326 ADC Data Buffer 3 xxxx

ADCBUF4 0328 ADC Data Buffer 4 xxxx

ADCBUF5 032A ADC Data Buffer 5 xxxx

ADCBUF6 032C ADC Data Buffer 6 xxxx

ADCBUF7 032E ADC Data Buffer 7 xxxx

ADCBUF12 0338 ADC Data Buffer 12 xxxx

ADCBUF13 033A ADC Data Buffer 13 xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Page 66

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

— 0000

—ADSIDLSLOWCLK—GSWTRG— FORM EIE ORDER SEQSAMP ASYNCSAMP — ADCS<2:0> 0003

— — — — PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

SFR Name

TABLE 4-30: HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY

— — — — — — — — — P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY 0000

Addr

ADBASE 0308 ADBASE<15:1>

ADPCFG 0302

ADCON 0300 ADON

ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 TRGSRC0<4:0> 0000

ADSTAT 0306

ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0> IRQEN2 PEND2 SWTRG2 TRGSRC2<4:0> 0000

ADCPC2 030E IRQEN5 PEND5 SWTRG5 TRGSRC5<4:0> IRQEN4 PEND4 SWTRG4 TRGSRC4<4:0> 0000

— — — — — — — — IRQEN6 PEND6 SWTRG6 TRGSRC6<4:0> 0000

ADCPC3 0310

ADCBUF0 0320 ADC Data Buffer 0 xxxx

ADCBUF1 0322 ADC Data Buffer 1 xxxx

ADCBUF2 0324 ADC Data Buffer 2 xxxx

ADCBUF3 0326 ADC Data Buffer 3 xxxx

ADCBUF4 0328 ADC Data Buffer 4 xxxx

ADCBUF5 032A ADC Data Buffer 5 xxxx

ADCBUF6 032C ADC Data Buffer 6 xxxx

ADCBUF7 032E ADC Data Buffer 7 xxxx

ADCBUF8 0330 ADC Data Buffer 8 xxxx

ADCBUF9 0332 ADC Data Buffer 9 xxxx

ADCBUF10 0334 ADC Data Buffer 10 xxxx

ADCBUF11 0336 ADC Data Buffer 11 xxxx

ADCBUF12 0338 ADC Data Buffer 12 xxxx

ADCBUF13 033A ADC Data Buffer 13 xxxx

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

Resets

All

Resets

— CMPSIDL — — — — DACOE INSEL<1:0> EXTREF — CMPSTAT — CMPPOL RANGE 0000

— — — — — —CMREF<9:0>0000

File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 4-31: ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY

CMPCON1 0540 CMPON

CMPCON2 0544 CMPON

CMPDAC1 0542

CMPDAC2 0546

TABLE 4-32: ANALOG COMPARATOR CONTROL REGISTER MAP dsPIC33FJ16GS502/504 DEVICES ONLY

— CMPSIDL — — — — DACOE INSEL<1:0> EXTREF — CMPSTAT — CMPPOL RANGE 0000

— — - — — —CMREF<9:0>0000

— — — — — —CMREF<9:0>0000

File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CMPCON1 0540 CMPON

CMPCON2 0544 CMPON

CMPCON3 0548 CMPON

CMPDAC1 0542

CMPDAC2 0546

CMPCON4 054C CMPON

CMPDAC3 054A

CMPDAC4 054E

Page 68

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All

Resets

All

Resets

— —INT1R<5:0>— — — — — — — — 3F00

— — — — — — — — — —INT2R<5:0>003F

— —T1CKR<5:0>— — — — — — — — 0000

— —T3CKR<5:0>— —T2CKR<5:0>3F3F

— — IC2R<5:0> — — IC1R<5:0> 3F3F

— — — — — — — — — —OCFAR<5:0>3F3F

— — U1CTSR<5:0> — —U1RXR<5:0>003F

— —SCK1R<5:0>— —SDI1R<5:0>3F3F

— — — — — — — — — —SS1R<5:0>0000

— —FLT1R<5:0>— — — — — — — — 3F00

— —FLT3R<5:0>— —FLT2R<5:0>3F3F

— —FLT5R<5:0>— —FLT4R<5:0>3F3F

— —FLT7R<5:0>— —FLT6R<5:0>3F3F

— — SYNCI1R<5:0> — —FLT8R<5:0>3F3F

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-33: PERIPHERAL PIN SELECT INPUT REGISTER MAP

RPINR2 0684

RPINR7 068E

RPINR11 0696

RPINR18 06A4

RPINR20 06A8

RPINR21 06AA

RPINR29 06BA

RPINR1 0682

RPINR0 0680

RPINR3 0686

RPINR31 06BE

RPINR30 06BC

— — — — — — — — — — SYNCI2R<5:0> 3F3F

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RPINR32 06C0

RPINR33 06C2

RPINR34 06C4

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File

TABLE 4-34: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS101

— — RP3R<5:0> — — RP2R<5:0> 0000

— — RP5R<5:0> — — RP4R<5:0> 0000

— — RP7R<5:0> — — RP6R<5:0> 0000

— — RP33<5:0> — — RP32<5:0> 0000

— — RP35<5:0> — — RP34<5:0> 0000

Name

RPOR0 06D0 — — RP1R<5:0> — — RP0R<5:0> 0000

RPOR1 06D2

RPOR2 06D4

RPOR3 06D6

RPOR16 06F0

RPOR17 06F2

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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All

Resets

All

Resets

— — RP3R<5:0> — —RP2R<5:0>0000

— — RP5R<5:0> — —RP4R<5:0>0000

— — RP7R<5:0> — —RP6R<5:0>0000

— — RP9R<5:0> — —RP8R<5:0>0000

— —RP11R<5:0> — — RP10R<5:0> 0000

— —RP13R<5:0> — — RP12R<5:0> 0000

— —RP15R<5:0> — — RP14R<5:0> 0000

— — RP33<5:0> — — RP32<5:0> 0000

— — RP35<5:0> — — RP34<5:0> 0000

— — RP3R<5:0> — —RP2R<5:0>0000

— — RP5R<5:0> — —RP4R<5:0>0000

— — RP7R<5:0> — —RP6R<5:0>0000

— — RP9R<5:0> — —RP8R<5:0>0000

— —RP11R<5:0>— —RP10R<5:0>0000

— —RP13R<5:0> — —RP12R<5:0>0000

— —RP15R<5:0> — —RP14R<5:0>0000

— —RP17R<5:0> — —RP16R<5:0>0000

— —RP19R<5:0> — —RP18R<5:0>0000

— —RP21R<5:0> — —RP20R<5:0>0000

— —RP23R<5:0> — —RP22R<5:0>0000

— —RP25R<5:0> — —RP24R<5:0>0000

— —RP27R<5:0> — —RP26R<5:0>0000

— —RP29R<5:0> — —RP28R<5:0>0000

— — RP33<5:0> — — RP32<5:0> 0000

— — RP35<5:0> — — RP34<5:0> 0000

AND dsPIC33FJ16GS502

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RPOR1 06D2

RPOR0 06D0 — — RP1R<5:0> — — RP0R<5:0> 0000

RPOR2 06D4

RPOR3 06D6

RPOR4 06D8

RPOR5 06DA

RPOR6 06DC

RPOR7 06DE

RPOR16 06F0

RPOR17 06F2

TABLE 4-35: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-36: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RPOR1 06D2

RPOR2 06D4

RPOR3 06D6

RPOR4 06D8

RPOR5 06DA

RPOR6 06DC

RPOR7 06DE

RPOR8 06E0

RPOR9 06E2

RPOR10 06E4

RPOR11 06E6

RPOR12 06E8

RPOR13 06EA

RPOR14 06EC

RPOR16 06F0

RPOR17 06F2

RPOR0 06D0 — — RP1R<5:0> — —RP0R<5:0>0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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All

Resets

All

Resets

All

Resets

All

Resets

— — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F

— — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx

— — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-37: PORTA REGISTER MAP

TRISA 02C0

— — — — — — — — — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000

PORTA 02C2

LATA 02C4

ODCA 02C6

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-38: PORTB REGISTER MAP FOR dsPIC33FJ06GS101

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

— — — — — — — — TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 00FF

TRISB 02C8

— — — — — — — — RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx

PORTB 02CA

— — — — — — — — LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000

LATB 02CC

— — — — — — — — ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000

ODCB 02CE

— — TRISC13 TRISC12 TRISC11 TRISC10 TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 3FFF

— — RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx

— — LATC 13 L ATC 12 L ATC 11 L ATC 10 LAT C9 L ATC 8 LAT C7 L ATC6 L ATC 5 LATC 4 L ATC 3 L ATC 2 L ATC 1 LA TC0 0000

— — ODCC13 ODCC12 ODCC11 ODCC10 ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000

PORTC 02D2

LATC 02D4

ODCC 02D6

TABLE 4-40: PORTC REGISTER MAP FOR dsPIC33FJ16GS404 AND dsPIC33FJ16GS504

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TRISC 02D0

dsPIC33FJ16GS502 AND dsPIC33FJ16GS504

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF

PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx

LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-39: PORTB REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402, dsPIC33FJ16GS404,

ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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dsPIC33FJ06GS101/X02 an d dsPIC33FJ16GSX02/X04

All

(1)

(2)

Resets

TUN<5:0> 0000

(1)

All

Resets

All

Resets

All

Resets

— — APSTSCLR<2:0> ASRCSEL FRCSEL — — — — — — 0000

— — — — — —ERASE— —NVMOP<3:0>0000

— — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx

— ROSIDL ROSEL RODIV<3:0> — — — — — — — — 0000

OSCCON 0742 —COSC<2:0>— NOSC<2:0> CLKLOCK IOLOCK LOCK —CF — —OSWEN0300

CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040

— — — — — — — PLLDIV<8:0> 0030

PLLFBD 0746

REFOCON 074E ROON

— — — T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD — — ADCMD 0000

— — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000

— — — — —CMPMD— — — — — — — — — — 0000

— — — — — — — — — — — —REFOMD— — — 0000

PMD3 0774

PMD4 0776

— — — —PWM4MD — —PWM1MD— — — — — — — — 0000

PMD6 077A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-44: PMD REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

2: The OSCCON register Reset values are dependent on the FOSC Configuration bits and on type of Reset.

SFR

ACLKCON 0750 ENAPLL APLLCK SELACLK

OSCTUN 0748

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: The RCON register Reset values are dependent on type of Reset.

TABLE 4-42: NVM REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000

NVMCON 0760 WR WREN WRERR

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.

TABLE 4-43: PMD REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY

Name

PMD2 0772

PMD1 0770

— — — T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD — — ADCMD 0000

— — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000

— — — — —CMPMD— — — — — — — — — — 0000

— — — — — — — — — — — —REFOMD— — — 0000

PMD3 0774

PMD4 0776

— — — — — — PWM2MD PWM1MD — — — — — — — — 0000

PMD6 077A

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

PMD2 0772

PMD1 0770

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR Name

TABLE 4-41: SYSTEM CONTROL REGISTER MAP

RCON 0740 TRAPR IOPUWR

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

All

Resets

All

Resets

All

Resets

— — — T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD — — ADCMD 0000

— — — — — — —IC1MD— — — — — — —OC1MD0000

— — — — —CMPMD— — — — — — — — — — 0000

— — — — — — — — — — — —REFOMD— — — 0000

— — — — — — PWM2MD PWM1MD — — — — — — — — 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

TABLE 4-45: PMD REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY

— — — — — — CMP2MD CMP1MD — — — — — — — — 0000

Addr

Name

PMD2 0772

PMD3 0774

PMD1 0770

PMD4 0776

PMD6 077A

PMD7 077C

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-46: PMD REGISTER MAP FOR dsPIC33FJ16GS402 AND dsPIC33FJ16GS404 DEVICES ONLY

— — T3MD T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD — — ADCMD 0000

— — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000

— — — — — — — — — — — — — — — — 0000

— — — — — — — — — — — —REFOMD— — — 0000

— — — — — PWM3MD PWM2MD PWM1MD — — — — — — — — 0000

PMD4 0776

PMD6 077A

— — — — — — — — — — — — — — — — 0000

PMD7 077C

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-47: PMD REGISTER MAP FOR dsPIC33FJ16GS502 AND dsPIC33FJ16GS504 DEVICES ONLY

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

PMD2 0772

PMD3 0774

PMD1 0770

— — T3MD T2MD T1MD —PWMMD—I2C1MD—U1MD — SPI1MD — — ADCMD 0000

— — — — — —IC2MDIC1MD— — — — — —OC2MDOC1MD0000

— — — — —CMPMD— — — — — — — — — — 0000

— — — — — — — — — — — —REFOMD— — — 0000

— — — — PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000

PMD4 0776

PMD6 077A

— — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — — — 0000

PMD7 077C

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SFR

Addr

SFR

Name

PMD2 0772

PMD3 0774

PMD1 0770

Page 73

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

PC<15:0>

000000000

015

W15 (before CALL)

W15 (after CALL)

Stack Grows Toward

Higher Address

0x0000

PC<22:16>

POP : [--W15] PUSH : [W15++]

4.2.6 SOFTWARE STACK

In addition to its use as a working register, the W15 register in the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear.

Note: A PC push during exception processing

concatenates the SRL register to the MSb of the PC prior to the push.

The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1000 in RAM, initialize the SPLIM with the value 0x0FFE.

Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space.

A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.

FIGURE 4-6: CALL STACK FRAME

4.3 Instruction Addressing Modes

The addressing modes shown in Table 4-48 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types.

4.3.1 FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space.

4.3.2 MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-Bit or 10-Bit Literal

Note: Not all instructions support all the

addressing modes given above. Individual instructions can support different subsets of these addressing modes.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct The address of the file register is specified explicitly.

decremented) by a constant value.

to form the EA.

The sum of Wn and Wb forms the EA.

4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS

Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode.

Note: For the MOV instructions, the addressing

mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (register offset) field is shared by both source and destination (but typically only used by one).

In summary, the following addressing modes are supported by move and accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-Bit Literal

• 16-Bit Literal

Note: Not all instructions support all the

addressing modes given above. Individual instructions may support different subsets of these addressing modes.

4.3.4 MAC INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively

manipulate the data pointers through register indirect

tables.

The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11.

Note: Register Indirect with Register Offset

Addressing mode is available only for W9 (in X space) and W11 (in Y space).

In summary, the following addressing modes are supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

4.3.5 OTHER INSTRUCTIONS

Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands.

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

0x1100

0x1163

Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words

Byte

Address

MOV #0x1100, W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address MOV #0x8001, W0 MOV W0, MODCON ;enable W1, X AGU for modulo

MOV #0x0000, W0 ;W0 holds buffer fill value

MOV #0x1110, W1 ;point W1 to buffer

DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value

4.4 Modulo Addressing

Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms.

Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively.

In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer.

The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries).

4.4.1 START AND END ADDRESS

The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1).

Note: Y space Modulo Addressing EA

calculations assume word-sized data (LSb of every EA is always clear).

The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes).

4.4.2 W ADDRESS REGISTER SELECTION

The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that will operate with Modulo Addressing:

• If XWM = 15, X RAGU and X WAGU Modulo

Addressing is disabled.

• If YWM = 15, Y AGU Modulo Addressing is

disabled.

The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON<3:0> (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON<15>.

The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON<7:4>. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>.

FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE

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4.4.3 MODULO ADDRESSING APPLICABILITY

Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to:

• The upper boundary addresses for incrementing

buffers

• The lower boundary addresses for decrementing

buffers

It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly.

Note: The modulo corrected effective address is

written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7 + W2]) is used, Modulo Addressing correction is performed but the contents of the register remain unchanged.

4.5 Bit-Reversed Addressing

Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.

The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier.

4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-Reversed Addressing mode is enabled in any of these situations:

• BWM bits (W register selection) in the MODCON

• The BREN bit is set in the XBREV register

• The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment

If the length of a bit-reversed buffer is M = 2 the last ‘N’ bits of the data buffer start address must be zeros.

XB<14:0> is the Bit-Reversed Address modifier, or ‘pivot point,’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.

Note: All bit-reversed EA calculations assume

word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses.

When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear).

Note: Modulo Addressing and Bit-Reversed

Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU; Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU.

If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the Bit-Reversed Pointer.

bytes,

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b3 b2 b1 0

b2 b3 b4

Bit Locations Swapped Left-to-Right Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-Word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

Sequential Address

Pivot Point

FIGU R E 4-8: BIT-REVERSED ADDRESS EXAMPLE

TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address

A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal

0000 0 0000 0

0001 1 1000 8

0010 2 0100 4

0011 3 1100 12

0100 4 0010 2

0101 5 1010 10

0110 6 0110 6

0111 7 1110 14

1000 8 0001 1

1001 9 1001 9

1010 10 0101 5

1011 11 1101 13

1100 12 0011 3

1101 13 1011 11

1110 14 0111 7

1111 15 1111 15

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4.6 Interfacing Program and Data

Memory Spaces

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be

present in the program space. To use this data success-

fully, it must be accessed in a way that preserves the alignment of information in both spaces.

Aside from normal execution, the dsPIC33FJ06GS101/ X02 and dsPIC33FJ16GSX02/X04 architecture provides two methods by which program space can be accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the least significant word of the program word.

4.6.1 ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used.

For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1).

For remapping operations, the 8-bit Program Space Visibility Register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area.

Table 4-50 and Figure 4-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, and D<15:0> refers to a data space word.

TABLE 4-50: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Type

Instruction Access (Code Execution)

TBLRD/TBLWT

(Byte/Word Read/Write)

Program Space Visibility (Block Remap/Read)

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

Access

Space

User 0 PC<22:1> 0

User TBLPAG<7:0> Data EA<15:0>

Configuration TBLPAG<7:0> Data EA<15:0>

User 0 PSVPAG<7:0> Data EA<14:0>

<23> <22:16> <15> <14:1> <0>

0xxx xxxx xxxx xxxx xxxx xxxx

1xxx xxxx xxxx xxxx xxxx xxxx

0 xxxx xxxx xxx xxxx xxxx xxxx

Program Space Address

0xx xxxx xxxx xxxx xxxx xxx0

(1)

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0Program Counter

23 bits

PSVPAG

8 bits

15 bits

Program Counter

(1)

Select

TBLPAG

8 bits

16 bits

Byte Select

1/0

User/Configuration

Table Operations

(2)

Program Space Visibility

(1)

Space Select

24 bits

23 bits

(Remapping)

1/0

Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word

alignment of data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

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081623

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.W

TBLRDL.B

(Wn<0> = 1)

TBLRDL.B

(Wn<0> = 0)

23 15 0

TBLPAG

0x000000

0x800000

0x020000

0x030000

Program Space

The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.

4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.

The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte.

Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations.

• TBLRDL (Table Read Low):

- In Word mode, this instruction maps the lower word of the program space location

(P<15:0>) to a data address (D<15:0>).

- In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’.

• TBLRDH (Table Read High):

- In Word mode, this instruction maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’.

- In Byte mode, this instruction maps the upper or lower byte of the program word to D<7:0> of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1).

Similarly, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are

explained in Section 5.0 “Flash Program Memory”.

For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space.

FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

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23 15 0

PSVPAG

Data Space

Program Space

0x0000

0x8000

0xFFFF

0x000000

0x800000

0x010000

0x018000

When CORCON<2> = 1 and EA<15> = 1:

The data in the page designated by PSVPAG is mapped into the upper half of the data memory space...

Data EA<14:0>

...while the lower 15 bits of the EA specify an exact address within

the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.

PSV Area

4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H).

Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses.

Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required.

Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 4-11), only the lower 16 bits of the

24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed.

Note: PSV access is temporarily disabled during

table reads/writes.

For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time.

For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an interrupt

• Execution upon re-entering the loop after an interrupt is serviced

Any other iteration of the REPEAT loop will allow the instruction using PSV to access data, to execute in a single cycle.

FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION

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NOTES:

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Program Counter

24 bits

Program Counter

TBLPAG Reg

8 bits

Working Reg EA

16 bits

Byte

24-bit EA

1/0

Select

Using Table Instruction

Using

User/Configuration Space Sel ect

5.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference Manual”, Section 5. “Flash Programming” (DS70191), which is

available from the Microchip web site (www.microchip.com).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V

Flash memory can be programmed in two ways:

• In-Circuit Serial Programming™ (ICSP™) programming capability

• Run-Time Self-Programming (RTSP)

ICSP allows a dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx, and three other lines for power (V This allows customers to manufacture boards with unprogrammed devices and then program the digital

DD range.

DD), ground (VSS) and Master Clear (MCLR).

signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.

RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data, either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time, or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time.

5.1 Table Instructions and Flash

Programming

Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits<7:0> of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1.

The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

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7.37 MHz FRC Accuracy()% FRC Tuning()%××

--------------------------------------------------------------------------------------------------------------------------

11064 Cycles

7.37 MHz 10.05+()1 0.00375–()××

---------------------------------------------------------------------------------------------- 1 . 4 35 ms==

11064 Cycles

7.37 MHz 10.05–()1 0.00375–()××

----------------------------------------------------------------------------------------------1.586ms==

5.2 RTSP Operation

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.

The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary.

The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions.

All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row.

5.3 Programming Operations

A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished.

The programming time depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tuning register (see Register 8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 24-12).

EQUATION 5-1: PROGRAMMING TIME

For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN<5:0> bits (see Register 8-4) are set to ‘b111111, the Minimum Row Write Time is:

and, the Maximum Row Write Time is:

Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished.

5.4 Control Registers

Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and

0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details.

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REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER

(1)

R/SO-0

WR WREN WRERR — — — — —

bit 15 bit 8

R/W-0

(1)

R/W-0

(1)

U-0 U-0 U-0 U-0 U-0

U-0 R/W-0

(1)

U-0 U-0 R/W-0

— ERASE — —NVMOP<3:0>

(1)

R/W-0

(1)

R/W-0

(2)

(1)

R/W-0

(1)

bit 7 bit 0

Legend: SO = Settable Only bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control bit

1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0 = Program or erase operation is complete and inactive

bit 14 WREN: Write Enable bit

1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit

1 = An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0 = The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit

1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits

(2)

If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase general segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte

If ERASE =

0: 1111 = No operation 1101 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte

Note 1: These bits can only be Reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

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REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only)

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; Set up NVMCON for block erase operation

MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON

; Init pointer to row to be ERASED

MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7

; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted

5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY

One row of program Flash memory can be programmed at a time. To achieve this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is:

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits.

b) Write the starting address of the page to be

erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the

duration of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2).

5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

6. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.

For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3.

EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE

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; Set up NVMCON for row programming operations

MOV #0x4001, W0 ;

MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled

MOV #0x0000, W0 ;

MOV W0, TBLPAG ; Initialize PM Page Boundary SFR

MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word

MOV #LOW_WORD_0, W2 ;

MOV #HIGH_BYTE_0, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word

MOV #LOW_WORD_1, W2 ;

MOV #HIGH_BYTE_1, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word

MOV #LOW_WORD_2, W2 ;

MOV #HIGH_BYTE_2, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

•

; 63rd_program_word

MOV #LOW_WORD_31, W2 ;

MOV #HIGH_BYTE_31, W3 ;

TBLWTL W2, [W0] ; Write PM low word into program latch

TBLWTH W3, [W0++] ; Write PM high byte into program latch

DISI #5 ; Block all interrupts with priority <7

EXAMPLE 5-2: LOADING THE WRITE BUFFERS

EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE

Page 89

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

MCLR

VDD

Internal

Regulator

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect

POR

Configuration Mismatch

6.0 RESETS

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the “dsPIC33F Family Reference Manual”, Section 8. “Reset”

(DS70192), which is available from the Microchip web site (www.microchip.com).

The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR

: Master Clear Pin Reset

• SWR: Software RESET Instruction

• WDTO: Watchdog Timer Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

A simplified block diagram of the Reset module is shown in Figure 6-1.

. The

Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected.

Note: Refer to the specific peripheral section or

Section 3 .0 “CPU” of this data sheet for

All types of device Reset sets a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1).

A POR clears all the bits, except for the POR bit (RCON<0>), that are set. The user application can set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device Reset to occur.

The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset is meaningful.

FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM

Page 90

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

(1)

R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

TRAPR IOPUWR — — — —CMVREGS

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1

(2)

EXTR SWR SWDTEN

WDTO SLEEP IDLE BOR POR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred

bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0 = An illegal opcode or uninitialized W Reset has not occurred

bit 13-10 Unimplemented: Read as ‘0’ bit 9 CM: Configuration Mismatch Flag bit

1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has NOT occurred

bit 8 VREGS: Voltage Regulator Standby During Sleep bit

1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep

bit 7 EXTR: External Reset Pin (MCLR

) bit

1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset Flag (Instruction) bit

1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed

bit 5 SWDTEN: Software Enable/Disable of WDT bit

(2)

1 = WDT is enabled 0 = WDT is disabled

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT time-out has occurred 0 = WDT time-out has not occurred

bit 3 SLEEP: Wake-up from Sleep Flag bit

1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode

bit 2 IDLE: Wake-up from Idle Flag bit

1 = Device was in Idle mode 0 = Device was not in Idle mode

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

Page 91

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

(1)

(CONTINUED)

Page 92

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

6.1 System Reset

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 families of devices have two types of Reset:

•Cold Reset

•Warm Reset

A cold Reset is the result of a Power-on Reset (POR)

or a Brown-out Reset (BOR). On a cold Reset, the FNOSC Configuration bits in the FOSC Configuration register select the device clock source.

A warm Reset is the result of all the other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register.

The device is kept in a Reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. The sequence in which this occurs is detailed below and is shown in Figure 6-2.

1. POR Reset: A POR circuit holds the device in

Reset when the power supply is turned on. The POR circuit is active until V threshold and the delay, TPOR, has elapsed.

DD crosses the VPOR

2. BOR Reset: The on-chip voltage regulator has

a BOR circuit that keeps the device in Reset until V

DD crosses the VBOR threshold and the

delay, T

BOR, has elapsed. The delay, TBOR,

ensures that the voltage regulator output becomes stable.

3. PWRT Timer: The programmable power-up

timer continues to hold the processor in Reset for a specific period of time (T BOR. The delay T

PWRT ensures that the system

PWRT) after a

power supplies have stabilized at the appropriate level for full-speed operation. After the delay, T

PWRT, has elapsed, the SYSRST

becomes inactive, which in turn enables the selected oscillator to start generating clock cycles.

4. Oscillator Delay: The total delay for the clock to

be ready for various clock source selections is

given in Table 6-1. Refer to Section 8.0 “Oscillator Configu ration” for more information.

5. When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine.

6. The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay, T

FSCM,

elapsed.

TABLE 6-1: OSCILLATOR DELAY

Oscillator Mode

FRC, FRCDIV16, FRCDIVN T

FRCPLL TOSCD

XT TOSCD

HS TOSCD

Oscillator

Startup Delay

(1)

OSCD

(1) (1) (1)

EC ————

XTPLL TOSCD

HSPLL TOSCD

(1)

ECPLL — — TLOCK

LPRC TOSCD

(1)

Note 1: TOSCD = Oscillator start-up delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal oscillator start-up

times vary with crystal characteristics, load capacitance, etc.

OST = Oscillator start-up timer delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a

2: T

10 MHz crystal and T

OST = 32 ms for a 32 kHz crystal.

3: TLOCK = PLL lock time (1.5 ms nominal) if PLL is enabled.

Oscillator

Startup Timer

PLL Lock Time Total Delay

——TOSCD

—TLOCK

(2)

TOST

(2)

TOST

(2)

TOST

(2)

TOST

(3)

—TOSCD + TOST

(3)

TLOCK

(3)

TLOCK

(3)

——TOSCD

(1)

TOSCD + TLOCK

TOSCD + TOST +

LOCK

TLOCK

(1,2,3)

(3) (1)

(1,3) (1,2) (1,2)

Page 93

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Reset

Run

Device Status

VPOR

VBOR

POR Reset

BOR Reset

SYSRST

TPWRT

TPOR

TBOR

Oscillator Clock

OSCD TOST

TLOCK

Time

FSCM

Note 1: POR Reset : A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is

active until V

DD crosses the VPOR threshold and the delay, TPOR, has elapsed.

2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V

DD crosses

the V

BOR threshold and the delay, TBOR, has elapsed. The delay, TBOR, ensures the voltage regulator output

becomes stable.

3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period

of time (T

PWRT) after a BOR. The delay, TPWRT, ensures that the system power supplies have stabilized at the

appropriate level for full-speed operation. After the delay, T

PWRT has elapsed and the SYSRST becomes

inactive, which in turn, enables the selected oscillator to start generating clock cycles.

4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in

Table 6-1. Refer to Section 8.0 “Oscillator Configuration” for more information.

5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application

programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine.

6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is

ready and the delay, T

FSCM, has elapsed.

FIGURE 6-2: SYSTEM RESET TIMING

Page 94

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 6-2: OSCILLATOR DELAY

Symbol Parameter Value

VPOR POR threshold 1.8V nominal TPOR POR extension time 30 μs maximum

VBOR BOR threshold 2.5V nominal

BOR BOR extension time 100 μs maximum

TPWRT Programmable power-up time delay 0-128 ms nominal TFSCM Fail-Safe Clock Monitor delay 900 μs maximum

Note: When the device exits the Reset

condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device may not function correctly. The user application must ensure that the delay between the time power is first applied, and the time SYSRST

becomes inactive, is long enough to get all operating parameters within specification.

6.2 Power-on Reset (POR)

A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, T device bias circuits become stable.

The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to

Section 24.0 “Electrical Characteristics” for details.

The POR status (POR) bit in the Reset Control (RCON<0>) register is set to indicate the Power-on Reset.

POR, ensures the internal

6.2.1 Brown-out Reset (BOR) and Power-up Timer (PWRT)

The on-chip regulator has a Brown-out Reset (BOR) circuit that resets the device when the V

DD < VBOR) for proper device operation. The BOR

(V circuit keeps the device in Reset until V

BOR threshold and the delay, TBOR, has elapsed. The

V delay, T

BOR, ensures the voltage regulator output

becomes stable.

The BOR status (BOR) bit in the Reset Control (RCON<1>) register is set to indicate the Brown-out Reset.

The device will not run at full speed after a BOR as the

DD should rise to acceptable levels for full-speed

V operation. The PWRT provides power-up time delay

PWRT) to ensure that the system power supplies have

(T stabilized at the appropriate levels for full-speed operation before the SYSRST is released.

The power-up timer delay (T

PWRT) is programmed by

the Power-on Reset Timer Value Select (FPWRT<2:0>) bits in the POR Configuration (FPOR<2:0>) register, which provides eight settings

(from 0 ms to 128 ms). Refer to Section 21.0 “Special Features” for further details.

Figure 6-3 shows the typical brown-out scenarios. The reset delay (T

BOR + TPWRT) is initiated each time VDD

rises above the VBOR trip point

DD is too low

DD crosses the

Page 95

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

VDD

SYSRST

VBOR

SYSRST

VBOR

SYSRST

VBOR

BOR + TPWRT

VDD dips before PWRT expires

BOR + TPWRT

TBOR + TPWRT

FIGURE 6-3: BROWN-OUT SITUATIONS

6.3 External Reset (EXTR)

The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer

to Section 24.0 “Electrical Characteristics” for

minimum pulse width specifications. The external Reset (MCLR

) pin (EXTR) bit in the Reset Control

(RCON) register is set to indicate the MCLR

6.3.0.1 EXTERNAL SUPERVISORY CIRCUIT

Many systems have external supervisory circuits that generate Reset signals to reset multiple devices in the system. This external Reset signal can be directly connected to the MCLR

pin to reset the device when

the rest of system is reset.

6.3.0.2 INTERNAL SUPERVISORY CIRCUIT

When using the internal power supervisory circuit to reset the device, the external Reset pin (MCLR be tied directly or resistively to V

pin will not be used to generate a Reset. The

MCLR external Reset pin (MCLR pull-up and must not be left unconnected.

DD. In this case, the

) does not have an internal

6.4 Software RESET Instruction (SWR)

Whenever the RESET instruction is executed, the device will assert SYSRST special Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to

, placing the device in a

Reset.

) should

the RESET instruction will remain. SYSRST

is released at the next instruction cycle and the Reset vector fetch will commence.

The Software Reset (SWR) flag (instruction) in the Reset Control (RCON<6>) register is set to indicate the software Reset.

6.5 Watchdog Time-out Reset (WDTO)

Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST

. The clock source will remain unchanged. A WDT time-out during Sleep or Idle mode will wake-up the processor, but will not reset the processor.

The Watchdog Timer Time-out (WDTO) flag in the Reset Control (RCON<4>) register is set to indicate

the Watchdog Reset. Refer to Section 21.4 “Watchdog Timer (WDT)” for more information on

Watchdog Reset.

6.6 Trap Conflict Reset

If a lower priority hard trap occurs while a higher priority trap is being processed, a hard Trap Conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category.

The Trap Reset (TRAPR) flag in the Reset Control (RCON<15>) register is set to indicate the Trap Conflict

Reset. Refer to Section 7.0 “Interrupt Controller” for

more information on Trap Conflict Resets.

Page 96

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

6.7 Configuration Mismatch Reset

To maintain the integrity of the Peripheral Pin Select Control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset occurs.

The Configuration Mismatch (CM) flag in the Reset Control (RCON<9>) register is set to indicate the

Configuration Mismatch Reset. Refer to Section 10.0 “I/O Ports” for more information on the

Configuration Mismatch Reset.

Note: The Configuration Mismatch Reset

feature and associated Reset flag are not available on all devices.

6.8 Illegal Condition Device Reset

An illegal condition device Reset occurs due to the following sources:

• Illegal Opcode Reset

• Uninitialized W Register Reset

• Security Reset

The Illegal Opcode or Uninitialized W Access Reset (IOPUWR) flag in the Reset Control (RCON<14>) register is set to indicate the illegal condition device Reset.

each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value.

6.8.2 UNINITIALIZED W REGISTER RESET

Any attempt to use the uninitialized W register as an Address Pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to.

6.8.3 SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a Security Reset.

The PFC occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine or other form of branch instruction.

The VFC occurs when the program counter is reloaded with an interrupt or trap vector.

Refer to Section 21.8 “Code Protection and CodeGuard™ Security” for more information on

Security Reset.

6.9 Using the RCON Status Bits

6.8.1 ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory.

The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of

The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset.

Note: The status bits in the RCON register

should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.

Table 6-3 provides a summary of the Reset flag bit operation.

TA BLE 6-3: RESET FLAG BIT OPERATION

Flag Bit Set by: Cleared by:

TRAPR (RCON<15>) Trap conflict event POR,BOR IOPWR (RCON<14>) Illegal opcode or uninitialized W register

access or Security Reset

CM (RCON<9>) Configuration Mismatch POR,BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR,BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, CLRWDT instruction,

SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR,BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR,BOR BOR (RCON<1>) POR, BOR POR (RCON<0>) POR

Note: All Reset flag bits can be set or cleared by user software.

POR,BOR

Page 97

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

7.0 INTERRUPT CONTROLLER

Note: This data sheet summarizes the features

of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data

sheet, refer to the “dsPIC33F Family

Reference Manual”, Section 41. “Interrupts (Part IV)” (DS70300), which

is available on the Microchip web site (www.microchip.com).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU. It has the following features:

• Up to eight processor exceptions and software traps

• Seven user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug support

• Fixed interrupt entry and return latencies

7.1 Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of eight nonmaskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address.

PIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/

The X04 devices implement up to 35 unique interrupts and 4 non-maskable traps. These are summarized in Table 7-1.

7.1.1 ALTERNATE INTERRUPT VECTOR TAB LE

The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors.

The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT.

7.2 Reset Sequence

A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.

Page 98

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002

Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0 0x000014 Interrupt Vector 1

~ ~

~ Interrupt Vector 52 0x00007C Interrupt Vector 53 0x00007E Interrupt Vector 54 0x000080

Interrupt Vector 116 0x0000FC Interrupt Vector 117 0x0000FE

Reserved

0x000100 Reserved 0x000102 Reserved

Oscillator Fail Trap Vector Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved Reserved Reserved

Interrupt Vector 0 0x000114 Interrupt Vector 1

~ ~

~ Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180

Interrupt Vector 116 Interrupt Vector 117 0x0001FE

Start of Code 0x000200

Decreasing Natural Order Priority

Interrupt Vector Table (IVT)

(1)

Alternate Interrupt Vector Table (AIVT)

(1)

Note 1: See Table 7-1 for the list of implemented interrupt vectors.

FIGURE 7-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR

TABLE

Page 99

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 7-1: INTERRUPT VECTORS

Vector

Number

8 0 0x000014 0x000114 INT0 – External Interrupt 0

9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1

11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C Reserved 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3

17 9 0x000026 0x000126 SPI1E – SPI1 Fault 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC – ADC Group Convert Done

22 14 0x000030 0x000130 Reserved 23 15 0x000032 0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Event 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Event 26 18 0x000038 0x000138 CMP1 – Analog Comparator 1 Interrupt 27 19 0x00003A 0x00013A CN – Input Change Notification Interrupt

28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29 21 0x00003E 0x00013E Reserved 30 22 0x000040 0x000140 Reserved 31 23 0x000042 0x000142 Reserved 32 24 0x000044 0x000144 Reserved 33 25 0x000046 0x000146 Reserved

34 26 0x000048 0x000148 Reserved 35 27 0x00004A 0x00014A Reserved 36 28 0x00004C 0x00014C Reserved 37 29 0x00004E 0x00014E INT2 – External Interrupt 2

38-64 30-56 Reserved

65 57 0x000086 0x000186 PWM PSEM Special Event Match

66-72 58-64 Reserved

73 65 0x000096 0x000196 U1E – UART1 Error Interrupt

74-101 66-93 Reserved

102 94 0x0000D0 0x0001D0 PWM1 – PWM1 Interrupt 103 95 0x0000D2 0x0001D2 PWM2 – PWM2 Interrupt 104 96 0x0000D4 0x0001D4 PWM3 – PWM3 Interrupt

105 97 0x0000D6 0x0001D6 PWM4 – PWM4 Interrupt 106 98 0x0000D8 0x0001D8 Reserved 107 99 0x0000DA 0x0001DA Reserved 108 100 0x0000DC 0x0001DC Reserved 109 101 0x0000DE 0x0001DE Reserved 110 102 0x0000E0 0x0001E0 Reserved

111 103 0x0000E2 0x00001E2 CMP2 – Analog Comparator 2

Interrupt

Request

(IQR)

IVT Address AIVT Address Interrupt Source

Highest Natural Order Priority

Page 100

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 7-1: INTERRUPT VECTORS (CONTINUED)

Vector

Number

112 104 0x0000E4 0x0001E4 CMP3 – Analog Comparator 3

113 105 0x0000E6 0x0001E6 CMP4 – Analog Comparator 4 114 106 0x0000E8 0x0001E8 Reserved 115 107 0x0000EA 0x0001EA Reserved 116 108 0x0000EC 0x0001EC Reserved 117 109 0x0000EE 0x0001EE Reserved 118 110 0x0000F0 0x0001F0 ADC Pair 0 Convert Done

119 111 0x0000F2 0x0001F2 ADC Pair 1 Convert Done 120 112 0x0000F4 0x0001F4 ADC Pair 2 Convert Done 121 113 0x0000F6 0x0001F6 ADC Pair 3 Convert Done 122 114 0x0000F8 0x0001F8 ADC Pair 4 Convert Done 123 115 0x0000FA 0x0001FA ADC Pair 5 Convert Done 124 116 0x0000FC 0x0001FC ADC Pair 6 Convert Done

125 117 0x0000FE 0x0001FE Reserved

Interrupt Request

(IQR)

IVT Address AIVT Address Interrupt Source

Lowest Natural Order Priority

Datasheet dsPIC33FJ06GS102 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Operating Range:

High-Performance DSC CPU:

Digital I/O:

On-Chip Flash and SRAM:

Peripheral Features:

Interrupt Controller:

High-Speed PWM Module Features:

High-Speed Analog Comparator

High-Speed 10-Bit ADC

Power Management:

CMOS Flash T echnology:

System Management:

Application Examples

Packaging:

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families

Pin Diagrams

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Pin Diagrams (Continued)

Table of Contents

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM

TABLE 1-1: PINOUT I/O DESCRIPTIONS

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

2.1 Basic Connection Requirements

2.2 Decoupling Capacitors

2.2.1 TANK CAPACITORS

2.4 Master Clear (MCLR) Pin

2.5 ICSP Pins

2.6 External Oscillator Pins

2.7 Oscillator Value Conditions on Device Start-up

2.8 Configuration of Analog and Digital Pins During ICSP Operations

2.9 Unused I/Os

2.10 Typical Application Connection Examples

FIGURE 2-4: DIGITAL PFC

FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION

FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER

FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER

FIGURE 2-8: OFF-LINE UPS

FIGURE 2-9: INTERLEAVED PFC

FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER

FIGURE 2-11: AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V)

3.0 CPU

3.1 Data Addressing Overview

3.2 DSP Engine Overview

3.3 Special MCU Features

FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL

3.4 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

3.5 Arithmetic Logic Unit (ALU)

3.5.1 MULTIPLIER

3.5.2 DIVIDER

3.6 DSP Engine

TABLE 3-1: DSP INSTRUCTIONS SUMMARY

FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM

3.6.1 MULTIPLIER

3.6.3 ACCUMULATOR ‘WRITE BACK’

3.6.4 BARREL SHIFTER

4.0 MEMORY ORGANIZATION

4.1 Program Address Space

4.1.1 PROGRAM MEMORY ORGANIZATION

4.1.2 INTERRUPT AND TRAP VECTORS

FIGURE 4-2: PROGRAM MEMORY ORGANIZATION

4.2 Data Address Space

4.2.1 DATA SPACE WIDTH

4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

4.2.3 SFR SPACE