dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302
16-Bit Microcontrollers and Digital Signal Controllers with
High-Speed PWM, ADC and Comparators
Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Core: 16-Bit dsPIC33F CPU
• Code Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
• ±2% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 2.0 mA/MHz Dynamic Current (typical)
•135 µA I
PD Current (typical)
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 1.04 ns PWM Resolution for Dead Time, Duty Cycle,
Phase and Frequency
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• Two High-Speed Comparators with Direct Connection to
the PWM module:
- Buffered/amplified output drive
- Independent 10-bit DAC for each comparator
- Rail-to-rail comparator operation
- DACOUT amplifier (1x, 1.8x)
- Selectable hysteresis
- Programmable output polarity
- Interrupt generation capability
Advanced Analog Features (Continued)
• ADC module:
- 10-bit resolution with Successive Approximation
Register (SAR) converter (2 Msps) and three
Sample-and-Hold (S&H) circuits
- Up to 8 input channels grouped into four conversion
pairs, plus two inputs for monitoring voltage references
- Flexible and independent ADC trigger sources
- Dedicated Result register for each
analog channel
Timers/Output Compare/Input Capture
• Two 16-Bit General Purpose Timers/Counters
• Input Capture module
• Output Compare module
• Peripheral Pin Select (PPS) to allow Function Remap
Communication Interfaces
• UART module (10 Mbps):
- With support for LIN/J2602 protocols and IrDA
• 4-Wire SPI module
2
C™ module (up to 1 Mbaud) with SMBus Support
•I
• PPS to allow Function Remap
®
Input/Output
• Constant Current Source:
- Constant current generator (10 µA nominal)
• Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• External Interrupts on 16 I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-Circuit and In-Application Programming
• Two Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
2011-2012 Microchip Technology Inc. DS75018C-page 1
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in Ta b le 1 . The
following pages show their pinout diagrams.
TABLE 1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES
Remappable Peripherals
(1)
ADC
Device
dsPIC33FJ06GS001
dsPIC33FJ06GS101A
dsPIC33FJ06GS102A
dsPIC33FJ06GS202A
dsPIC33FJ09GS302
Note 1:
INT0 is not remappable.
2:
The PWM4 pair is remappable and only available on dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices.
Pins
RAM (Bytes)
Program Flash Memory (Kbytes)
18
62568200 002x22 3 00011 2 613
20 SSOP
18
62568201 112x20 3 00111 3 613
20 SSOP
28
6256162011 12x20 3 00111 3 621
36 VTLA
28
61K162111 12x22 3 10111 3 621
36 VTLA
28
91K162111 13x22 3 11111 3 821
36 VTLA
16-Bit Timer
Remappable Pins
Input Capture
UART
Output Compare
(2)
SPI
PWM
Analog Comparator
DAC Output
External Interrupts
Constant Current Source
Reference Clock
2
C™
I
SARs
I/O Pins
Analog-to-Digital Inputs
Sample-and-Hold (S&H) Circuit
PDIP,
SOIC
PDIP,
SOIC
SPDIP,
SOIC,
SSOP,
QFN-S
SPDIP,
SOIC,
SSOP,
QFN-S
SPDIP,
SOIC,
SSOP,
QFN-S
Packages
DS75018C-page 2 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
18-Pin SOIC, PDIP
dsPIC33FJ06GS001
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
V
DD
VSS
AN2/CMP1C/CMP2A/RA2
TDO/RP5
(1)
/CN5/RB5
PGEC2/TMS/EXTREF/RP4
(1)
/CN4/RB4
PGED2/TCK/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSC2/CLKO/AN7/RP2
(1)
/CN2/RB2
OSC1/CLKI/AN6/RP1
(1)
/CN1/RB1
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PWM1L/RA3
PWM1H/RA4
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
= Pins are up to 5V tolerant
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AV
DD
AVSS
AN2/CMP1C/CMP2A/RA2
TDO/RP5
(1)
/CN5/RB5
PGEC2/TMS/EXTREF/RP4
(1)
/CN4/RB4
PGED2/TCK/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSCO/CLKO/AN7/RP2
(1)
/CN2/RB2
OSCI/CLKI/AN6/RP1
(1)
/CN1/RB1
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
PWM1L/RA3
PWM1H/RA4
VDD
VSS
20-Pin SSOP
= Pins are up to 5V tolerant
dsPIC33FJ06GS001
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
19
20
MCLR
AN0/RA0
AN1/RA1
V
DD
VSS
AN2/RA2
TDO/RP5
(1)
/CN5/RB5
PGEC2/TMS/RP4
(1)
/CN4/RB4
PGED2/TCK/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSC2/CLKO/AN7/RP2
(1)
/CN2/RB2
OSC1/CLKI/AN6/RP1
(1)
/CN1/RB1
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
AN3/RP0
(1)
/CN0/RB0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PWM1L/RA3
PWM1H/RA4
dsPIC33FJ06GS101A
MCLR
AN0/RA0
AN1/RA1
AV
DD
AVSS
AN2/RA2
TDO/RP5
(1)
/CN5/RB5
PGEC2/TMS/RP4
(1)
/CN4/RB4
PGED2/TCK/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSCO/CLKO/AN7/RP2
(1)
/CN2/RB2
OSCI/CLKI/AN6/RP1
(1)
/CN1/RB1
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
AN3/RP0
(1)
/CN0/RB0
PWM1L/RA3
PWM1H/RA4
VDD
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
19
20
dsPIC33FJ06GS101A
Pin Diagrams
2011-2012 Microchip Technology Inc. DS75018C-page 3
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
28-Pin SPDIP, SOIC, SSOP
dsPIC33FJ09GS302
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TCK/RP12
(1)
/CN12/RB12
TMS/RP11
(1)
/CN11/RB11
V
SS
VDD
AN0/CMP1A/RA0
AN1/CMP1B1/RA1
AV
DD
AVSS
AN2/CMP1C/CMP2A/RA2
PGED3/RP8
(1)
/CN8/RB8
PGEC3/RP15/CN15/RB15
PGEC2/EXTREF/RP4
(1)
/CN4/RB4
PGED2/DACOUT/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSC2/CLKO/AN7/ISRC1/RP2
(1)
/CN2/RB2
OSC1/CLKI/AN6/ISRC2/RP1
(1)
/CN1/RB1
V
SS
TDO/RP5
(1)
/CN5/RB5
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
AN5/ISRC3/CMP2D/RP10
(1)
/CN10/RB10
AN4/ISRC4/CMP2C/RP9
(1)
/CN9/RB9
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
= Pins are up to 5V tolerant
28-Pin SOIC, SPDIP, SSOP
dsPIC33FJ06GS102A
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TCK/RP12
(1)
/CN12/RB12
TMS/RP11
(1)
/CN11/RB11
V
SS
VDD
AN0/RA0
AN1/RA1
AV
DD
AVSS
AN2/RA2
PGED3/RP8
(1)
/CN8/RB8
PGEC3/RP15
(1)
/CN15/RB15
PGEC2/RP4
(1)
/CN4/RB4
PGED2/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSC2/CLKO/RP2
(1)
/CN2/RB2
OSC1/CLKI/RP1
(1)
/CN1/RB1
V
SS
TDO/RP5
(1)
/CN5/RB5
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/1SCL1/RP6
(1)
/CN6/RB6
AN5/RP10
(1)
/CN10/RB10
AN4/RP9
(1)
/CN9/RB9
AN3/RP0
(1)
/CN0/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SPDIP, SOIC, SSOP
dsPIC33FJ06GS202A
MCLR
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TCK/RP12
(1)
/CN12/RB12
TMS/RP11
(1)
/CN11/RB11
V
SS
VDD
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AV
DD
AVSS
AN2/CMP1C/CMP2A/RA2
PGED3/RP8
(1)
/CN8/RB8
PGEC3/RP15
(1)
/CN15/RB15
PGEC2/EXTREF/RP4
(1)
/CN4/RB4
PGED2/DACOUT/INT0/RP3
(1)
/CN3/RB3
V
CAP
OSC2/CLKO/RP2
(1)
/CN2/RB2
OSC1/CLKI/RP1
(1)
/CN1/RB1
V
SS
TDO/RP5
(1)
/CN5/RB5
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
AN5/CMP2D/RP10
(1)
/CN10/RB10
AN4/CMP2C/RP9
(1)
/CN9/RB9
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
Note 1: The RPn pins can be used by any remappable peripheral. See Ta bl e 1 for the list of available peripherals.
Pin Diagrams (Continued)
DS75018C-page 4 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
28-Pin QFN-S
(2)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ06GS102A
PGED2/INT0/RP3
(1)
/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TCK/RP12
(1)
/CN12/RB12
TMS/RP11
(1)
/CN11/RB11
V
SS
VCAP
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
TDO/RP5
(1)
/CN5/RB5
PGEC3/RP15
(1)
/CN15/RB15
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
AN3/RP0
(1)
/CN0/RB0
AN4/RP9
(1)
/CN9/RB9
AN5/RP10
(1)
/CN10/RB10
V
SS
OSC1/CLKI/RP1
(1)
/CN1/RB1
OSC2/CLKO/RP2
(1)
/CN2/RB2
PGEC2/RP4
(1)
/CN4/RB4
V
DD
PGED3/RP8
(1)
/CN8/RB8
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ06GS202A
PGED2/DACOUT/INT0/RP3
(1)
/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TCK/RP12
(1)
/CN12/RB12
TMS/RP11
(1)
/CN11/RB11
V
SS
VCAP
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
TDO/RP5
(1)
/CN5/RB5
PGEC3/RP15
(1)
/CN15/RB15
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
AN4/CMP2C/RP9
(1)
/CN9/RB9
AN5/CMP2D/RP10
(1)
/CN10/RB10
V
SS
OSC1/CLKI/RP1
(1)
/CN1/RB1
OSC2/CLKO/RP2
(1)
/CN2/RB2
PGEC2/EXTREF/RP4
(1)
/CN4/RB4
V
DD
PGED3/RP8
(1)
/CN8/RB8
Note 1: The RPn pins can be used by any remappable peripheral. See Ta bl e 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
V
SS externally.
= Pins are up to 5V tolerant
= Pins are up to 5V tolerant
28-Pin QFN-S
(2)
Pin Diagrams (Continued)
2011-2012 Microchip Technology Inc. DS75018C-page 5
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
28-Pin QFN-S
(2)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
dsPIC33FJ09GS302
PGED2/DACOUT/INT0/RP3
(1)
/CN3/RB3
5
4
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TCK/RP12
(1)
/CN12/RB12
TMS/RP11
(1)
/CN11/RB11
V
SS
VCAP
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
TDO/RP5
(1)
/CN5/RB5
PGEC3/RP15
(1)
/CN15/RB15
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
AN4/ISRC4/CMP2C/RP9
(1)
/CN9/RB9
AN5/ISRC3/CMP2D/RP10
(1)
/CN10/RB10
V
SS
OSC1/CLKI/AN6/ISRC2/RP1
(1)
/CN1/RB1
OSC2/CLKO/AN7/ISRC1//RP2
(1)
/CN2/RB2
PGEC2/EXTREF/RP4
(1)
/CN4/RB4
V
DD
PGED3/RP8
(1)
/CN8/RB8
Note 1: The RPn pins can be used by any remappable peripheral. See Ta bl e 1 for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
V
SS externally.
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
DS75018C-page 6 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
36-Pin VTLA
Note 1: The RPn pins can be used by any remappable peripheral. See Ta ble 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
1
dsPIC33FJ06GS102A
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
AN1/RA1
AN2/RA2
AN3/RP0
(1)
/CN0/RB0
MCLR
AVDD
PWM1L/RA3
RMW1H/RA4
AV
SS
AN0/RA0
N/C
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TMS/RP11
(1)
/CN11/RB11
TCK/RP12
(1)
/CN12/RB12
V
DD
VCAP
VDD
AN4/RP9
(1)
/CN9/RB9
NC
OSCO/CLKO/RP2
(1)
/CN2/RB2
NC
NC
AN5/RP10
(1)
/CN10/RB10
V
SS
OSCI/CLKI/RP1
(1)
/CN1/RB1
VSS
PGEC2/RP4
(1)
/CN4/RB4
PGED3/RP8
(1)
/CN8/RB8
PGED2/INT0/RP3
(1)
/CN3/RB3
PGEC3/RP15
(1)
/CN15/RB15
TDO/RP5
(1)
/CN5/RB5
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
V
DD
VDD
7
8
9
34
35
36
16
17
18
27
26
25
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
2011-2012 Microchip Technology Inc. DS75018C-page 7
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
36-Pin VTLA
Note 1: The RPn pins can be used by any remappable peripheral. See Ta ble 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to V
SS externally.
1
dsPIC33FJ06GS202A
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
MCLR
AVDD
PWM1L/RA3
RMW1H/RA4
AV
SS
AN0/CMP1A/RA0
N/C
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TMS/RP11
(1)
/CN11/RB11
TCK/RP12
(1)
/CN12/RB12
V
DD
VCAP
VDD
AN4/CMP2C/RP9
(1)
/CN9/RB9
NC
OSCO/CLKO/RP2
(1)
/CN2/RB2
NC
NC
AN5/CMP2D/RP10
(1)
/CN10/RB10
V
SS
OSCI/CLKI/RP1
(1)
/CN1/RB1
VSS
PGEC2/EXTREF/RP4
(1)
/CN4/RB4
PGED3/RP8
(1)
/CN8/RB8
PGED2/DACOUT/INT0/RP3
(1)
/CN3/RB3
PGEC3/RP15
(1)
/CN15/RB15
TDO/RP5
(1)
/CN5/RB5
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
V
DD
VDD
7
8
9
34
35
36
16
17
18
27
26
25
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
DS75018C-page 8 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
36-Pin VTLA
Note 1: The RPn pins can be used by any remappable peripheral. See Ta bl e 1 for the list of available peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
V
SS externally.
1
dsPIC33FJ09GS302
10
33 32 31 30 29 28
2
3
4
5
6
24
23
22
21
20
19
11 12 13 14 15
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0
(1)
/CN0/RB0
MCLR
AVDD
PWM1L/RA3
RMW1H/RA4
AV
SS
AN0/CMP1A/RA0
N/C
V
SS
PGEC1/SDA1/RP7
(1)
/CN7/RB7
PWM2L/RP14
(1)
/CN14/RB14
PWM2H/RP13
(1)
/CN13/RB13
TMS/RP11
(1)
/CN11/RB11
TCK/RP12
(1)
/CN12/RB12
V
DD
VCAP
VDD
AN4/ISRC4/CMP2C/RP9
(1)
/CN9/RB9
NC
OSCO/CLKO/AN7/ISRC1/RP2
(1)
/CN2/RB2
NC
NC
AN5/ISRC3/CMP2D/RP10
(1)
/CN10/RB10
V
SS
OSCI/CLKI/AN6/ISRC2/RP1
(1)
/CN1/RB1
VSS
PGEC2/EXTREF/RP4
(1)
/CN4/RB4
PGED3/RP8
(1)
/CN8/RB8
PGED2/DACOUT/INT0/RP3
(1)
/CN3/RB3
PGEC3/RP15
(1)
/CN15/RB15
TDO/RP5
(1)
/CN5/RB5
PGED1/TDI/SCL1/RP6
(1)
/CN6/RB6
V
DD
VDD
7
8
9
34
35
36
16
17
18
27
26
25
= Pins are up to 5V tolerant
Pin Diagrams (Continued)
2011-2012 Microchip Technology Inc. DS75018C-page 9
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers .......................................................................................... 17
3.0 CPU ............................................................................................................................................................................................ 25
4.0 Memory Organization ................................................................................................................................................................. 37
5.0 Flash Program Memory .............................................................................................................................................................. 75
6.0 Resets ....................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 87
8.0 Oscillator Configuration ......................................................................................................................................................... 123
9.0 Power-Saving Features ............................................................................................................................................................ 137
10.0 I/O Ports ................................................................................................................................................................................... 145
11.0 Timer1 ...................................................................................................................................................................................... 173
12.0 Timer2 Features ....................................................................................................................................................................... 175
13.0 Input Capture............................................................................................................................................................................ 177
14.0 Output Compare....................................................................................................................................................................... 179
15.0 High-Speed PWM..................................................................................................................................................................... 183
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205
17.0 Inter-Integrated Circuit™ (I
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 219
19.0 High-Speed 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................. 225
20.0 High-Speed Analog Comparator .............................................................................................................................................. 243
21.0 Constant Current Source.......................................................................................................................................................... 249
22.0 Special Features ...................................................................................................................................................................... 251
23.0 Instruction Set Summary .......................................................................................................................................................... 259
24.0 Development Support............................................................................................................................................................... 267
25.0 Electrical Characteristics .......................................................................................................................................................... 271
26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 315
27.0 Packaging Information.............................................................................................................................................................. 319
Appendix A: Revision History............................................................................................................................................................. 339
Index ................................................................................................................................................................................................. 341
2
C™).............................................................................................................................................. 211
DS75018C-page 10 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2011-2012 Microchip Technology Inc. DS75018C-page 11
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered the primary reference for the operation of a
particular module or device feature.
Note: To access the documents listed below,
visit the Microchip web site
(www.microchip.com).
• Section 1. “Introduction” (DS70197)
• Section 2. “CPU” (DS70204)
• Section 3. “Data Memory” (DS70202)
• Section 4. “Program Memory” (DS70203)
• Section 5. “Flash Programming” (DS70191)
• Section 8. “Reset” (DS70192)
• Section 9. “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196)
• Section 10. “I/O Ports” (DS70193)
• Section 11. “Timers” (DS70205)
• Section 12. “Input Capture” (DS70198)
• Section 13. “Output Compare” (DS70209)
• Section 17. “UART” (DS70188)
• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
• Section 19. “Inter-Integrated Circuit™ (I
• Section 24. “Programming and Diagnostics” (DS70207)
• Section 25. “Device Configuration” (DS70194)
• Section 41. “Interrupts (Part IV)” (DS70300)
• Section 42. “Oscillator (Part IV)” (DS70307)
• Section 43. “High-Speed PWM” (DS70323)
• Section 44. “High-Speed 10-Bit ADC” (DS70321)
• Section 45. “High-Speed Analog Comparator” (DS70296)
2
C™)” (DS70195)
DS75018C-page 12 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
1.0 DEVICE OVERVIEW
Note: This data sheet summarizes the features of
the dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest “dsPIC33F/PIC24H Family
Reference Manual” sections.
This document contains device-specific information for
the following dsPIC33F Digital Signal Controller (DSC)
devices:
• dsPIC33FJ06GS001
• dsPIC33FJ06GS101A
• dsPIC33FJ06GS102A
• dsPIC33FJ06GS202A
• dsPIC33FJ09GS302
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices contain extensive
Digital Signal Processor (DSP) functionality with a
high-performance, 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the devices. Table 1-1 lists the
functions of the various pins shown in the pinout
diagrams.
2011-2012 Microchip Technology Inc. DS75018C-page 13
16
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
FRC/LPRC
Oscillators
Regulator
Volta ge
VCAP
IC1
I2C1
PORTA
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program
Data Latch
Literal Data
16
16
16
16
Data Latch
Address
Latch
16
X RAM
Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1Time r1 ,2
PORTB
Address Generator Units
CNx
UART1
PWM
3 x 2
Remappable
Pins
SPI1
OC1
Analog
Comparator 1, 2
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
Reference
Constant
Current
Source
Clock
Memory
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 1-1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 BLOCK DIAGRAM
DS75018C-page 14 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Name
AN0-AN7 I Analog No Analog input channels.
CLKI
CLKO
OSC1
OSC2
CN0-CN15 I ST No Change notification inputs. Can be software programmed for
IC1 I ST Yes Capture Input 1.
OCFA
OC1
INT0
INT1
INT2
RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15
RP0-RP15
T1CK
T2CK
U1CTS
U1RTS
U1RX
U1TX
SCK1
SDI1
SDO1
SS1
SCL1
SDA1
TMS
TCK
TDI
TDO
Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
(1)
(1)
ST = Schmitt Trigger input with CMOS levels P = Power O = Output
TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select — = Does not apply
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.
Pin
Type
I/O
O
I/O ST No PORTB is a bidirectional I/O port.
I/O ST No Remappable I/O pins.
O
O
I/O
O
I/O
I/O
I/O
O
Buffer
Type
IOST/CMOS—NoNoExternal clock source input. Always associated with OSC1 pin
I
ST/CMOS—NoNoOscillator crystal input. ST buffer when configured in RC mode;
I
I
I
I
I
I
I
I
I
I
I
I
ST
—
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
—
ST
ST
ST
TTL
TTL
TTL
—
PPS
Capable
function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes. Always associated with OSC2 pin function.
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes.
internal weak pull-ups on all inputs.
Yes
Compare Fault A input (for Compare Channel 1).
Yes
Compare Output 1.
No
External Interrupt 0.
Yes
External Interrupt 1.
Yes
External Interrupt 2.
Yes
Timer1 external clock input.
Yes
Timer2 external clock input.
Yes
UART1 Clear-to-Send.
Yes
UART1 Ready-to-Send.
Yes
UART1 receive.
Yes
UART1 transmit.
Yes
Synchronous serial clock input/output for SPI1.
Yes
SPI1 data in.
Yes
SPI1 data out.
Yes
SPI1 slave synchronization or frame pulse I/O.
NoNoSynchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
No
JTAG Test mode select pin.
No
JTAG test clock input pin.
No
JTAG test data input pin.
No
JTAG test data output pin.
Description
2011-2012 Microchip Technology Inc. DS75018C-page 15
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
DACOUT O — No DAC output voltage.
ACMP1-ACMP2 O — Yes DAC trigger to PWM module.
ISRC1
ISRC2
ISRC3
ISRC4
(2)
(2)
(2)
(2)
O
O
O
O
EXTREF I Analog No External voltage reference input for the reference DACs.
REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system
FLT1-FLT8 I ST Yes Fault inputs to PWM module.
SYNCI1-SYNCI2
SYNCO1
PWM1L
PWM1H
PWM2L
PWM2H
PWM4L
PWM4H
PGED1
O
O
O
O
O
O
O
I/O
PGEC1
PGED2
I/O
PGEC2
PGED3
PGEC3
MCLR
(1)
(1)
I/O
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
AVDD P P No Positive supply for analog modules. This pin must be connected
AVSS P P No Ground reference for analog modules. AV
DD P — No Positive supply for peripheral logic and I/O pins.
V
V
CAP P — No CPU logic filter capacitor connection.
V
SS P — No Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input
ST = Schmitt Trigger input with CMOS levels P = Power O = Output
TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select — = Does not apply
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.
Buffer
Typ e
I
Analog
I
Analog
I
Analog
I
Analog
I
Analog
I
Analog
I
Analog
I
Analog
—
—
—
—
PPS
Capable
No
No
No
No
No
No
No
No
No
No
No
No
Description
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A.
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
Constant Current Source Output 1.
Constant Current Source Output 2.
Constant Current Source Output 3.
Constant Current Source Output 4.
clock.
I
I
ST
—
—
—
—
—
—
—
ST
ST
Yes
External synchronization signal to PWM master time base.
Yes
PWM master time base for external device synchronization.
No
PWM1 low output.
No
PWM1 high output.
No
PWM2 low output.
No
PWM2 high output.
Yes
PWM4 low output.
Yes
PWM4 high output.
No
Data I/O pin for programming/debugging Communication Channel 1.
No
Clock input pin for programming/debugging Communication
Channel 1.
ST
I
ST
No
Data I/O pin for programming/debugging Communication Channel 2.
No
Clock input pin for programming/debugging Communication
Channel 2.
ST
I
ST
No
Data I/O pin for programming/debugging Communication Channel 3.
No
Clock input pin for programming/debugging Communication
Channel 3.
device.
at all times. AVDD is connected to VDD on 18 and 28-pin devices.
SS is connected to VSS
on 18 and 28-pin devices.
DS75018C-page 16 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1 Basic Connection Requirements
Getting started with the dsPIC33FJ06GS001/101A/
102A/202A and dsPIC33FJ09GS302 family of 16-bit
Digital Signal Controllers (DSCs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names which must always be connected:
DD and VSS pins
• All V
(see Section 2.2 “Decoupling Capacitors”)
• All AV
•V
•MCLR
• PGECx/PGEDx pins used for In-Circuit Serial
• OSC1 and OSC2 pins when external oscillator
DD and AVSS pins, regardless if ADC module
is not used
(see Section 2.2 “Decoupling Capacitors”)
CAP
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (V
(see Section 2.4 “Master Clear (MCLR) Pin”)
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP™ Pins”)
source is used
(see Section 2.6 “External Oscillator Pins”)
CAP)”)
pin
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as V
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible;
for example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
DD, VSS, AVDD and
2011-2012 Microchip Technology Inc. DS75018C-page 17
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
dsPIC33F
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
C
R
V
DD
MCLR
0.1 µF
Ceramic
VCAP
L1
(1)
R1
10 µF
Tantalum
Note 1: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between V
DD and
AV
DD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
f
FCNV
2
--------------=
f
1
2 LC
-----------------------=
L
1
2fC
----------------------
2
=
(i.e., ADC conversion rate/2)
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR
pin VIH and VIL specifications are
met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR
pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin V
IH and VIL specifications are met.
C
R1
(2)
R
(1)
VDD
MCLR
dsPIC33F
JP
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTION
2.2.1 TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a
local power source. The value of the tank capacitor
should be determined based on the trace resistance
that connects the power supply source to the device,
and the maximum current drawn by the device in the
application. In other words, select the tank capacitor so
that it meets the acceptable voltage sag at the device;
typical values range from 4.7 µF to 47 µF.
2.3 Capacitor on Internal Voltage
Regulator (V
A low-ESR (<0.5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage regulator
output voltage. The V
VDD, and must have a capacitor between 4.7 µF and
10 µF, 16V connected to ground. The type can be
ceramic or tantalum. Refer to Section 25.0 “Electrical
Characteristics” for additional information.
The placement of this capacitor should be close to the
CAP. It is recommended that the trace length not
V
exceed one-quarter inch (6 mm). Refer to Section 22.2
“On-Chip Voltage Regulator” for details.
CAP)
CAP pin must not be connected to
2.4 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device Programming and Debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is recommended
that the capacitor, C, be isolated from the MCLR
during programming and debugging operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
pin. Consequently,
pin
pin.
DS75018C-page 18 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
13
Main Oscillator
Guard Ring
Guard Trace
Secondary
Oscillator
14
15
16
17
18
19
20
2.5 ICSP™ Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging
purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins, are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and Input Voltage High (V
and Input Voltage Low (VIL) pin requirements.
Ensure that the “Communication Channel Select”
(i.e., PGECx/PGEDx pins), programmed into the
device matches the physical connections for the ICSP
to MPLAB
®
ICD 3 or MPLAB REAL ICE™.
For more information on MPLAB ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web site
www.microchip.com):
(
• “Using MPLAB® ICD 3” (poster) (DS51765)
• “Multi-Tool Design Advisory” (DS51764)
®
• “MPLAB
REAL ICE™ In-Circuit Emulator User’s
Guide” (DS51616)
®
• “Using MPLAB
REAL ICE™” (poster) (DS51749)
IH)
2.6 External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
2011-2012 Microchip Technology Inc. DS75018C-page 19
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2.7 Oscillator Value Conditions on Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
start-up conditions. This means that if the external
oscillator frequency is outside of this range, the
application must start up in the FRC mode first. The
default PLL settings after a POR, with an oscillator
frequency outside of this range, will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
IN < 8 MHz to comply with device PLL
2.8 Configuration of Analog and Digital Pins During ICSP Operations
If MPLAB ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analog-to-Digital
input pins (ANx) as “digital” pins, by setting all bits in the
ADPCFG register.
The bits in the registers that correspond to the
Analog-to-Digital pins that are initialized by MPLAB
ICD 3 or REAL ICE, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain Analog-to-Digital
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the ADPCFG register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG register. Automatic
initialization of these registers is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all Analog-to-Digital pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between V
and unused pins, and drive the output to logic low.
SS
2.10 Typical Application Connection Examples
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-8.
DS75018C-page 20 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
VAC
IPFC
VHV_BUS
ADC Channel ADC Channel
ADC Channel
PWM Output
|VAC|
k
1
k
2
k
3
FET
dsPIC33FJ06GS001
Driver
IPFC
VOUTPUT
ADC Channel
ADC
ADC Channel
PWM
k
1
k
2
k
3
FET
dsPIC33FJ06GS001
VINPUT
Channel Output
Driver
FIGURE 2-4: DIGITAL PFC
FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION
2011-2012 Microchip Technology Inc. DS75018C-page 21
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
k
1
Analog
Comp.
k
2
k
7
PWM
PWM
ADC
Channel
ADC
Channel
5V Output
I
5V
12V Input
dsPIC33FJ06GS202A
FET
Driver
VAC
VOUT+
ADC Channel PWM ADCPWM
|V
AC|
k
4
k
3
FET
dsPIC33FJ06GS202A
Driver
V
OUT-
ADC Channel
FET
Driver
ADC
k
1
k
2
Channel
Channel
ADC
Channel
FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
FIGURE 2-7: INTERLEAVED PFC
DS75018C-page 22 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
VIN+
V
IN-
S1
Gate 4
Gate 2
Gate 3
Gate 1
Analog
Ground
VOUT+
V
OUT-
k
2
FET
Driver
k
1
FET
Driver
FET
Driver
Gate 1
Gate 2
S1
Gate 3
Gate 4
S3
S3
Gate 6
Gate 5
Gate 6
Gate 5
dsPIC33FJ09GS302
PWM
PWM ADC
Channel
PWM ADC
Channel
FIGURE 2-8: PHASE-SHIFTED FULL-BRIDGE CONVERTER
2011-2012 Microchip Technology Inc. DS75018C-page 23
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
NOTES:
DS75018C-page 24 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
3.0 CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The CPU module has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, including
significant support for DSP. The CPU has a 24-bit
instruction word with a variable length opcode field. The
Program Counter (PC) is 23 bits wide and addresses up
to 4M x 24 bits of user program memory space. The
actual amount of program memory implemented varies
from device to device. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute in
a single cycle, with the exception of instructions that
change the program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO and
REPEAT instructions, both of which are interruptible at
any point.
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices have sixteen, 16-bit
working registers in the programmer’s model. Each of the
working registers can serve as a Data, Address or
Address Offset register. The sixteenth working register
(W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
There are two classes of instruction: MCU and DSP.
These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed
for optimum C compiler efficiency. For most instructions, the devices are capable of executing a data
(or program data) memory read, a working register
(data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported, allowing A + B = C operations to be executed
in a single cycle.
A block diagram of the CPU is shown in Figure 3-1,
and the programmer’s model is shown in Figure 3-2.
3.1 Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through
the X memory AGU, which accesses the entire
memory map as one linear data space. Certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y data space
boundary is device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software boundary
checking overhead for DSP algorithms. Furthermore,
the X AGU Circular Addressing can be used with any of
the MCU class of instructions. The X AGU also supports
Bit-Reversed Addressing to greatly simplify input or
output data reordering for radix-2 FFT algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
3.2 DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits, right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
2011-2012 Microchip Technology Inc. DS75018C-page 25
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Instruction
Decode and
Control
PCH PCL
Program Counter
16-Bit ALU
24
23
Instruction Reg
PCU
ROM Latch
EA MUX
Interrupt
Controller
Stac k
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Control Signals
to Various Blocks
Literal Data
16
16
16
To Peripheral Modules
Data Latch
Address
Latch
16
X RAM
Y RAM
Address Generator Units
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
16
23
23
16
8
PSV and Table
Data Access
Control Block
16
16
16
16
Program Memory
Data Latch
Address Latch
16 x 16
W Register Array
3.3 Special MCU Features
A 17-bit by 17-bit single-cycle multiplier is shared by both
the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for special
operations, such as (-1.0) x (-1.0).
FIGURE 3-1: CPU CORE BLOCK DIAGRAM
The 16/16 and 32/16 divide operations are supported,
both fractional and integer. All divide instructions are
iterative operations. They must be executed within a
REPEAT loop, resulting in a total execution time of
19 instruction cycles. The divide operation can be
interrupted during any of those 19 cycles without loss of
data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
DS75018C-page 26 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
PC22
PC0
7
0
D0D15
Program Counter
Data Table Page Address
STATUS Register
Working Registers
DSP Operand
Registers
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
DSP Address
Registers
AD39 AD0AD31
DSP
Accumulators
ACCA
ACCB
7
0
Program Space Visibility Page Address
Z
0
OA OB SA SB
RCOUNT
15
0
REPEAT Loop Counter
DCOUNT
15
0
DO Loop Counter
DOSTART
22
0
DO Loop Start Address
IPL2 IPL1
SPLIM
Stack Pointer Limit Register
AD15
SRL
PUSH.S Shadow
DO Shadow
OAB SAB
15
0
Core Configuration Register
Legend
CORCON
DA DC
RA
N
TBLPAG
PSVPAG
IPL0 OV
W0/WREG
SRH
DO Loop End Address
DOEND
22
C
FIGURE 3-2: PROGRAMMER’S MODEL
2011-2012 Microchip Technology Inc. DS75018C-page 27
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
3.4 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER
R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0
OA OB SA
(1)
bit 15 bit 8
SB
(1)
OAB SAB
(1,4)
DA DC
R/W-0
(3)
IPL<2:0>
R/W-0
(3)
(2)
R/W-0
(3)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
RA N OV Z C
bit 7 bit 0
Legend:
C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Settable bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit
(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
(1,4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when
IPL3 = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
4: Clearing this bit will clear SA and SB.
DS75018C-page 28 2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
bit
(2,3)
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when
IPL3 = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
4: Clearing this bit will clear SA and SB.
2011-2012 Microchip Technology Inc. DS75018C-page 29
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0
— — —USEDT
(1)
DL<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0
SATA SATB SATDW ACCSAT IPL3
(2)
PSV RND IF
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15-13 Unimplemented: Read as ‘0’
bit 12 US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit
(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Note 1: This bit will always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS75018C-page 30 2011-2012 Microchip Technology Inc.
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