Datasheet dsPIC33EV64GM002, dsPIC33EV64GM102, dsPIC33EV128GM002, dsPIC33EV128GM102, dsPIC33EV256GM002 Datasheet

...

Download

dsPIC33EVXXXGM00X/10X FAMILY

16-Bit, 5V Digital Signal Controllers with

PWM, SENT, Op Amps and Advanced Analog Features

Operating Conditions

• 4.5V to 5.5V, -40°C to +85°C, DC to 70 MIPS

• 4.5V to 5.5V, -40°C to +125°C, DC to 60 MIPS

• 4.5V to 5.5V, -40°C to +150°C, DC to 40 MIPS

Core: 16-Bit dsPIC33E CPU

• Code-Efficient (C and Assembly) Architecture

• 16-Bit Wide Data Path

• Two 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL plus Hardware Divide

• 32-Bit Multiply Support

• Intermediate Security for Memory:

- Provides a Boot Flash Segment in addition to

the existing General Flash Segment

• Error Code Correction (ECC) for Flash

• Added Two Alternate Register Sets for Fast Context Switching

Clock Management

• Internal, 15% Low-Power RC (LPRC) – 32 kHz

• Internal, 1% Fast RC (FRC) – 7.37 MHz

• Internal, 10% Backup RC (BFRC) – 7.37 MHz

• Programmable PLLs and Oscillator Clock Sources

• Fail-Safe Clock Monitor (FSCM)

• Additional FSCM Source (BFRC), Intended to Provide a Clock Fail Switch Source for the System Clock

• Independent Watchdog Timer (WDT)

• System Windowed Watchdog Timer (DMT)

• Fast Wake-up and Start-up

Power Management

• Low-Power Management modes (Sleep, Idle and Doze)

• Power Consumption Minimized Executing NOP String

• Integrated Power-on Reset (POR) and Brown-out Reset (BOR)

• 0.5 mA/MHz Dynamic Current (typical)

• 50 µA at +25°C I

PD Current (typical)

PWM

• Up to Six Pulse-Width Modulation (PWM) Outputs (three generators)

• Primary Master Time Base Inputs allow Time Base Synchronization from Internal/External Sources

• Dead Time for Rising and Falling Edges

• 7.14 ns PWM Resolution

• PWM Support for:

- DC/DC, AC/DC, inverters, Power Factor

Correction (PFC) and lighting

- Brushless Direct Current (BLDC), Permanent

Magnet Synchronous Motor (PMSM), AC Induction Motor (ACIM), Switched Reluctance Motor (SRM)

- Programmable Fault inputs

- Flexible trigger configurations for

Analog-to-Digital conversion

- Supports PWM lock, PWM output chopping

and dynamic phase shifting

Advanced Analog Features

• ADC module:

- Configurable as 10-bit, 1.1 Msps with

four S&H or 12-bit, 500 ksps with one S&H

- Up to 36 analog inputs

• Flexible and Independent ADC Trigger Sources

• Up to Four Op Amp/Comparators with Direct Connection to the ADC module:

- Additional dedicated comparator and

7-bit Digital-to-Analog Converter (DAC)

- Two comparator voltage reference outputs

- Programmable references with 128 voltage

points

- Programmable blanking and filtering

• Charge Time Measurement Unit (CTMU):

- Supports mTouch™ capacitive touch sensing

- Provides high-resolution time

measurement (1 ns)

- On-chip temperature measurement

- Temperature sensor diode

- Nine sources of edge input triggers (CTED1,

CTED2, OCPWM, TMR1, SYSCLK, OSCLK, FRC, BFRC and LPRC)

 2013-2014 Microchip Technology Inc. DS70005144C-page 1

dsPIC33EVXXXGM00X/10X FAMILY

Timers/Output Compare/Input Capture

• Nine General Purpose Timers:

- Five 16-bit and up to two 32-bit timers/counters; Timer3 can provide ADC trigger

• Four Output Capture modules Configurable as Timers/Counters

• Four Input Capture modules

Communication Interfaces

• Two Enhanced Addressable Universal Asynchronous Receiver/Transmitter (UART) modules (6.25 Mbps):

- With support for LIN/J2602 bus support and

IrDA

- High and low speed (SCI)

• Two SPI modules (15 Mbps):

- 25 Mbps data rate without using PPS

•One I

• Two SENT J2716 (Single-Edge Nibble

• One CAN module:

C™ module (up to 1 Mbaud) with SMBus

Support

Transmission-Transmit/Receive) module for Automotive Applications

- 32 buffers, 16 filters and three masks

Direct Memory Access (DMA)

• 4-Channel DMA with User-Selectable Priority Arbitration

• UART, Serial Peripheral Interface (SPI), ADC, Input Capture, Output Compare and Controller Area Network (CAN)

Input/Output

• GPI/O Registers to Support Selectable Slew Rate I/O

• Peripheral Pin Select (PPS) to allow Function Remap

• Sink/Source: 8 mA or 12 mA, Pin-Specific for Standard V

• Selectable Open-Drain, Pull-ups and Pull-Downs

• Change Notice Interrupts on All I/O Pins

OH/VOL

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1: -40°C to +125°C) Completed

• AEC-Q100 REVG (Grade 0: -40°C to +150°C) Planned

• Class B Safety Library, IEC 60730

Class B Fault Handling Support

• Backup FRC

• Windowed WDT uses LPRC

• Windowed Deadman Timer (DMT) uses System Clock (System Windowed Watchdog Timer)

• H/W Clock Monitor Circuit

• Oscillator Frequency Monitoring through CTMU (OSCI, SYSCLK, FRC, BFRC, LPRC)

• Dedicated PWM Fault Pin

• Lockable Clock Configuration

Debugger Development Support

• In-Circuit and In-Application Programming

• Three Complex and Five Simple Breakpoints

• Trace and Run-Time Watch

DS70005144C-page 2  2013-2014 Microchip Technology Inc.

 2013-2014 Microchip Technology Inc. DS70005144C-page 3

dsPIC33EVXXXGM00X/10X PRODUCT FAMILIES

The device names, pin counts, memory sizes and peripheral availability of each device are listed in Tab le 1. The following pages show the devices’ pinout diagrams.

TABLE 1: dsPIC33EVXXXGM00X/10X FAMILY DEVICES

Device

SRAM Bytes

Program Memory Bytes

dsPIC33EV64GM002

dsPIC33EV64GM102 1

dsPIC33EV128GM002

dsPIC33EV128GM102 1

dsPIC33EV256GM002

dsPIC33EV256GM102 1

dsPIC33EV64GM004

dsPIC33EV64GM104 1

dsPIC33EV128GM004

dsPIC33EV128GM104 1

dsPIC33EV256GM004

dsPIC33EV256GM104 1

dsPIC33EV64GM006

dsPIC33EV64GM106 1

dsPIC33EV128GM006

dsPIC33EV128GM106 1

dsPIC33EV256GM006

dsPIC33EV256GM106 1

64K 8K

128K 8K

256K 16K

64K 8K

128K 8K

256K 16K

64K 8K

128K 8K

256K 16K

C™

SPI

CAN

32-Bit Timers

DMA Channels

16-Bit Timers (T1)

452443x222121113/41IntermediateY21328

452443x222121244/51IntermediateY35344 TQFP, QFN

452443x222121364/51IntermediateY53364 TQFP, QFN

Input Capture

PWM

UART

Output Compare

SENT

10/12-Bit ADC

ADC Inputs

CTMU

Op Amp/Comparators

Security

Peripheral Pin Select (PPS)

General Purpose I/O (GPIO)

Pins

External Interrupts

SPDIP, SOIC,

Packages

dsPIC33EVXXXGM00X/10X FAMILY

QFN-S

dsPIC33EVXXXGM00X/10X FAMILY

28-Pin SPDIP/SOIC

(1,2,3)

MCLR

AVDD

AVSS

RPI47/PWM1L1/T5CK/RB15

PGED3/OA2IN-/AN2/C2IN1-/SS1

/RPI32/CTED2/RB0

RPI46/PWM1H1/T3CK/RB14

PGEC3/OA1OUT/A N3/C1IN4-/C4IN2-/ RPI33/CTED1/RB1

RPI45/PWM1L2/CTPLS/RB13

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

RPI44/PWM1H2/RB12

PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3

RP43/PWM1L3/RB11

RP42/PWM1H3/RB10

OSC1/CLKI/AN32/RPI18/RA2 V

CAP

OSC2/CLKO/RPI19/RA3

FLT32/RP36/RB4

OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9

OA5IN+/AN24/C5IN3-/C5IN1+/C4IN1+/RP20/T1CK/RA4 AN26/CV

REF1O/CVREF2O/ASCL1/SDO1/RP40/T4CK/RB8

OA5OUT/AN25/C5IN4-/SCK1/RP39/INT0/RB7

PGED2/SDA1/RP37/RB5 PGEC2/SCL1/RP38/RB6

OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0

OA2IN+/AN1/C2IN1+/RPI17/RA1

dsPIC33EV128GM002/102

dsPIC33EV64GM002/102

dsPIC33EV256GM002/102

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral

Pin Select (PPS)” for available peripherals and information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O

Ports” for more information.

3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is

used.

Pin Diagrams

DS70005144C-page 4  2013-2014 Microchip Technology Inc.

Pin Diagrams (Continued)

28-Pin QFN-S

(1,2,3,4)

dsPIC33EV 64GM002/102 dsPIC33EV 128GM002/102 dsPIC33EV256GM002/102

28 27 26 25 24 23 22

10 11 12 13 14

OA5OUT/AN25/C5IN4-/SCK1/RP39/INT0/RB7

PGEC2/SCL1/RP38/RB6

PGED2/SDA1/RP37/RB5

OA 5 IN+/AN24/C5IN3-/C5 IN1+/C4IN1+/RP20/T1CK/RA4

FLT32/RP36/RB4

RPI45/PWM1L2/CTPLS/RB13

RPI44/PWM1H2/RB12

RP43/PWM1L3/RB11

RP42/PWM1H3/RB10

CAP

VSS

OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9

RPI46/PWM1H1/T3CK/RB14

RPI47/PWM1L1/T5CK/RB15

AVSSAVDD

MCLR

PGED3/OA2IN-/AN2/C21N1-/SS1/RPI32/CTED2/RB0

PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

OSC1/CLKI/AN32/RPI18/RA2

OSC2/CLKO/RPI19/RA3

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3

OA2OUT/AN0/C2IN4-/ C4IN3-/RPI16/RA0

OA2IN+/AN1/C2IN1+/RPI17/RA1

AN26/CVREF1O/CVREF2O/ASCL1/SDO1/RP40/T4CK/RB8

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral

Pin Select (PPS)” for available peripherals and information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O

Ports” for more information.

3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is

used.

4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to

SS externally.

dsPIC33EVXXXGM00X/10X FAMILY

 2013-2014 Microchip Technology Inc. DS70005144C-page 5

dsPIC33EVXXXGM00X/10X FAMILY

AN26/CV

REF1O

/ASCL1/RP40/T4CK/RB8

AN56/RA10

RPI45/PWM1L2/CTPLS/RB13

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3

OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0

OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1

OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS

/BCLK1/FLT3/RC2

OSC1/CLKI/AN32/RPI18/RA2

OSC2/CLKO/RPI19/RA3

RPI24/RA8

FLT32/RP36/RB4

AN55/RA7

RPI46/PWM1H1/T3CK/RB14

RPI47/PWM1L1/T5CK/RB15

MCLR

OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0

OA2IN+/AN1/C2IN1+/RPI17/RA1

PGED3/OA2IN-/AN2/C2IN1-/SS1

/RPI32/CTED2/RB0

PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

RPI44/PWM1H2/RB12

RP43/PWM1L3/RB11

RP42/PWM1H3/RB10

CAP

AN54/RP57/RC9

AN51/RP56/RC8

AN52/RP55/RC7

AN53/RP54/RC6

OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9

OA5OUT/AN25/C5IN4-/RP39/INT0/RB7

PGEC2/SCL1/RP38/RB6

PGED2/SDA1/RP37/RB5

VDDVSSAN31/CV

REF2O

/RPI53/RC5

AN30/CV

REF

+/RPI52/RC4

AN29/SCK1/RPI51/RC3

AN28/SDI1/RPI25/RA9

OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4

1213141516171819202122

4443424140393837363534

dsPIC33EV64GM004/104 dsPIC33EV128GM004/104 dsPIC33EV256GM004/104

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral

Pin Select (PPS)” for available peripherals and information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O

Ports” for more information.

3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is

used.

44-Pin TQFP

(1,2,3)

Pin Diagrams (Continued)

DS70005144C-page 6  2013-2014 Microchip Technology Inc.

Pin Diagrams (Continued)

dsPIC33EV64GM004/104 dsPIC33EV128GM004/104 dsPIC33EV256GM004/104

43 42 41 40 39 38 37 36 35

12 13 14 15 16 17 18 19 20 21

AN26/CV

REF1O

/ASCL1/RP40/T4CK/RB8AN56/RA10

RPI45/PWM1L2/CTPLS/RB13

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

PGED1/OA1IN-/ AN5/C1IN1-/CTMUC/RP35/RB3

OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0

OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1

OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS

/BCLK1/FLT3/RC2

OSC1/CLKI/AN32/RPI18/RA2

OSC2/CLKO/RPI19/RA3

RPI24/RA8

FLT32/RP36/RB4

AN55/RA7

RPI46/PWM1H1/T3CK/RB14

RPI47/PWM1L1/T5CK/RB15

MCLR

OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0

OA2IN+/AN1/C2I N1+/RPI17/RA1

PGED3/OA2IN-/AN2/C2IN1-/SS1

/RPI32/CTE D2/RB0

PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

RPI44/PWM1H2/RB12

RP43/PWM1L3/RB11

RP42/PWM1H3/RB10

CAP

AN54/RP57/RC9

AN51/RP56/RC8

AN52/RP55/RC7

AN53/RP54/RC6

OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9

OA5OUT/AN25/C5IN4-/RP39/INT0/RB7

PGEC2/SCL1/RP38/RB6

PGED2/SDA1/RP37/RB5

VDDVSSAN31/CV

REF2O

/RPI53/RC5

AN30/CV

REF

+/RPI52/RC4

AN29/SCK1/RPI 51/RC3

AN28/SDI1/RPI25/RA9

OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4

44-Pin QFN

(1,2,3,4)

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral

Pin Select (PPS)” for available peripherals and information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O

Ports” for more information.

3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is

used.

4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to

SS externally.

dsPIC33EVXXXGM00X/10X FAMILY

 2013-2014 Microchip Technology Inc. DS70005144C-page 7

dsPIC33EVXXXGM00X/10X FAMILY

64-Pin TQFP

(1,2,3)

AN55/RA7

RPI46/PWM1H1/T3CK/RB14

RPI47/PWM1L1/T5CK/RB15

AN19/RP118/RG6

AN18/RPI119/RG7

AN17/RP120/RG8

MCLR

AN16/RPI121/RG9

AN10/RPI28/RA12

AN9/RPI27/RA11

OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0

OA2IN+/AN1/C2IN1+/RPI17/ RA1

PGED3/OA2IN-/AN2/C2IN1-/

SS1/RPI32/CTED2/RB0

PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

AN56/RA10

RPI45/PWM1L2/CTPLS/RB13

RPI44/PWM1H2/RB12

RP43/PWM1L3/RB11

RP42/PWM1H3/RB10

RP97/RF1

RPI96/RF0

VDDV

CAP

AN54/RP57/RC9

RP70/RD6

RP69/RD5

AN51/RP56/RC8

AN52/RP55/RC7

AN53/RP54/RC6

OA5IN-/AN27//C5IN1-/ASDA1/RP41/RB9

AN26/CV

REF1O

/ASCL1/RP40/T4CK/RB8

RPI61/RC13 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7 AN48/CV

REF2O

/RPI58/RC10

PGEC2/SCL1/RP38/RB6 PGED2/SDA1/RP37/RB5 RPI72/RD8 V

OSC2/CLKO/RPI63/RC15 OSC1/CLKI/AN49/RPI60/ RC12 V

AN31/RPI53/RC5 AN30/CV

REF

+/RPI52/RC4

AN29/SCK1/ RPI51/RC3 AN28/SDI1/RPI25/RA9 OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

PGED1/OA1IN- /AN5/C1IN1-/(CTMUC)/RP35/RB3

OA3OUT/AN6/C3I N4-/C4IN4-/C4IN1+/RP48/RC0

OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1

OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/

U1RTS/BCLK1/FLT3/RC2

AN11/C1IN2-/

U1CTS/FLT4/RC11

AN12/C2IN2-/C5IN2-/

U2RTS/BCLK2/FLT5/RE12

AN13/C3IN2-/

U2CTS/FLT6/RE13

AN14/RPI94/

FLT7/RE14

AN15/RPI95/

FLT8/RE15

RPI24/RA8

FLT32

/RP36/RB4

dsPIC33EV64GM006/106 dsPIC33EV128GM006/106 dsPIC33EV256GM006/106

646362616059585756

5453525150

171819202122232425262728293031

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral

Pin Select (PPS)” for available peripherals and information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O

Ports” for more information.

3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is

used.

Pin Diagrams (Continued)

DS70005144C-page 8  2013-2014 Microchip Technology Inc.

Pin Diagrams (Continued)

64-Pin QFN

(1,2,3,4)

dsPIC33EV64GM006/106 dsPIC33EV128GM006/106 dsPIC33EV256GM006/106

646362616059585756555453525150

171819202122232425262728293031

AN56/RA10

RPI45/PWM1L2/CTPLS/RB13

RPI44/PWM1H2/RB12

RP43/PWM1L3/RB11

RP42/PWM1 H3/RB10

RP97/RF1

RPI96/RF0

VDDV

CAP

AN54/RP57/RC9

RP70/RD6

RP69/RD5

AN51/RP56/RC8

AN52/RP55/RC7

AN53/RP54/RC6

OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9

AN26/CV

REF1O

/ASCL1/RP40/T4CK/RB8

RPI61/RC13 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7 AN48/CV

REF2O

/RPI58/RC10

PGEC2/SCL1/RP38/RB6 PGED2/SDA1/RP37/ RB5 RPI72/RD8 V

OSC2/CLKO/RPI63/RC15 OSC1/CLKI/AN49/RPI60/RC12 V

AN31/RPI53/RC5 AN30/CV

REF

+/RPI52/RC4

AN29/SCK1/RPI51/RC3 AN28/SDI1/RPI25/RA9 OA5

IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RB3

OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0

OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1

OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS

/BCLK1/FLT3/RC2

AN11/C1IN2-/U1CTS

/FLT4/RC11

AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/RE12

AN13/C3IN2-/U2CTS

/FLT6/RE13

AN14/RPI94/FLT7/RE14

AN15/RPI95/FLT8/RE15

RPI24/RA8

FLT32/RP36/RB4

AN55/RA7

RPI46/PWM1H1/T3CK/RB14

RPI47/PWM1L1/T5CK/RB15

AN19/RP118/RG6

AN18/RPI119/RG7

AN17/RP120/RG8

MCLR

AN16/RPI121/RG9

AN10/RPI28/RA12

AN9/RPI27/RA11

OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0

OA2IN+/AN1/C2IN1+/RPI17/RA1

PGED3/OA2IN-/AN2/C2IN1-/

SS1/RPI32/CTED2/RB0

PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral

Pin Select (PPS)” for available peripherals and information on limitations.

2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O

Ports” for more information.

3: If the op amp is selected when OPAEN (CMxCON<10>) = 1, the OAx input is used; otherwise, the ANx input is

used.

4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to

SS externally.

dsPIC33EVXXXGM00X/10X FAMILY

 2013-2014 Microchip Technology Inc. DS70005144C-page 9

dsPIC33EVXXXGM00X/10X FAMILY

Table of Contents

dsPIC33EVXXXGM00X/10X Product Families ...................................................................................................................................... 3

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 17

3.0 CPU............................................................................................................................................................................................ 21

4.0 Memory Organization ................................................................................................................................................................. 31

5.0 Flash Program Memory.............................................................................................................................................................. 81

6.0 Resets ....................................................................................................................................................................................... 89

7.0 Interrupt Controller ..................................................................................................................................................................... 93

8.0 Direct Memory Access (DMA) .................................................................................................................................................. 107

9.0 Oscillator Configuration............................................................................................................................................................ 121

10.0 Power-Saving Features............................................................................................................................................................ 131

11.0 I/O Ports ................................................................................................................................................................................... 141

12.0 Timer1 ...................................................................................................................................................................................... 171

13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 173

14.0 Deadman Timer (DMT) ............................................................................................................................................................ 179

15.0 Input Capture............................................................................................................................................................................ 187

16.0 Output Compare....................................................................................................................................................................... 191

17.0 High-Speed PWM Module ....................................................................................................................................................... 197

18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 219

19.0 Inter-Integrated Circuit™ (I

20.0 Single-Edge Nibble Transmission (SENT) ............................................................................................................................... 235

21.0 Universal Asynchronous Receiver Transmitter (UART) .......................................................................................................... 245

22.0 Controller Area Network (CAN) Module (dsPIC33EVXXXGM10X Devices Only).................................................................... 251

23.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 277

24.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 283

25.0 Op Amp/Comparator Module ................................................................................................................................................... 299

26.0 Comparator Voltage Reference ................................................................................................................................................ 311

27.0 Special Features ...................................................................................................................................................................... 315

28.0 Instruction Set Summary .......................................................................................................................................................... 325

29.0 Development Support............................................................................................................................................................... 335

30.0 Electrical Characteristics .......................................................................................................................................................... 339

31.0 High-Temperature Electrical Characteristics............................................................................................................................ 401

32.0 Packaging Information.............................................................................................................................................................. 411

Appendix A: Revision History............................................................................................................................................................. 431

Index ................................................................................................................................................................................................. 433

The Microchip Web Site..................................................................................................................................................................... 439

Customer Change Notification Service .............................................................................................................................................. 439

Customer Support .............................................................................................................................................................................. 439

Product Identification System............................................................................................................................................................. 441

C™).............................................................................................................................................. 227

DS70005144C-page 10  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

 2013-2014 Microchip Technology Inc. DS70005144C-page 11

dsPIC33EVXXXGM00X/10X FAMILY

Referenced Sources

This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Reference Manual”, which are available from the Microchip web site (www.microchip.com). The follow- ing documents should be considered as the general reference for the operation of a particular module or device feature:

• “Introduction” (DS70573)

• “CPU” (DS70359)

• “Data Memory” (DS70595)

• “Program Memory” (DS70613)

• “Flash Programming” (DS70609)

• “Interrupts” (DS70000600)

• “Oscillator” (DS70580)

• “Reset” (DS70602)

• “Watchdog Timer and Power-Saving Modes” (DS70615)

• “I/O Ports” (DS70000598)

• “Timers” (DS70362)

• “CodeGuard™ Intermediate Security” (DS70005182)

• “Deadman Timer (DMT)” (DS70005155)

• “Input Capture” (DS70000352)

• “Output Compare” (DS70005157)

• “High-Speed PWM”(DS70645)

• “Analog-to-Digital Converter (ADC)” (DS70621)

• “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)

• “Serial Peripheral Interface (SPI)” (DS70005185)

• “Inter-Integrated Circuit™ (I

• “Enhanced Controller Area Network (ECAN™)”(DS70353)

• “Direct Memory Access (DMA)” (DS70348)

• “Programming and Diagnostics” (DS70608)

• “Op Amp/Comparator” (DS70000357)

• “Device Configuration” (DS70000618)

• “Charge Time Measurement Unit (CTMU)” (DS70661)

• “Single-Edge Nibble Transmission (SENT) Module” (DS70005145)

C™)” (DS70000195)

DS70005144C-page 12  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

PORTA

Power-up

Timer

Oscillator

Start-up

OSC1/CLKI

MCLR

VDD, VSS

UART1/2

Timing

Generation

CAN1

(1)

I2C1

ADC

Timers

Input

Capture

Output

Compare

DD, AVSS

SPI1/2

Watchdog

Timer/

POR/BOR

PWM

Remappable

Pins

Note 1: This feature or peripheral is only available on dsPIC33EVXXXGM10X devices.

CTMU

SENT1/2

CPU

Refer to Figure 3-1 for CPU diagram details.

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

PORTS

Peripheral Modules

Timer

Deadman

Op Amp/

Comparator

Timer

1.0 DEVICE OVERVIEW

This document contains device-specific information for the dsPIC33EVXXXGM00X/10X family Digital Signal

Note 1: This data sheet summarizes the features

of the dsPIC33EVXXXGM00X/10X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the

“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip

Controller (DSC) devices.

dsPIC33EVXXXGM00X/10X family devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit MCU architecture.

Figure 1-1 shows a general block diagram of the core

and peripheral modules. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register and bit information.

FIGURE 1-1: dsPIC33EVXXXGM00X/10X FAMILY BLOCK DIAGRAM

 2013-2014 Microchip Technology Inc. DS70005144C-page 13

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name

AN0-AN35 I Analog No Analog input channels.

CLKI

CLKO

OSC1

OSC2

REFCLKO O — Yes Reference clock output.

IC1-IC4 I ST Yes Capture Inputs 1 to 4.

OCFA OC1-OC4

INT0 INT1 INT2

RA0-RA4, RA7-RA12 I/O ST Yes PORTA is a bidirectional I/O port.

RB0-RB15 I/O ST Yes PORTB is a bidirectional I/O port.

RC0-RC13, RC15 I/O ST Yes PORTC is a bidirectional I/O port.

RD5-RD6, RD8 I/O ST Yes PORTD is a bidirectional I/O port.

RE12-RE15 I/O ST Yes PORTE is a bidirectional I/O port.

RF0-RF1 I/O ST No PORTF is a bidirectional I/O port.

RG6-RG9 I/O ST Yes PORTG is a bidirectional I/O port.

T1CK T2CK T3CK T4CK T5CK

CTPLS CTED1 CTED2

U1CTS U1RTS U1RX U1TX

U2CTS U2RTS U2RX U2TX

SCK1 SDI1 SDO1 SS1

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer

Typ e

I/O

I I I

I I I I I

I I

I/O

Buffer

Typ e

ST/

CMOS

—

ST/

CMOS

—

ST—Yes

ST ST ST

ST ST ST ST ST

ST ST ST

—

ST ST

—

PPS Description

NoNoExternal clock source input. Always associated with OSC1 pin

function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

NoNoOscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

Compare Fault A input (for compare channels).

Yes

Compare Outputs 1 to 4.

External Interrupt 0.

Yes

External Interrupt 1.

Yes

External Interrupt 2.

Timer1 external clock input.

Yes

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

CTMU pulse output.

CTMU External Edge Input 1.

CTMU External Edge Input 2.

Yes

UART1 Clear-to-Send.

Yes

UART1 Ready-to-Send.

Yes

UART1 receive.

Yes

UART1 transmit.

Yes

UART2 Clear-to-Send.

Yes

UART2 Ready-to-Send.

Yes

UART2 receive.

Yes

UART2 transmit.

Synchronous serial clock input/output for SPI1.

SPI1 data in.

SPI1 data out.

SPI1 slave synchronization or frame pulse I/O.

DS70005144C-page 14  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Typ e

Buffer

Typ e

PPS Description

SCK2 SDI2 SDO2 SS2

SCL1 SDA1 ASCL1 ASDA1

C1RX C1TX

SENT1TX SENT1RX SENT2TX SENT2RX

REF O Analog No Comparator Voltage Reference output.

C1IN1+, C1IN2-, C1IN1-, C1IN3- C1OUT

C2IN1+, C2IN2-, C2IN1-, C2IN3C2OUT

C3IN1+, C3IN2-, C2IN1-, C3IN3C3OUT

C4IN1+, C4IN2-, C4IN1-, C4IN3C4OUT

C5IN1+, C5IN2-, C5IN1-, C5IN3C5OUT

FLT1-FLT2 FLT3-FLT8 FLT32 DTCMP1-DTCMP3 PWM1L-PWM3L PWM1H-PWM3H SYNCI1 SYNCO1

PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3

MCLR

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer

I/O

I/O I/O I/O I/O

I/O

I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the

Yes

O O

—

Yes

ST ST ST ST

ST—Yes

—

— —

—

IOAnalog—No

— —

—

ST ST

No No No No

Yes

Yes Yes Yes Yes

Yes

Yes NO NO Yes

No Yes Yes

Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1.

CAN1 bus receive pin. CAN1 bus transmit pin.

SENT1 transmit pin. SENT1 receive pin. SENT2 transmit pin. SENT2 receive pin.

Comparator 1 inputs.

Comparator 1 output.

Comparator 2 inputs.

Comparator 2 output.

Comparator 3 inputs.

Comparator 3 output.

Comparator 4 inputs.

Comparator 4 output.

Comparator 5 inputs.

Comparator 5 output.

PWM Fault Inputs 1 and 2. PWM Fault Inputs 3 to 8. PWM Fault Input 32. PWM dead-time compensation input. PWM Low Outputs 1 to 3. PWM High Outputs 1 to 3. PWM Synchronization Input 1. PWM Synchronization Output 1.

Data I/O pin for Programming/Debugging Communication Channel 1. Clock input pin for Programming/Debugging Communication Channel 1. Data I/O pin for Programming/Debugging Communication Channel 2. Clock input pin for Programming/Debugging Communication Channel 2. Data I/O pin for Programming/Debugging Communication Channel 3. Clock input pin for Programming/Debugging Communication Channel 3.

device.

 2013-2014 Microchip Technology Inc. DS70005144C-page 15

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

AVDD P P No Positive supply for analog modules. This pin must be connected at all

SS P P No Ground reference for analog modules.

VDD P — No Positive supply for peripheral logic and I/O pins.

VCAP P — No CPU logic filter capacitor connection.

SS P — No Ground reference for logic and I/O pins.

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input PPS = Peripheral Pin Select TTL = TTL input buffer

Typ e

Buffer

Typ e

PPS Description

times.

DS70005144C-page 16  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

Note 1: This data sheet summarizes the features

of the dsPIC33EVXXXGM00X/10X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the

“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip

web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

2.1 Basic Connection Requirements

Getting started with the dsPIC33EVXXXGM00X/10X family of 16-bit microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

DD and VSS pins

•All V

(see Section 2.2 “Decoupling Capacitors”)

•All AV

•V

•MCLR

• PGECx/PGEDx pins used for In-Circuit Serial

• OSC1 and OSC2 pins when external oscillator

DD and AVSS pins (regardless if ADC module

is not used) (see Section 2.2 “Decoupling Capacitors”)

CAP

(see Section 2.3 “CPU Logic Filter Capacitor

Connection (VCAP)”)

(see Section 2.4 “Master Clear (MCLR) Pin”)

Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”)

source is used (see Section 2.6 “External Oscillator Pins”)

2.2 Decoupling Capacitors

The use of decoupling capacitors on every pair of power supply pins, such as V

SS, is required.

Consider the following criteria when using decoupling capacitors:

• Value and type of capacitor: A value of 0.1 µF (100 nF), 10V-20V is recommended. This capacitor should be a Low Equivalent Series Resistance (low-ESR), and have resonance frequency in the range of 20 MHz and higher. It is recommended to use ceramic capacitors.

• Placement on the Printed Circuit Board (PCB): The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

• Handling high-frequency noise: If the board is experiencing high-frequency noise, above tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF.

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing the PCB track inductance.

DD, VSS, AVDD and

Note: The AV

connected, regardless of the ADC voltage reference source.

 2013-2014 Microchip Technology Inc. DS70005144C-page 17

DD and AVSS pins must be

dsPIC33EVXXXGM00X/10X FAMILY

dsPIC33EV

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

MCLR

0.1 µF

Ceramic

VCAP

(1)

10 µF

Tantalum

Note 1: As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between V

DD and

DD to improve ADC noise rejection. The inductor

impedance should be less than 1 and the inductor capacity greater than 10 mA.

Where:

FCNV

--------------=

2 LC

------------- ----------=

2fC

----------------------





(i.e., ADC Conversion Rate/2)

Note 1: R  10 k is recommended. A suggested

starting value is 10 k. Ensure that the MCLR pin V

IH and VIL specifications are met.

2: R1  470 will limit any current flow into

MCLR

from the external capacitor, C, in the

event of MCLR

pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR

IH and VIL specifications are met.

(2)

(1)

VDD

MCLR

dsPIC33EV

FIGURE 2-1: RECOMMENDED

MINIMUM CONNECTION

The placement of this capacitor should be close to the

CAP pin. It is recommended that the trace length

V should not exceed one-quarter inch (6 mm).

2.4 Master Clear (MCLR) Pin

The MCLR pin provides two specific device functions:

• Device Reset

• Device Programming and Debugging

During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR specific voltage levels (V transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as shown in Figure 2-1, it is recommended that the capacitor, C, be isolated from the MCLR

pin during programming and debugging

operations.

Place the components as shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR

pin. Consequently,

IH and VIL) and fast signal

pin.

2.2.1 TANK CAPACITORS

On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF.

2.3 CPU Logic Filter Capacitor

A low-ESR (<1 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The V must have a capacitor greater than 4.7 µF (10 µF is recommended), with at least a 16V rating connected to the ground. The type can be ceramic or tantalum. See

Section 30.0 “Electrical Characteristics” for additional

information.

DS70005144C-page 18  2013-2014 Microchip Technology Inc.

Connection (V

CAP pin must not be connected to VDD, and

CAP)

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

dsPIC33EVXXXGM00X/10X FAMILY

Main Oscillator

Guard Ring

Guard Trace

Oscillator Pins

2.5 ICSP Pins

The PGECx and PGEDx pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not exceeding 100 Ohms.

Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin Voltage Input High

IH) and Voltage Input Low (VIL) requirements.

Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB REAL ICE™.

For more information on MPLAB ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site (www.microchip.com).

• “Using MPLAB

• “MPLAB® ICD 3 Design Advisory” (DS51764)

• “MPLAB® REAL ICE™ In-Circuit Emulator User’s

• “Using MPLAB

PICkit™ 3, MPLAB ICD 3 or MPLAB

ICD 3” (poster) (DS51765)

Guide” (DS51616)

(poster) (DS51749)

REAL ICE™ In-Circuit Emulator”

2.6 External Oscillator Pins

FIGURE 2-3: SUGGESTED PLACEMENT

OF THE OSCILLATOR CIRCUIT

2.7 Oscillator Value Conditions on Device Start-up

If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 5 MHz < F start-up conditions. This intends that, if the external oscillator frequency is outside this range, the application must start up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed.

Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLFBD, to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source.

Note: Clock switching must be enabled in the

IN < 13.6 MHz to comply with device PLL

device Configuration Word.

Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. For more information, see Section 9.0 “Oscillator Configuration”.

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed as shown in Figure 2-3.

 2013-2014 Microchip Technology Inc. DS70005144C-page 19

2.8 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic low state.

Alternatively, connect a 1k to 10k resistor between V and unused pins, and drive the output to logic low.

dsPIC33EVXXXGM00X/10X FAMILY

NOTES:

DS70005144C-page 20  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

3.0 CPU

Note 1: This data sheet summarizes the features

of the dsPIC33EVXXXGM00X/10X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “CPU” (DS70359) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.

The CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for digital signal processing. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space.

An instruction prefetch mechanism helps maintain throughput and provides predictable execution. Most instructions execute in a single-cycle effective execution rate, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction, PSV accesses and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

3.1 Registers

The dsPIC33EVXXXGM00X/10X family devices have sixteen, 16-bit Working registers in the programmer’s model. Each of the Working registers can act as a Data, Address or Address Offset register. The sixteenth Working register (W15) operates as a Software Stack Pointer for interrupts and calls.

In addition, the dsPIC33EVXXXGM00X/10X devices include two alternate Working register sets, which consist of W0 through W14. The alternate registers can be made persistent to help reduce the saving and restoring of register content during Interrupt Service Routines (ISRs). The alternate Working registers can be assigned to a specific Interrupt Priority Level (IPL1 through IPL6) by configuring the CTXTx<2:0> bits in the FALTREG Configuration register.

The alternate Working registers can also be accessed manually by using the CTXTSWP instruction.

The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT register can be used to identify the current, and most recent, manually selected Working register sets.

3.2 Instruction Set

The device instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many addressing modes and was designed for optimum C compiler efficiency.

3.3 Data Space Addressing

The Base Data Space can be addressed as 4K words or 8 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear Data Space. On dsPIC33EV devices, certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y Data Space boundary is device-specific.

The upper 32 Kbytes of the Data Space (DS) memory map can optionally be mapped into Program Space (PS) at any 16K program word boundary. The Program-toData Space mapping feature, known as Program Space Visibility (PSV), lets any instruction access Program Space as if it were Data Space. Moreover, the Base Data Space address is used in conjunction with a Data Space Read or Write Page register (DSRPAG or DSWPAG) to form an Extended Data Space (EDS) address. The EDS can be addressed as 8M words or 16 Mbytes. For more information on EDS, PSV and table accesses, refer to “Data Memory” (DS70595) and “Program Memory” (DS70613) in the “dsPIC33/PIC24 Family Reference Manual”.

On dsPIC33EV devices, overhead-free circular buffers (Modulo Addressing) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. The X AGU Circular Addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. Figure 3-1 illustrates the block diagram of the dsPIC33EVXXXGM00X/10X family devices.

3.4 Addressing Modes

The CPU supports these addressing modes:

• Inherent (no operand)

• Relative

•Literal

• Memory Direct

• Register Direct

• Register Indirect

Each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. As many as six addressing modes are supported for each instruction.

 2013-2014 Microchip Technology Inc. DS70005144C-page 21

dsPIC33EVXXXGM00X/10X FAMILY

PCH

Program Counter

16-Bit ALU

X Data Bus

PCU

Divide

Support

Engine

DSP

ROM Latch

Y Data Bus

EA MUX

X RAGU X WAGU

Y AGU

Interrupt

Controller

PSV and Table

Data Access Control Block

Stac k

Control

Logic

Loop

Control

Logic

Data LatchData Latch

Y Data

RAM

X Data

RAM

Address

Latch

Address

Latch

Data Latch

X Address Bus

Y Address Bus

Literal Data

Program Memory

Address Latch

Power, Reset

and Oscillator

Control Signals

to Various Blocks

Ports

Peripheral

Modules

PCL

16 x 16

W Register Array

Instruction

Decode and

Control

FIGURE 3-1: dsPIC33EVXXXGM00X/10X FAMILY CPU BLOCK DIAGRAM

DS70005144C-page 22  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

3.5 Programmer’s Model

The programmer’s model for the dsPIC33EVXXXGM00X/ 10X family is shown in Figure 3-2. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 3-1 lists a description of each register.

In addition to the registers contained in the programmer’s model, the dsPIC33EVXXXGM00X/10X family devices contain control registers for Modulo Addressing and Bit-Reversed Addressing, and interrupts. These registers are described in subsequent sections of this document.

All registers associated with the programmer’s model are memory-mapped, as shown in Table 4-1.

TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

W0 through W15

W0 through W14

ACCA, ACCB 40-Bit DSP Accumulators

PC 23-Bit Program Counter

SR ALU and DSP Engine STATUS Register

SPLIM Stack Pointer Limit Value Register

TBLPAG Table Memory Page Address Register

DSRPAG Extended Data Space (EDS) Read Page Register

RCOUNT REPEAT Loop Count Register

DCOUNT DO Loop Count Register

DOSTARTH

DOENDH, DOENDL DO Loop End Address Register (High and Low)

CORCON Contains DSP Engine, DO Loop Control and Trap Status bits

Note 1: Memory-mapped W0 through W14 represents the value of the register in the currently active CPU context.

2: The DOSTARTH and DOSTARTL registers are read-only.

(1)

(2)

, DOSTARTL

(2)

Working Register Array

Alternate Working Register Array 1

Alternate Working Register Array 2

DO Loop Start Address Register (High and Low)

 2013-2014 Microchip Technology Inc. DS70005144C-page 23

dsPIC33EVXXXGM00X/10X FAMILY

W10

W11

W12

W13

W14

D0D15

W10

W11

W12

W13

W14

NOVZ C

TBLPAG

PC23

PC0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Alternate Working/Address

DSP Operand Registers

W0 (WREG)

W10

W11

W12

W13

Frame Pointer/W14

Stack Pointer/W15

DSP Address Registers

AD39 AD0

AD31

DSP Accumulators

(1)

ACCA

ACCB

DSRPAG

OA OB SA SB

RCOUNT

REPEAT Loop Counter

15 0

DO Loop Counter and Stack

DOSTART

23 0

DO Loop Start Address and Stack

DOEND

DO Loop End Address and Stack

IPL2 IPL1

SPLIM

Stack Pointer Limit

AD15

SRL

IPL0

PUSH.s and POP.s Shadows

Nested

DO Stack

OAB SAB

X Data Space Read Page Address

CORCON

CPU Core Control Register

DCOUNT

D0D15

Registers

Working/Address Registers

FIGURE 3-2: PROGRAMMER’S MODEL

DS70005144C-page 24  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

3.6 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0

OA OB SA

(3)

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2

(1,2)

IPL1

(1,2)

IPL0

(1,2)

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit

1 = Accumulator A has overflowed 0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit

1 = Accumulator B has overflowed 0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit

1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit

1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulator A or B has overflowed 0 = Accumulator A and B have not overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

1 = Accumulator A or B is saturated or has been saturated at some time 0 = Accumulator A and B have not been saturated

bit 9 DA: DO Loop Active bit

1 = DO loop is in progress 0 = DO loop is not in progress

bit 8 DC: MCU ALU Half Carry/Borrow

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

(3)

OAB SAB DA DC

RA N OV Z C

(3)

bit

Note 1: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1.

2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1. 3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using the bit operations.

 2013-2014 Microchip Technology Inc. DS70005144C-page 25

dsPIC33EVXXXGM00X/10X FAMILY

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop is in progress 0 = REPEAT loop is not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = Overflow has not occurred for signed arithmetic

bit 1 Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

bit

(1,2)

Note 1: The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL3 = 1. User interrupts are disabled when IPL3 = 1.

2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1. 3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using the bit operations.

DS70005144C-page 26  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

REGISTER 3-2: CORCON: CORE CONTROL REGISTER

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0

(1)

(2)

DL2 DL1 DL0

SFA RND IF

VAR

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 VAR: Variable Exception Processing Latency Control bit

bit 14 Unimplemented: Read as ‘0’

bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits

bit 11 EDT: Early DO Loop Termination Control bit

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits

bit 7 SATA: ACCA Saturation Enable bit

bit 6 SATB: ACCB Saturation Enable bit

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit

bit 4 ACCSAT: Accumulator Saturation Mode Select bit

— US1 US0 EDT

1 = Variable exception processing latency is enabled 0 = Fixed exception processing latency is enabled

11 = Reserved 10 = DSP engine multiplies are mixed-sign 01 = DSP engine multiplies are unsigned 00 = DSP engine multiplies are signed

1 = Terminates executing DO loop at the end of current loop iteration 0 = No effect

111 = 7 DO loops are active

•

001 = 1 DO loop is active 000 = 0 DO loops are active

1 = Accumulator A saturation is enabled 0 = Accumulator A saturation is disabled

1 = Accumulator B saturation is enabled 0 = Accumulator B saturation is disabled

1 = Data Space write saturation is enabled 0 = Data Space write saturation is disabled

1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation)

Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

 2013-2014 Microchip Technology Inc. DS70005144C-page 27

dsPIC33EVXXXGM00X/10X FAMILY

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is less than 7

bit 2 SFA: Stack Frame Active Status bit

1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and

DSWPAG values

0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space

bit 1 RND: Rounding Mode Select bit

1 = Biased (conventional) rounding is enabled 0 = Unbiased (convergent) rounding is enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit

1 = Integer mode is enabled for DSP multiply 0 = Fractional mode is enabled for DSP multiply

Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

(2)

DS70005144C-page 28  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

REGISTER 3-3: CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — CCTXI2 CCTXI1 CCTXI0

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R-0 R/W-0 R/W-0

— — — — — MCTXI2 MCTXI1 MCTXI0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 CCTXI<2:0>: Current (W Register) Context Identifier bits

111 = Reserved

•

011 = Reserved 010 = Alternate Working Register Set 2 is currently in use 001 = Alternate Working Register Set 1 is currently in use 000 = Default register set is currently in use

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 MCTXI<2:0>: Manual (W Register) Context Identifier bits

111 = Reserved

•

011 = Reserved 010 = Alternate Working Register Set 2 was most recently manually selected 001 = Alternate Working Register Set 1 was most recently manually selected 000 = Default register set was most recently manually selected

 2013-2014 Microchip Technology Inc. DS70005144C-page 29

dsPIC33EVXXXGM00X/10X FAMILY

3.7 Arithmetic Logic Unit (ALU)

The dsPIC33EVXXXGM00X/10X family ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as

and Digit Borrow bits, respectively, for

Borrow subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. The data for the ALU operation can come from the W register array or from the data memory, depending on the addressing mode of the instruction. Similarly, the output data from the ALU can be written to the W register array or a data memory location.

For information on the SR bits affected by each instruction, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157).

The core CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division.

3.7.1 MULTIPLIER

Using the high-speed, 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit signed x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

3.8 DSP Engine

The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a 40-bit barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic).

The DSP engine can also perform inherent accumulatorto-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in the CPU Core Control register (CORCON) as follows:

• Fractional or Integer DSP Multiply (IF)

• Signed, Unsigned or Mixed-Sign DSP Multiply (US)

• Conventional or Convergent Rounding (RND)

• Automatic Saturation On/Off for ACCA (SATA)

• Automatic Saturation On/Off for ACCB (SATB)

• Automatic Saturation On/Off for Writes to Data Memory (SATDW)

• Accumulator Saturation mode Selection (ACCSAT)

TABLE 3-2: DSP INSTRUCTIONS

SUMMARY

Instruction

CLR A = 0 Yes

ED A = (x – y)

EDAC A = A + (x – y)

MAC A = A + (x • y) Yes

MAC A = A + x

MOVSAC No change in A Yes

MPY A = x • y No

MPY A = x

MPY.N A = – x • y No

MSC A = A – x • y Ye s

Algebraic Operation

ACC Write

Back

3.7.2 DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes:

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes the single-cycle per bit of the divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

DS70005144C-page 30  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

Reset Address

0x000000

0x000002

User Program Flash Memory

0x00AB80

0x00AB7E

(21696 instructions)

0x800000

DEVID

0xFEFFFE 0xFF0000

0xFFFFFE

Unimplemented

(Read ‘0’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

0x000200

0x0001FE

Interrupt Vector Table

Configuration Memory Space User Memory Space

Device Configuration

0x00AC00

0x00ABFE

Reserved

0xFF0002

Note 1: Memory areas are not shown to scale.

0xFF0004

Executive Code Memory

0x801000

0x800FFE

User OTP Memory

0xF9FFFE 0xFA0000

0xFA0002 0xFA0004

Write Latches

Reserved

0x800F80

Reserved

0x800BFE 0x800C00

4.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features of

the dsPIC33EVXXXGM00X/10X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Program Memory” (DS70613) in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).

The dsPIC33EVXXXGM00X/10X family architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the Data Space (DS) during code execution.

4.1 Program Address Space

The program address memory space of the dsPIC33EVXXXGM00X/10X family devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit PC, during program execution or from table operation, or from DS remapping, as described in Section 4.7 “Interfacing

Program and Data Memory Spaces”.

User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x02ABFF). The exception is the use of the TBLRD operations, which use TBLPAG<7> to read Device ID sections of the configuration memory space and the TBLWT operations, which are used to set up the write latches located in configuration memory space.

The program memory maps, which are presented by the device family and memory size, are shown in

Figure 4-1 through Figure 4-3.

FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EV64GM00X/10X DEVICES

(1)

 2013-2014 Microchip Technology Inc. DS70005144C-page 31

dsPIC33EVXXXGM00X/10X FAMILY

Reset Address

0x000000

0x000002

User Program Flash Memory

0x015780

0x01577E

(44736 instructions)

0x800000

0xFA0000

Write Latches

0xFA0002 0xFA0004

DEVID

0xFEFFFE 0xFF0000

0xFFFFFE

0xF9FFFE

Unimplemented

(Read ‘0’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

Interrupt Vector Table

Configuration Memory Space User Memory Space

0x015800

0x0157FE

Reserved

0xFF0002

Note 1: Memory areas are not shown to scale.

0xFF0004

Executive Code Memory

0x801000

0x800FFE

User OTP Memory

Device Configuration

0x800F80

Reserved

0x800BFE 0x800C00

FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EV128GM00X/10X DEVICES

(1)

DS70005144C-page 32  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

Reset Address

0x000000

0x000002

User Program Flash Memory

0x02AB80

0x02AB7E

(87232 instructions)

0x800000

0xFA0000

Write Latches

0xFA0002 0xFA0004

DEVID

0xFEFFFE 0xFF0000

0xFFFFFE

0xF9FFFE

Unimplemented

(Read ‘

’s)

GOTO Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

Interrupt Vector Table

Configuration Memory Space User Memory Space

0x02AC00

0x02ABFE

Reserved

0xFF0002

Note 1: Memory areas are not shown to scale.

0xFF0004

Executive Code Memory

0x801000

0x800FFE

User OTP Memory

0x800F80

Device Configuration

Reserved

0x800BFE 0x800C00

FIGURE 4-3: PROGRAM MEMORY MAP FOR dsPIC33EV256GM00X/10X DEVICES

(1)

 2013-2014 Microchip Technology Inc. DS70005144C-page 33

dsPIC33EVXXXGM00X/10X FAMILY

0816

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Least Significant WordMost Significant Word

Instruction Width

0x000001

0x000003

0x000005

0x000007

msw

Address (lsw Address)

4.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (see Figure 4-4).

Program memory addresses are always word-aligned on the lower word and addresses are incremented or decremented by two during the code execution. This

4.1.2 INTERRUPT AND TRAP VECTORS

All dsPIC33EVXXXGM00X/10X family devices reserve the addresses between 0x000000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at address, 0x000000 of Flash memory, with the actual address for the start of code at address, 0x000002 of Flash memory.

For more information on the Interrupt Vector Tables,

see Section 7.1 “Interrupt Vector Table”. arrangement provides compatibility with the Data Memory Space Addressing and makes data in the program memory space accessible.

FIGURE 4-4: PROGRAM MEMORY ORGANIZATION

DS70005144C-page 34  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

4.2 Data Address Space

The dsPIC33EVXXXGM00X/10X family CPU has a separate, 16-bit wide data memory space. The Data Space (DS) is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps, which are presented by device family and memory size, are shown in Figure 4-5 and

Figure 4-6.

All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the DS. This arrangement gives a Base Data Space address range of 64 Kbytes or 32K words.

The Base Data Space address is used in conjunction with a Data Space Read or Write Page register (DSRPAG or DSWPAG) to form an Extended Data Space (EDS), which has a total address range of 16 Mbytes.

dsPIC33EVXXXGM00X/10X family devices implement up to 20 Kbytes of data memory (4 Kbytes of data memory for Special Function Registers and up to 16 Kbytes of data memory for RAM). If an EA points to a location outside of this area, an all zero word or byte is returned.

4.2.1 DATA SPACE WIDTH

The data memory space is organized in byteaddressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all DS EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.

4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC devices and improve Data Space memory usage efficiency, the dsPIC33EVXXXGM00X/10X family instruction set supports both word and byte operations. As a consequence of byte accessibility, all the Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

A data byte read, reads the complete word that contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.

MCU

All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, therefore, care must be taken when mixing byte and word operations or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the LSB; the MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address.

4.2.3 SFR SPACE

The first 4 Kbytes of the Near Data Space, from 0x0000 to 0x0FFF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33EVXXXGM00X/10X family core and peripheral modules for controlling the operation of the device.

SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’.

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.

4.2.4 NEAR DATA SPACE

The 8-Kbyte area, between 0x0000 and 0x1FFF, is referred to as the Near Data Space. Locations in this space are directly addressable through a 13-bit absolute address field within all memory direct instructions. Additionally, the whole DS is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a Working register as an Address Pointer.

 2013-2014 Microchip Technology Inc. DS70005144C-page 35

dsPIC33EVXXXGM00X/10X FAMILY

0x0000

0x0FFE

0xFFFE

LSB

Address

16 Bits

LSBMSB

MSB

Address

0x0001

0x0FFF

0xFFFF

Optionally Mapped into Program Memory Space

0x2FFF 0x2FFE

0x1001

0x1000

4-Kbyte SFR Space

8-Kbyte SRAM Space

0x30000x3001

Space

Near Data

8-Kbyte

Note 1: Memory areas are not shown to scale.

(via PSV)

0x1FFE

0x1FFF

0x2001 0x2000

X Data

Unimplemented (X)

SFR Space

0x7FFF

0x7FFE 0x8000

0x8001

X Data RAM (X)

Y Data RAM (Y)

FIGURE 4-5: DATA MEMORY MAP FOR 64-KBYTE/128-KBYTE DEVICES

(1)

DS70005144C-page 36  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

0x0000

0x0FFE

0xFFFE

LSB

Address

16 Bits

LSBMSB

MSB

Address

0x0001

0x0FFF

0xFFFF

Optionally Mapped into Program Memory Space

0x4FFF 0x4FFE

0x1001

0x1000

4-Kbyte SFR Space

16-Kbyte SRAM Space

0x5000

0x5001

Space

Near Data

8-Kbyte

Note 1: Memory areas are not shown to scale.

(via PSV)

0x2FFE

0x2FFF

0x3001

0x3000

X Data

Unimplemented (X)

SFR Space

X Data RAM (X)

0x7FFF

0x7FFE 0x8000

0x8001

0x1FFE 0x2000

0x1FFF

0x2001

Y Data RAM (Y)

FIGURE 4-6: DATA MEMORY MAP FOR 256-KBYTE DEVICES

(1)

 2013-2014 Microchip Technology Inc. DS70005144C-page 37

dsPIC33EVXXXGM00X/10X FAMILY

4.2.5 X AND Y DATA SPACES

The dsPIC33EVXXXGM00X/10X family core has two Data Spaces: X and Y. These Data Spaces can be considered either separate (for some DSP instructions) or as one unified, linear address range (for MCU instructions). The Data Spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms, such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT).

The X DS is used by all instructions and supports all addressing modes. The X DS has separate read and write data buses. The X read data bus is the read data path for all instructions that view the DS as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class).

The Y DS is used in concert with the X DS by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths.

Both the X and Y Data Spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to the X Data Space.

All data memory writes, including in DSP instructions, view Data Space as combined X and Y address space. The boundary between the X and Y Data Spaces is device-dependent and is not user-programmable.

DS70005144C-page 38  2013-2014 Microchip Technology Inc.

 2013-2014 Microchip Technology Inc. DS70005144C-page 39

4.3 Special Function Register Maps

TABLE 4-1: CPU CORE REGISTER MAP

SFR

Name

W0 0000 W0 (WREG) 0000

W1 0002 W1 0000

W2 0004 W2 0000

W3 0006 W3 0000

W4 0008 W4 0000

W5 000A W5 0000

W6 000C W6 0000

W7 000E W7 0000

W8 0010 W8 0000

W9 0012 W9 0000

W10 0014 W10 0000

W11 0016 W11 0000

W12 0018 W12 0000

W13 001A W13 0000

W14 001C W14 0000

W15 001E W15 0800

SPLIM 0020 SPLIM xxxx

ACCAL 0022 ACCAL xxxx

ACCAH 0024 ACCAH xxxx

ACCAU 0026 Sign Extension of ACCA<39> ACCAU xxxx

ACCBL 0028 ACCBL xxxx

ACCBH 002A ACCBH xxxx

ACCBU 002C Sign Extension of ACCB<39> ACCBU xxxx

PCL 002E Program Counter Low Word Register

PCH 0030

DSRPAG 0032

DSWPAG 0034

RCOUNT 0036 REPEAT Loop Count Register 0 xxxx

DCOUNT 0038 DCOUNT<15:1> 0 xxxx

DOSTARTL 003A DOSTARTL<15:1> 0 xxxx

DOSTARTH 003C

DOENDL 003E DOENDL<15:1>

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — — — — — — — Program Counter High Word Register 0000

— — — — — — Data Space Read Page Register 0001

— — — — — — — Data Space Write Page Register 0001

— — — — — — — — — — DOSTARTH<5:0> 00xx

All

Resets

— 0000

— xxxx

dsPIC33EVXXXGM00X/10X FAMILY

DS70005144C-page 40  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)

SFR

Name

DOENDH 0040 — — — — — — — — — — DOENDH<5:0> 00xx

SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000

CORCON 0044 VAR

MODCON 0046 XMODEN YMODEN

XMODSRT 0048 XMODSRT<15:1> 0 xxxx

XMODEND 004A XMODEND<15:1> 1 xxxx

YMODSRT 004C YMODSRT<15:1> 0 xxxx

YMODEND 004E YMODEND<15:1> 1 xxxx

XBREV 0050 BREN XBREV14 XBREV13 XBREV12 XBREV11 XBREV10 XBREV9 XBREV8 XBREV7 XBREV6 XBREV5 XBREV4 XBREV3 XBREV2 XBREV1 XBREV0 8xxx

DISICNT 0052

TBLPAG 0054

MSTRPR 0058 MSTRPR<15:0> 0000

CTXTSTAT 005A

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— US1 US0 EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020

— — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000

— — DISICNT<13:0> xxxx

— — — — — — — — TBLPAG<7:0> 0000

— — — — — CCTXI2 CCTXI1 CCTXI0 — — — — — MCTXI2 MCTXI1 MCTXI0 0000

All

Resets

 2013-2014 Microchip Technology Inc. DS70005144C-page 41

TABLE 4-2: TIMERS REGISTER MAP

SFR

Name

TMR1 0100 Timer1 Register 0000

PR1 0102 Period Register 1 FFFF

T1CON 0104 TON

TMR2 0106 Timer2 Register 0000

TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) 0000

TMR3 010A Timer3 Register 0000

PR2 010C Period Register 2 FFFF

PR3 010E Period Register 3 FFFF

T2CON 0110 TON

T3CON 0112 TON

TMR4 0114 Timer4 Register 0000

TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) 0000

TMR5 0118 Timer5 Register 0000

PR4 011A Period Register 4 FFFF

PR5 011C Period Register 5 FFFF

T4CON 011E TON

T5CON 0120 TON

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS — 0000

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — —TCS — 0000

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 —TCS — 0000

—TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — —TCS — 0000

All

Resets

dsPIC33EVXXXGM00X/10X FAMILY

DS70005144C-page 42  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-3: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP

SFR

Name

IC1CON1 0140

IC1CON2 0142

IC1BUF 0144 Input Capture 1 Buffer Register xxxx

IC1TMR 0146 Input Capture 1 Timer Register 0000

IC2CON1 0148

IC2CON2 014A

IC2BUF 014C Input Capture 2 Buffer Register xxxx

IC2TMR 014E Input Capture 2 Timer Register 0000

IC3CON1 0150

IC3CON2 0152

IC3BUF 0154 Input Capture 3 Buffer Register xxxx

IC3TMR 0156 Input Capture 3 Timer Register 0000

IC4CON1 0158

IC4CON2 015A

IC4BUF 015C Input Capture 4 Buffer Register xxxx

IC4TMR 015E Input Capture 4 Timer Register 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

— — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D

— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

— — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D

— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

— — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D

— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000

— — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D

All

Resets

TABLE 4-4: I2C1 REGISTER MAP

SFR

Name

I2C1CON1 0200 I2C EN

I2C1CON2 0202

I2C1STAT 020 4 ACKSTAT TRSTAT ACKTIM

I2C1ADD 0206

I2C1MSK 0208

I2C1BRG 020A Baud Rate Generator Register 0000

I2C1TRN 020C

I2C1RCV 020E

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000

— — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 1000

— — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000

— — — — — — I2C1 Address Register 0000

— — — — — — I2C1 Address Mask Register 0000

— — — — — — — — I2C1 Transmit Register 00FF

— — — — — — — — I2C1 Receive Register 0000

All

Resets

 2013-2014 Microchip Technology Inc. DS70005144C-page 43

TABLE 4-5: UART1 AND UART2 REGISTER MAP

SFR

Name

U1MODE 0220 UARTEN

U1STA 0222 UTXISEL1 UTXINV UTXISEL0

U1TXREG 0224

U1RXREG 0226

U1BRG 0228 Baud Rate Generator Prescaler Register 0000

U2MODE 0230 UARTEN

U2STA 0232 UTXISEL1 UTXINV UTXISEL0

U2TXREG 0234

U2RXREG 0236

U2BRG 0238 Baud Rate Generator Prescaler Register 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

— — — — — — — UART1 Transmit Register xxxx

— — — — — — — UART1 Receive Register 0000

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

— — — — — — — UART2 Transmit Register xxxx

— — — — — — — UART2 Receive Register 0000

All

Resets

TABLE 4-6: SPI1 AND SPI2 REGISTER MAP

SFR

Name

SPI1STAT 0240 SPIEN

SPI1CON1 0242

SPI1CON2 0244 FRMEN SPIFSD FRMPOL

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000

SPI2STAT 0260 SPIEN

SPI2CON1 0262

SPI2CON2 0264 FRMEN SPIFSD FRMPOL

SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

— — — — — — — — — — — FRMDLY SPIBEN 0000

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

— — — — — — — — — — — FRMDLY SPIBEN 0000

All

Resets

dsPIC33EVXXXGM00X/10X FAMILY

DS70005144C-page 44  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-7: ADC1 REGISTER MAP

SFR

Name

ADC1BUF0 0300 ADC1 Data Buffer 0

ADC1BUF1 0302 ADC1 Data Buffer 1

ADC1BUF2 0304 ADC1 Data Buffer 2

ADC1BUF3 0306 ADC1 Data Buffer 3

ADC1BUF4 0308 ADC1 Data Buffer 4

ADC1BUF5 030A ADC1 Data Buffer 5

ADC1BUF6 030C ADC1 Data Buffer 6

ADC1BUF7 030E ADC1 Data Buffer 7

ADC1BUF8 0310 ADC1 Data Buffer 8

ADC1BUF9 0312 ADC1 Data Buffer 9

ADC1BUFA 0314 ADC1 Data Buffer 10

ADC1BUFB 0316 ADC1 Data Buffer 11

ADC1BUFC 0318 ADC1 Data Buffer 12

ADC1BUFD 031A ADC1 Data Buffer 13

ADC1BUFE 031C ADC1 Data Buffer 14

ADC1BUFF 031E ADC1 Data Buffer 15

AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM1 FORM0 SSRC2 SSRC1 SSRC0 SSRCG SIMSAM ASAM SAMP DONE

AD1CON2 0322 VCFG2 VCFG1 VCFG0 — — CSCNA CHPS1 CHPS0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS

AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0

AD1CHS123 0326 — — — CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0 — — — CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0

AD1CHS0 0328 CH0NB — CH0SB5 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — CH0SA5 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0

AD1CSSH 032E CSS<31:24> — — — — CSS<19:16>

AD1CSSL 0330 CSS<15:0>

AD1CON4 0332 — — — — — — — ADDMAEN — — — — — DMABL2 DMABL1 DMABL0

Legend:x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

xxxx

0000

TABLE 4-8: CTMU REGISTER MAP

SFR

Name

CTMUCON1 033A CTMUEN — CTMUSIDL TGEN E DGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — —

CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — —

CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — —

Legend:

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— = unimplemented, read as ‘0’. Reset val ues are shown i n hexadecimal.

All

Resets

0000

 2013-2014 Microchip Technology Inc. DS70005144C-page 45

TABLE 4-9: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 FOR dsPIC33EVXXXGM10X DEVICES

SFR

Name

C1CTRL1 0400 — — CSIDL ABAT CANCKS REQOP2 REQOP1 REQOP0 OPMODE2 OPMODE1 OPMODE0 —CANCAP— —WIN

C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0>

C1VEC 0404 — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 — ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0

C1FCTRL 0406 DMABS2 DMABS1 DMABS0 — — — — — — — FSA5 FSA4 FSA3 FSA2 FSA1 FSA0

C1FIFO 0408 — — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 — — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0

C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF

C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE

C1EC 040E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0

C1CFG1 0410 — — — — — — — — SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

C1CFG2 0412 —WAKFIL— — — SEG2PH2 SEG2PH1 SEG2PH0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0

C1FEN1 0414 FLTEN<15:0>

C1FMSKSEL1 0418 F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0 F3MSK1 F3MSK0 F2MSK1 F2MSK0 F1MSK1 F1MSK0 F0MSK1 F0MSK0

C1FMSKSEL2 041A F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK0 F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0

Legend:

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Resets

0480

0000

FFFF

0000

TABLE 4-10: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 FOR dsPIC33EVXXXGM10X DEVICES

SFR

Name

C1RXFUL1 0420 RXFUL<15:0> 0000

C1RXFUL2 0422 RXFUL<31:16> 0000

C1RXOVF1 0428 RXOVF<15:0> 0000

C1RXOVF2 042A RXOVF<31:16> 0000

C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI1 TX1PRI0 TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI1 TX0PRI0 0000

C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI1 TX3PRI0 TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI1 TX2PRI0 0000

C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI1 TX5PRI0 TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI1 TX4PRI0 0000

C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI1 TX7PRI0 TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI1 TX6PRI0 xxxx

C1RXD 0440 CAN1 Receive Data Word Register xxxx

C1TXD 0442 CAN1 Transmit Data Word Register xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0400041E

See definition when WIN = x

All

Resets

All

dsPIC33EVXXXGM00X/10X FAMILY

DS70005144C-page 46  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-11: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EVXXXGM10X DEVICES

SFR

Name

C1BUFPNT1 0420 F3BP3 F3BP2 F3BP1 F3BP0 F2BP3 F2BP2 F2BP1 F2BP0 F1BP3 F1BP2 F1BP1 F1BP0 F0BP3 F0BP2 F0BP1 F0BP0 0000

C1BUFPNT2 0422 F7BP3 F7BP2 F7BP1 F7BP0 F6BP3 F6BP2 F6BP1 F6BP0 F5BP3 F5BP2 F5BP1 F5BP0 F4BP3 F4BP2 F4BP1 F4BP0 0000

C1BUFPNT3 0424 F11BP3 F11BP2 F11BP1 F11BP0 F10BP3 F10BP2 F10BP1 F10BP0 F9BP3 F9BP2 F9BP1 F9BP0 F8BP3 F8BP2 F8BP1 F8BP0 0000

C1BUFPNT4 0426 F15BP3 F15BP2 F15BP1 F15BP0 F14BP3 F14BP2 F14BP1 F14BP0 F13BP3 F13BP2 F13BP1 F13BP0 F12BP3 F12BP2 F12BP1 F12BP0 0000

C1RXM0SID 0430 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXM0EID 0432 EID<15:0> xxxx

C1RXM1SID 0434 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXM1EID 0436 EID<15:0> xxxx

C1RXM2SID 0438 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXM2EID 043A EID<15:0> xxxx

C1RXF0SID 0440 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF0EID 0442 EID<15:0> xxxx

C1RXF1SID 0444 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF1EID 0446 EID<15:0> xxxx

C1RXF2SID 0448 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF2EID 044A EID<15:0> xxxx

C1RXF3SID 044C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF3EID 044E EID<15:0> xxxx

C1RXF4SID 0450 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF4EID 0452 EID<15:0> xxxx

C1RXF5SID 0454 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF5EID 0456 EID<15:0> xxxx

C1RXF6SID 0458 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF6EID 045A EID<15:0> xxxx

C1RXF7SID 045C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF7EID 045E EID<15:0> xxxx

C1RXF8SID 0460 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF8EID 0462 EID<15:0> xxxx

C1RXF9SID 0464 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF9EID 0466 EID<15:0> xxxx

C1RXF10SID 0468 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF10EID 046A EID<15:0> xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0400-

041E

See definition when WIN = x

—MIDE—EID17EID16xxxx

— EXIDE —EID17EID16xxxx

All

Resets

 2013-2014 Microchip Technology Inc. DS70005144C-page 47

TABLE 4-11: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EVXXXGM10X DEVICES (CONTINUED)

SFR

Name

C1RXF11SID 046C SID10 S ID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE —EID17EID16xxxx

C1RXF11EID 046E EID<15:0> xxxx

C1RXF12SID 0470 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF12EID 0472 EID<15:0> xxxx

C1RXF13SID 0474 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF13EID 0476 EID<15:0> xxxx

C1RXF14SID 0478 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF14EID 047A EID<15:0> xxxx

C1RXF15SID 047C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

C1RXF15EID 047E EID<15:0> xxxx

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— EXIDE —EID17EID16xxxx

All

Resets

TABLE 4-12: SENT1 RECEIVER REGISTER MAP

SFR

Name

SENT1CON1 0500 SNTEN

SENT1CON2 0504 TICKTIME<15:0> (Transmit modes) or SYNCMAX<15:0> (Receive mode) FFFF

SENT1CON3 0508 FRAMETIME<15:0> (Transmit modes) or SYNCMIN<15:0> (Receive mode) FFFF

SENT1STAT 050C

SENT1SYNC 0510 Synchronization Time Period Register (Transmit mode) 0000

SENT1DATL 0514 DATA4<3:0> DATA5<3:0> DATA6<3:0> CRC<3:0> 0000

SENT1DATH 0516 STAT<3:0> DATA1<3:0> DATA2<3:0> DATA3<3:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— SNTSIDL — RCVEN TXM TXPOL CRCEN PPP SPCEN —PS — NIBCNT2 NIBCNT1 NIBCNT0 0000

— — — — — — — — PAUSE NIB2 NIB1 NIB0 CRCERR FRMERR RXIDLE SYNCTXEN 0000

All

Resets

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-13: SENT2 RECEIVER REGISTER MAP

SFR

Name

SENT2CON1 0520 SNTEN

SENT2CON2 0524 TICKTIME<15:0> (Transmit modes) or SYNCMAX<15:0> (Receive mode) FFFF

SENT2CON3 0528 FRAMETIME<15:0> (Transmit modes) or SYNCMIN<15:0> (Receive mode) FFFF

SENT2STAT 052C

SENT2SYNC 0530 Synchronization Time Period Register (Transmit mode) 0000

SENT2DATL 0534 DATA4<3:0> DATA5<3:0> DATA6<3:0> CRC<3:0> 0000

SENT2DATH 0536 STAT<3:0> DATA1<3:0> DATA2<3:0> DATA3<3:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— SNTSIDL — RCVEN TXM TXPOL CRCEN PPP SPCEN —PS — NIBCNT2 NIBCNT1 NIBCNT0 0000

— — — — — — — — PAUSE NIB2 NIB1 NIB0 CRCERR FRMERR RXIDLE SYNCTXEN 0000

All

Resets

DS70005144C-page 48  2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X FAMILY

TABLE 4-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EVXXXGM002/102 DEVICES

SFR

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Name

RPOR0 0670

RPOR1 0672

RPOR2 0674

RPOR3 0676

RPOR4 0678

RPOR10 0684

RPOR11 0686

RPOR12 0688

RPOR13 068A

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000

— — RP37R5 RP37R4 RP37R3 RP37R2 RP37R1 RP37R0 — — RP36R5 RP36R4 RP36R3 RP36R2 RP36R1 RP36R0 0000

— — RP39R5 RP39R4 RP39R3 RP39R2 RP39R1 RP39R0 — — RP38R5 RP38R4 RP38R3 RP38R2 RP38R1 RP38R0 0000

— — RP41R5 RP41R4 RP41R3 RP41R2 RP41R1 RP41R0 — — RP40R5 RP40R4 RP40R3 RP40R2 RP40R1 RP40R0 0000

— — RP43R5 RP43R4 RP43R3 RP43R2 RP43R1 RP43R0 — — RP42R5 RP42R4 RP42R3 RP42R2 RP42R1 RP42R0 0000

— — RP176R5 RP176R4 RP176R3 RP176R2 RP176R1 RP176R0 — — — — — — — — 0000

— — RP178R5 RP178R4 RP178R3 RP178R2 RP178R1 RP178R0 — — RP177R5 RP177R4 RP177R3 RP177R2 RP177R1 RP177R0 0000

— — RP180R5 RP180R4 RP180R3 RP180R2 RP180R1 RP180R0 — — RP179R5 RP179R4 RP179R3 RP179R2 RP179R1 RP179R0 0000

— — — — — — — — — — RP181R5 RP181R4 RP181R3 RP181R2 RP181R1 RP181R0 0000

All

Resets

TABLE 4-15: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EVXXXGM004/104 DEVICES

SFR

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Name

RPOR0 0670 — — RP35R5 RP35R4 RP35R3 RP35R2 RP35R1 RP35R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000

RPOR1 0672

RPOR2 0674

RPOR3 0676

RPOR4 0678

RPOR5 067A

RPOR6 067C

RPOR7 067E

RPOR10 0684

RPOR11 0686

RPOR12 0688

RPOR13 068A

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — RP37R5 RP37R4 RP37R3 RP37R2 RP37R1 RP37R0 — — RP36R5 RP36R4 RP36R3 RP36R2 RP36R1 RP36R0 0000

— — RP39R5 RP39R4 RP39R3 RP39R2 RP39R1 RP39R0 — — RP38R5 RP38R4 RP38R3 RP38R2 RP38R1 RP38R0 0000

— — RP41R5 RP41R4 RP41R3 RP41R2 RP41R1 RP41R0 — — RP40R5 RP40R4 RP40R3 RP40R2 RP40R1 RP40R0 0000

— — RP43R5 RP43R4 RP43R3 RP43R2 RP43R1 RP43R0 — — RP42R5 RP42R4 RP42R3 RP42R2 RP42R1 RP42R0 0000

— — RP49R5 RP49R4 RP49R3 RP49R2 RP49R1 RP49R0 — — RP48R5 RP48R4 RP48R3 RP48R2 RP48R1 RP48R0 0000

— — RP55R5 RP55R4 RP55R3 RP55R2 RP55R1 RP55R0 — — RP54R5 RP54R4 RP54R3 RP54R2 RP54R1 RP54R0 0000

— — RP57R5 RP57R4 RP57R3 RP57R2 RP57R1 RP57R0 — — RP56R5 RP56R4 RP56R3 RP56R2 RP56R1 RP56R0 0000

— — RP176R5 RP176R4 RP176R3 RP176R2 RP176R1 RP176R0 — — — — — — — — 0000

— — RP178R5 RP178R4 RP178R3 RP178R2 RP178R1 RP178R0 — — RP177R5 RP177R4 RP177R3 RP177R2 RP177R1 RP177R0 0000

— — RP180R5 RP180R4 RP180R3 RP180R2 RP180R1 RP180R0 — — RP179R5 RP179R4 RP179R3 RP179R2 RP179R1 RP179R0 0000

— — — — — — — — — — RP181R5 RP181R4 RP181R3 RP181R2 RP181R1 RP181R0 0000

All

Resets

 2013-2014 Microchip Technology Inc. DS70005144C-page 49

TABLE 4-16: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EVXXXGM006/106 DEVICES

SFR

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Name

RPOR0 0670

RPOR1 0672

RPOR2 0674

RPOR3 0676

RPOR4 0678

RPOR5 067A

RPOR6 067C

RPOR7 067E

RPOR8 0680

RPOR9 0682