Datasheet PIC24EP32GP202, PIC24EP32GP203, PIC24EP32GP204, dsPIC33EP32GP502, dsPIC33EP32GP503 Datasheet
...
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X Family Silicon Errata and Data Sheet Clarification
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X family devices that you have
received conform functionally to the current Device Data
Sheet (DS70657E), except for the anomalies described in
this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will
be
addressed in future revisions of
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X silicon.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. The current
silicon revision levels are:
PIC24EP32/dsPIC33EP32: A3
PIC24EP64/dsPIC33EP64: A3
PIC24EP128/dsPIC33EP128: A3
PIC24EP256/dsPIC33EP256: A3
“N/A” indicates that the device family is
not released, or that the particular silicon
issue does not apply to this family.
Data Sheet clarifications and corrections start on
Page 13, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 3 or
PICkit™ 3:
1. Using the appropriate interface, connect the device
to the MPLAB ICD 3 programmer/debugger or
PICkit 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the development tool used, the part number and Device
Revision ID value appear in the Output window.
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The Device and Revision ID values for the various
silicon revisions are shown in
®
IDE and Microchip’s
Ta bl e 1.
2011-2012 Microchip Technology Inc. DS80533D-page 1
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID
(1)
Silicon Revision/Device ID
PIC24EP32GP202 0x1C19
PIC24EP32GP203 0x1C1A
PIC24EP32GP204 0x1C18
dsPIC33EP32GP502 0x1C0D
dsPIC33EP32GP503 0x1C0E
dsPIC33EP32GP504 0x1C0C
PIC24EP32MC202 0x1C11
PIC24EP32MC203 0x1C12
PIC24EP32MC204 0x1C10
—
dsPIC33EP32MC202 0x1C01
dsPIC33EP32MC203 0x1C02
dsPIC33EP32MC204 0x1C00
dsPIC33EP32MC502 0x1C05
dsPIC33EP32MC503 0x1C06
dsPIC33EP32MC504 0x1C04
dsPIC33EP32MC506 0x1D27
PIC24EP64GP202 0x1D39
PIC24EP64GP203 0x1D3A
PIC24EP64GP204 0x1D38
PIC24EP64GP206 0x1D3B
dsPIC33EP64GP502 0x1D2D
dsPIC33EP64GP503 0x1D2E
dsPIC33EP64GP504 0x1D2C
dsPIC33EP64GP506 0x1D2F
PIC24EP64MC202 0x1D31
PIC24EP64MC203 0x1D32
PIC24EP64MC204 0x1D30
A2
0x4002
PIC24EP64MC206 0x1D33
dsPIC33EP64MC202 0x1D21
dsPIC33EP64MC203 0x1D22
dsPIC33EP64MC204 0x1D20
dsPIC33EP64MC206 0x1D23
dsPIC33EP64MC502 0x1D25
dsPIC33EP64MC503 0x1D26
dsPIC33EP64MC504 0x1D24
dsPIC33EP64MC506 0x1D27
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.
(2)
A3
0x4003
A3
0x4003
DS80533D-page 2 2011-2012 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 1: SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID
(1)
Silicon Revision/Device ID
PIC24EP128GP202 0x1E59
PIC24EP128GP204 0x1E58
PIC24EP128GP206 0x1E5B
dsPIC33EP128GP502 0x1E4D
dsPIC33EP128GP504 0x1E4C
dsPIC33EP128GP506 0x1E4F
PIC24EP128MC202 0x1E51
PIC24EP128MC204 0x1E50
—
PIC24EP128MC206 0x1E53
dsPIC33EP128MC202 0x1E41
dsPIC33EP128MC204 0x1E40
dsPIC33EP128MC206 0x1E43
dsPIC33EP128MC502 0x1E45
dsPIC33EP128MC504 0x1E44
dsPIC33EP128MC506 0x1E47
PIC24EP256GP202 0x1F79
PIC24EP256GP204 0x1F78
PIC24EP256GP206 0x1F7B
dsPIC33EP256GP502 0x1F6D
dsPIC33EP256GP504 0x1F6C
dsPIC33EP256GP506 0x1F6F
PIC24EP256MC202 0x1F71
PIC24EP256MC204 0x1F70
—
PIC24EP256MC206 0x1F73
dsPIC33EP256MC202 0x1F61
dsPIC33EP256MC204 0x1F60
dsPIC33EP256MC206 0x1F63
dsPIC33EP256MC502 0x1F65
dsPIC33EP256MC504 0x1F64
dsPIC33EP256MC506 0x1F67
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.
(2)
A3
0x4003
A3
0x4003
2011-2012 Microchip Technology Inc. DS80533D-page 3
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
CPU div.sd 1. When using the div.sd instruction, the overflow bit is not getting set when
CPU DO Loop 2. PSV access, including table reads or writes in the last instruction of a DO
SPI Frame Sync Pulse 3. Frame Sync pulse is not generated in Master mode when FRMPOL = 0.
SPI Frame Sync Pulse 4. When in SPI Slave mode, with the Frame Sync pulse set as an input,
UART TX Interrupt 5. A Transmit (TX) interrupt may occur before the data transmission is complete.
Power
System
ADC DONE bit 7. The ADC Conversion Status bit (DONE) does not work when an external
PTG Strobe Output 8. Strobe output pulse width is incorrectly dependent on the PTGPWD<3:0>
Op Amp Enabling Op Amp
Op Amp AC/DC Electrical
PWM Dead-Time
Flash Flash Programming 12. The stall mechanism may not function properly when erasing or
QEI Index Counter 13. The QEI Index Counter does not count correctly in Quadrature Detector
QEI Modulo Mode 14. Modulo mode functionality is incorrect when the Count Polarity bit is set.
PWM Master Time Base
ADC 1.1 Msps Sampling 16. Selecting the same ANx input (AN0 or AN3) for CH0 and CH1 to achieve a
ADC Channel Scan 17. Channel scanning is limited to AN0 through AN15.
Output
Compare
ECAN™ DMA 19. Write collisions on a DMA-enabled ECAN™ module do not generate
PWM Immediate Update 20. Dead time is not asserted when PDCx is updated to cause an immediate
PWM Center-Aligned
PWM Complementary
CPU Program Memory 23. Address error trap may occur while accessing certain program memory
PWM Center-Aligned
PWM Independent Time
Flash Regulator 6. The VREGSF (RCON<11>) bit always reads back as ‘0’.
mode
Characteristics
Compensation
Mode
Interrupt 18. Under certain circumstances, an output compare match may cause the
Mode
Mode
Mode
Base Mode
Item
Number
an overflow occurs.
loop is not allowed.
FRMDLY must be set to ‘0’.
interrupt is selected as the ADC trigger source.
(PTGCON<7:4>) bit settings.
9. When using any of these Op Amp modules, or Analog Channels AN0, AN3
or AN6, to sample external signals, bit
set to ‘1’.
10. The AC/DC electrical characteristics for the Op Amp module (and the
related ADC specifications) are not within the specifications published in
the current data sheet.
11. Dead-Time Compensation is not enabled for Center-Aligned PWM mode.
programming Flash memory.
mode.
15. In Master Time Base mode, writing to the period register, and any other
timing parameter of the PWM module, will cause the update of the other
timing parameter to take effect one PWM cycle after the period update is
effective.
1.1 Msps sampling rate results in erroneous readings for CH1.
Output Compare Interrupt Flag (OCxIF) bit to become set prior to the
Change-of-State (COS) of the OCx pin.
DMAC error traps.
transition on the PWMxH and PWMxL outputs.
21. PWMxH is asserted for 100% of the PWM period in Complementary mode
under certain circumstances.
22. With dead time greater than zero, 0% and 100% duty cycle cannot be
obtained on PWMxL and PWMxH outputs.
locations.
24. Updates to active MDC/PDCx/ALTDTRx/PHASEx registers occur only
once every two PWM periods.
25. If IOCONx register is updated from 0xC300 to 0xC000, PWMxH or PWMxL
outputs may stop functioning.
Issue Summary
11 of the CMxCON register must be
DS80533D-page 4 2011-2012 Microchip Technology Inc.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
Silicon Errata Issues
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current.
1. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
2. Module: CPU
Table Write (TBLWTL, TBLWTH) instructions cannot
be the first or last instruction of a DO loop.
Work around
None.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
3. Module: SPI
When using the Frame Sync pulse output feature
(FRMEN bit (SPIxCON2<15>) = 1), in Master
mode (SPIFSD bit (SPIxCON2<14>) = 0), the
Frame Sync pulse is not being generated
with an active-low pulse (FRMPOL bit
(SPIxCON2<13>)
Work around
The SSx pin is used as the Frame Sync pulse
when the Frame Sync pulse output feature is used.
Mapping the
function to the same pad, by using the Peripheral
Pin Select (PPS) feature, resolves this issue.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
= 0).
SSx input function and output
4. Module: SPI
When in SPI Slave mode (MSTEN bit
(SPIxCON1<5>) = 0) and using the Frame Sync
pulse output feature (FRMEN bit
(SPIxCON2<15>) = 1) in Slave mode (SPIFSD bit
(SPIxCON2<14>) = 0), the Frame Sync Pulse
Edge Select bit must be set to ‘0’ (FRMDLY bit
(SPIxCON2<1>) = 0).
Work around
There is no work around. The Frame Sync Pulse
Edge Select bit, FRMDLY, cannot be set to
produce a Frame Sync pulse that coincides with
the first bit clock.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
2011-2012 Microchip Technology Inc. DS80533D-page 5
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
5. Module: UART
When using the UTXISELx bits = 01 (interrupt
when last character is shifted out of the Transmit
Shift Register) and the final character is being
shifted out through the Transmit Shift Register
(TSR), the Transmit (TX) interrupt may occur
before the final bit is shifted out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
6. Module: Power System
The VREGSF bit functions as documented, but will
always read back as ‘0’. Because of the
Read-Modify-Write process, any BSET or BCLR
instruction of the RCON register will also write a ‘0’
to the VREGSF bit.
Work around
If the VREGSF bit is intended to be set to ‘1’, the
user software must also write a ‘1’ to the VREGSF
bit when setting or clearing any other bit in the
RCON register.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
7. Module: ADC
The ADC Conversion Status (DONE) bit
(ADxCON1<0>) does not indicate completion of
conversion when an external interrupt is selected
as the ADC trigger source (SSRC<2:0> bits
(AD1CON1<7:5>) = 0x1).
Work around
Use an ADC interrupt or poll the ADxIF bit in the
IFSx registers to determine the completion of
conversion.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
8. Module: PTG
When using the strobe output step commands
(PTGCTRL 0x1110, PTGCTRL 0x1100 and
PTGCTRL 0x110) to write to the AD1CHS0
register, the PTGPWD<3:0> bits (PTGCON<7:4>)
determine the number of times the PTG module
will write to the AD1CHS0 register.
Work around
Set the PTGPWD<3:0> bits to ‘0000’ so that the
PTG module does not write to the AD1CHS0
register multiple times.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
DS80533D-page 6 2011-2012 Microchip Technology Inc.
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