Datasheet PIC24EP32GP202, PIC24EP32GP203, PIC24EP32GP204, dsPIC33EP32GP502, dsPIC33EP32GP503 Datasheet

dsPIC33EPXXXGP50X,

dsPIC33EPXXXMC20X/50X

and PIC24EPXXXGP/MC20X

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and

PIC24EPXXXGP/MC20X Family Silicon Errata and Data Sheet Clarification

The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X family devices that you have
received conform functionally to the current Device Data
Sheet (DS70657E), except for the anomalies described in
this document.

The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will
be

addressed in future revisions of
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X silicon.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,
previous as well as current. The current
silicon revision levels are:



PIC24EP32/dsPIC33EP32: A3
PIC24EP64/dsPIC33EP64: A3
PIC24EP128/dsPIC33EP128: A3
PIC24EP256/dsPIC33EP256: A3



“N/A” indicates that the device family is
not released, or that the particular silicon
issue does not apply to this family.

Data Sheet clarifications and corrections start on

Page 13, following the discussion of silicon issues.



The silicon revision level can be identified using the
current version of MPLAB
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).

For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 3 or
PICkit™ 3:

1. Using the appropriate interface, connect the device
to the MPLAB ICD 3 programmer/debugger or
PICkit 3.

2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.

3. Select the MPLAB hardware tool
(Debugger>Select Tool).

4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel­opment tool used, the part number and Device
Revision ID value appear in the Output window.

Note: If you are unable to extract the silicon

revision level, please contact your local
Microchip sales office for assistance.

The Device and Revision ID values for the various
silicon revisions are shown in

®

IDE and Microchip’s

Ta bl e 1.

 2011-2012 Microchip Technology Inc. DS80533D-page 1

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Silicon Revision/Device ID

PIC24EP32GP202 0x1C19

PIC24EP32GP203 0x1C1A

PIC24EP32GP204 0x1C18

dsPIC33EP32GP502 0x1C0D

dsPIC33EP32GP503 0x1C0E

dsPIC33EP32GP504 0x1C0C

PIC24EP32MC202 0x1C11

PIC24EP32MC203 0x1C12

PIC24EP32MC204 0x1C10

—

dsPIC33EP32MC202 0x1C01

dsPIC33EP32MC203 0x1C02

dsPIC33EP32MC204 0x1C00

dsPIC33EP32MC502 0x1C05

dsPIC33EP32MC503 0x1C06

dsPIC33EP32MC504 0x1C04

dsPIC33EP32MC506 0x1D27

PIC24EP64GP202 0x1D39

PIC24EP64GP203 0x1D3A

PIC24EP64GP204 0x1D38

PIC24EP64GP206 0x1D3B

dsPIC33EP64GP502 0x1D2D

dsPIC33EP64GP503 0x1D2E

dsPIC33EP64GP504 0x1D2C

dsPIC33EP64GP506 0x1D2F

PIC24EP64MC202 0x1D31

PIC24EP64MC203 0x1D32

PIC24EP64MC204 0x1D30

A2

0x4002

PIC24EP64MC206 0x1D33

dsPIC33EP64MC202 0x1D21

dsPIC33EP64MC203 0x1D22

dsPIC33EP64MC204 0x1D20

dsPIC33EP64MC206 0x1D23

dsPIC33EP64MC502 0x1D25

dsPIC33EP64MC503 0x1D26

dsPIC33EP64MC504 0x1D24

dsPIC33EP64MC506 0x1D27

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration

Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.

(2)

A3

0x4003

A3

0x4003

DS80533D-page 2  2011-2012 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

TABLE 1: SILICON DEVREV VALUES (CONTINUED)

Part Number Device ID

(1)

Silicon Revision/Device ID

PIC24EP128GP202 0x1E59

PIC24EP128GP204 0x1E58

PIC24EP128GP206 0x1E5B

dsPIC33EP128GP502 0x1E4D

dsPIC33EP128GP504 0x1E4C

dsPIC33EP128GP506 0x1E4F

PIC24EP128MC202 0x1E51

PIC24EP128MC204 0x1E50

—

PIC24EP128MC206 0x1E53

dsPIC33EP128MC202 0x1E41

dsPIC33EP128MC204 0x1E40

dsPIC33EP128MC206 0x1E43

dsPIC33EP128MC502 0x1E45

dsPIC33EP128MC504 0x1E44

dsPIC33EP128MC506 0x1E47

PIC24EP256GP202 0x1F79

PIC24EP256GP204 0x1F78

PIC24EP256GP206 0x1F7B

dsPIC33EP256GP502 0x1F6D

dsPIC33EP256GP504 0x1F6C

dsPIC33EP256GP506 0x1F6F

PIC24EP256MC202 0x1F71

PIC24EP256MC204 0x1F70

—

PIC24EP256MC206 0x1F73

dsPIC33EP256MC202 0x1F61

dsPIC33EP256MC204 0x1F60

dsPIC33EP256MC206 0x1F63

dsPIC33EP256MC502 0x1F65

dsPIC33EP256MC504 0x1F64

dsPIC33EP256MC506 0x1F67

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration

Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.

(2)

A3

0x4003

A3

0x4003

 2011-2012 Microchip Technology Inc. DS80533D-page 3

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

TABLE 2: SILICON ISSUE SUMMARY

Module Feature

CPU div.sd 1. When using the div.sd instruction, the overflow bit is not getting set when

CPU DO Loop 2. PSV access, including table reads or writes in the last instruction of a DO

SPI Frame Sync Pulse 3. Frame Sync pulse is not generated in Master mode when FRMPOL = 0.
SPI Frame Sync Pulse 4. When in SPI Slave mode, with the Frame Sync pulse set as an input,

UART TX Interrupt 5. A Transmit (TX) interrupt may occur before the data transmission is complete.
Power

System
ADC DONE bit 7. The ADC Conversion Status bit (DONE) does not work when an external

PTG Strobe Output 8. Strobe output pulse width is incorrectly dependent on the PTGPWD<3:0>

Op Amp Enabling Op Amp

Op Amp AC/DC Electrical

PWM Dead-Time

Flash Flash Programming 12. The stall mechanism may not function properly when erasing or

QEI Index Counter 13. The QEI Index Counter does not count correctly in Quadrature Detector

QEI Modulo Mode 14. Modulo mode functionality is incorrect when the Count Polarity bit is set.
PWM Master Time Base

ADC 1.1 Msps Sampling 16. Selecting the same ANx input (AN0 or AN3) for CH0 and CH1 to achieve a

ADC Channel Scan 17. Channel scanning is limited to AN0 through AN15.
Output

Compare

ECAN™ DMA 19. Write collisions on a DMA-enabled ECAN™ module do not generate

PWM Immediate Update 20. Dead time is not asserted when PDCx is updated to cause an immediate

PWM Center-Aligned

PWM Complementary

CPU Program Memory 23. Address error trap may occur while accessing certain program memory

PWM Center-Aligned

PWM Independent Time

Flash Regulator 6. The VREGSF (RCON<11>) bit always reads back as ‘0’.

mode

Characteristics

Compensation

Mode

Interrupt 18. Under certain circumstances, an output compare match may cause the

Mode

Mode

Mode

Base Mode

Item

Number

an overflow occurs.

loop is not allowed.

FRMDLY must be set to ‘0’.

interrupt is selected as the ADC trigger source.

(PTGCON<7:4>) bit settings.

9. When using any of these Op Amp modules, or Analog Channels AN0, AN3

or AN6, to sample external signals, bit
set to ‘1’.

10. The AC/DC electrical characteristics for the Op Amp module (and the

related ADC specifications) are not within the specifications published in
the current data sheet.

11. Dead-Time Compensation is not enabled for Center-Aligned PWM mode.

programming Flash memory.

mode.

15. In Master Time Base mode, writing to the period register, and any other

timing parameter of the PWM module, will cause the update of the other
timing parameter to take effect one PWM cycle after the period update is
effective.

1.1 Msps sampling rate results in erroneous readings for CH1.

Output Compare Interrupt Flag (OCxIF) bit to become set prior to the
Change-of-State (COS) of the OCx pin.

DMAC error traps.

transition on the PWMxH and PWMxL outputs.

21. PWMxH is asserted for 100% of the PWM period in Complementary mode

under certain circumstances.

22. With dead time greater than zero, 0% and 100% duty cycle cannot be

obtained on PWMxL and PWMxH outputs.

locations.

24. Updates to active MDC/PDCx/ALTDTRx/PHASEx registers occur only

once every two PWM periods.

25. If IOCONx register is updated from 0xC300 to 0xC000, PWMxH or PWMxL

outputs may stop functioning.

Issue Summary

11 of the CMxCON register must be

DS80533D-page 4  2011-2012 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

Silicon Errata Issues

Note: This document summarizes all silicon

errata issues from all revisions of silicon,
previous as well as current.

1. Module: CPU

When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.

Work around

Test for and handle overflow conditions outside of
the div.sd instruction.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

2. Module: CPU

Table Write (TBLWTL, TBLWTH) instructions cannot
be the first or last instruction of a DO loop.

Work around

None.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

3. Module: SPI

When using the Frame Sync pulse output feature
(FRMEN bit (SPIxCON2<15>) = 1), in Master
mode (SPIFSD bit (SPIxCON2<14>) = 0), the
Frame Sync pulse is not being generated
with an active-low pulse (FRMPOL bit
(SPIxCON2<13>)

Work around

The SSx pin is used as the Frame Sync pulse
when the Frame Sync pulse output feature is used.
Mapping the
function to the same pad, by using the Peripheral
Pin Select (PPS) feature, resolves this issue.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

= 0).

SSx input function and output

4. Module: SPI

When in SPI Slave mode (MSTEN bit
(SPIxCON1<5>) = 0) and using the Frame Sync
pulse output feature (FRMEN bit
(SPIxCON2<15>) = 1) in Slave mode (SPIFSD bit
(SPIxCON2<14>) = 0), the Frame Sync Pulse
Edge Select bit must be set to ‘0’ (FRMDLY bit
(SPIxCON2<1>) = 0).

Work around

There is no work around. The Frame Sync Pulse
Edge Select bit, FRMDLY, cannot be set to
produce a Frame Sync pulse that coincides with
the first bit clock.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

 2011-2012 Microchip Technology Inc. DS80533D-page 5

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

5. Module: UART

When using the UTXISELx bits = 01 (interrupt
when last character is shifted out of the Transmit
Shift Register) and the final character is being
shifted out through the Transmit Shift Register
(TSR), the Transmit (TX) interrupt may occur
before the final bit is shifted out.

Work around

If it is critical that the interrupt processing occurs
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

6. Module: Power System

The VREGSF bit functions as documented, but will
always read back as ‘0’. Because of the
Read-Modify-Write process, any BSET or BCLR
instruction of the RCON register will also write a ‘0’
to the VREGSF bit.

Work around

If the VREGSF bit is intended to be set to ‘1’, the
user software must also write a ‘1’ to the VREGSF
bit when setting or clearing any other bit in the
RCON register.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

7. Module: ADC

The ADC Conversion Status (DONE) bit
(ADxCON1<0>) does not indicate completion of
conversion when an external interrupt is selected
as the ADC trigger source (SSRC<2:0> bits
(AD1CON1<7:5>) = 0x1).

Work around

Use an ADC interrupt or poll the ADxIF bit in the
IFSx registers to determine the completion of
conversion.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

8. Module: PTG

When using the strobe output step commands
(PTGCTRL 0x1110, PTGCTRL 0x1100 and
PTGCTRL 0x110) to write to the AD1CHS0
register, the PTGPWD<3:0> bits (PTGCON<7:4>)
determine the number of times the PTG module
will write to the AD1CHS0 register.

Work around

Set the PTGPWD<3:0> bits to ‘0000’ so that the
PTG module does not write to the AD1CHS0
register multiple times.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

DS80533D-page 6  2011-2012 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

9. Module: Op Amp

When using any of these Op Amp modules, or
Analog Channels AN0, AN3 or AN6 to sample
external signals, bit 11 of the CMxCON register
must be set to ‘1’.

If Using

This

Feature:

AN0 CM2CON.OPMODE = 0 CM2CON<11> = 1

AN3 CM1CON.OPMODE = 0 CM1CON<11> = 1

AN6 CM3CON.OPMODE = 0 CM3CON<11> = 1

Op Amp 1 CM1CON.OPMODE = 1 CM1CON<11> = 1

Op Amp 2 CM2CON.OPMODE = 1 CM2CON<11> = 1

Op Amp 3 CM3CON.OPMODE = 1 CM3CON<11> = 1

Work around

None.

Affected Families and Silicon Revisions

24EP32/33EP32 devices —

24EP64/33EP64 devices A2

24EP128/33EP128 devices —

24EP256/33EP256 devices —

These conditions must be met:

OPMODE

(CMxCON<10>)

CMxCON<11>

10. Module: Op Amp

The AC/DC electrical characteristics for the Op
Amp module (and the related ADC module
specifications) differ from the specifications in the
published data sheet. Refer to
(below) for the A2 revision silicon specifications.

Work around

None.

Affected Families and Silicon Revisions

24EP32/33EP32 devices —

24EP64/33EP64 devices A2

24EP128/33EP128 devices —

24EP256/33EP256 devices —

Table 3 and Ta b le 4

TABLE 3 : AC/DC CHARACTERISTICS: OP AMP

Param.

No.

CM21a PM — 40 — Degree —

CM21b PM — 30 — Degree —

CM23a GBW — 7 — MHz —

CM23b GBW — 2 — MHz —

CM49a VOADC AVSS + 0.350

CM49b VOUT AVSS + 0.375

CM51a RINT1 351 468 613  —

Symbol Minimum Typical Maximum Units Conditions

AVSS + 0.500

AVSS + 0.525

—
—

—
—

AVDD – 0.350
AVDD – 0.500

AVDD – 0.375
AVDD – 0.525

V
V

V
V

IOUT = 390 µA, Op Amp 1 and 2
IOUT = 390 µA, Op Amp 3

IOUT = 390 µA, Op Amp 1 and 2
IOUT = 390 µA, Op Amp 3

TABLE 4 : AC/DC CHARACTERISTICS: ADC

Parameter

No.

AD57b TSAMP

Symbol Minimum Typical Maximum Units Conditions

5 TAD — — —

5 TAD — — —

7 TAD — — —

Op Amp 1 and 2, 12-bit mode, 
Configuration B

Op Amp 3, 10-bit mode, 
Configuration B

Op Amp 3, 12-bit mode, 
Configuration B

 2011-2012 Microchip Technology Inc. DS80533D-page 7

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

; Load write latches if programming

…

; Setup NVMCON register to erase or program

as required

…

; Disable interrupts

PUSH SR
MOV #0x00E0, W0
IOR SR

; Write the KEY sequence

MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY

; Start the programming sequence

BSET NVMCON, #15

; Insert two NOPs after programming

NOP

NOP
; Wait for operation to complete
prog_wait:

BTSC NVMCON, #15

BRA prog_wait
; Re-enable interrupts,

POP SR

11. Module: PWM

When dead-time compensation is enabled
(DTC<1:0> (PWMCONx<7:6>) = 11) in
Center-Aligned mode (CAM (PWMCONx<2>) = 1),
the dead time, as specified in the ALTDTRx
register, is not being applied to the PWMxH output.
The leading and trailing edges of the PWMxL
output are extended by one-half the value of the
ALTDTRx register, but the PWMxH leading and
trailing edges are unaffected.

Work around

Using the values from the “dsPIC33E/PIC24E
Family Reference Manual”, Section 14.

“High-Speed PWM” (DS70645), adjust the PWM
parameters as follows:

• Subtract one-half of the ALTDTR dead time
from PDCx

• Use twice the value for ALTDTR. For example:

- Frequency of 60 kHz, duty cycle of 50%

- Desired dead time of 833 ns and dead-time

compensation of 833 ns

Using the specified values from Section 14.
“High-Speed PWM” (DS70645):

• PHASEx = 1000

• PDCx = 500

• ALTDTR = 833 ns/8.33 ns = 100

• DTR = (833 ns/8.33 ns)/2 = 50

Applying the work around:

• ALTDTR = 2 * 100 = 200

• PDCx = PDCx – 25 = 475

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

DS80533D-page 8  2011-2012 Microchip Technology Inc.

12. Module: Flash

The stall mechanism may not function properly
when erasing or programming Flash memory.

Work around

Disable interrupts until the erase or programming
operation is complete. Test for completion by
inserting a bit test operation of the Write Control
(WR) bit.

Code is provided in Example 1 that can be used to
disable interrupts during RTSP erase/program
operations.

EXAMPLE 1:

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

13. Module: QEI

In Quadrature Encoder mode (CMM<1:0>
(QEIxCON<1:0>) = 00), the Index Counter
registers (INDXxCNTH and INDXxCNTL) cannot
be relied upon to increment when the last known
direction was positive and an index pulse occurs.
The Index Counter register can decrement even if
the last known direction was positive. This does
not apply to External Clock or Internal Timer QEI
modes.

Work around

The index event can be used to implement a
software counter. The direction could be
determined by comparing the current POSxCNT
value to that of the previous Index Event.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

14. Module: QEI

When Modulo Count mode (Mode 6) is selected
for the position counter (PIMOD<2:0>
(QEIxCON<12:10>) = 110), and the counter
direction is set to negative (CNTPOL
(QEIxCON<3>) = 1), the functions of the QEIxLEC
and QEIxGEC registers are reversed.

Work around

When using Modulo Count mode in conjunction
with a negative count direction (polarity), use the
QEIxLEC register as the upper count limit and the
QEIxGEC as the lower count limit.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

15. Module: PWM

The PWM module can operate with variable
period, duty cycle, dead time and phase values.
The master period and other timing parameters
can be updated in the same PWM cycle. With
immediate updates disabled, the new values
should take effect at the start of the next PWM
cycle.

As a result of this issue, the updated master period
takes effect on the next PWM cycle, while the
update of the additional timing parameter is
delayed by one PWM cycle. The parameters
affected by this erratum are as follows:

Master Period Registers – update effective on the
next PWM cycle:

• PTPER – if MTBS (PWMCONx<3>) = 0

• STPER – if MTBS (PWMCONx<3>) = 1

Additional PWM timing parameters: update
effective one PWM cycle after master period
update:

• Duty Cycle – PDCx, SDCx, and MDC registers

• Phase – PHASEx or SPHASEx registers

• Dead Time – DTRx and ALTDTRx registers
and dead-time compensation signals

• Clearing of current limit and Fault conditions,
and application of External Period Reset signal

Work around

If the application requires the master period and
other parameters to be updated at the same time,
enable both immediate updates:

• EIPU (PTCON<10>) = 1 – to enable
immediate period updates

• IUE (PWMCONx<0>) = 1 – to enable
immediate updates of additional parameters
listed above

Enabling immediate updates will allow updates to
the master period and the other parameter to take
effect immediately after writing to the respective
registers.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

 2011-2012 Microchip Technology Inc. DS80533D-page 9

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

16. Module: ADC

Selecting the same ANx input (AN0 or AN3) for
CH0 and CH1 to achieve a 1.1 Msps sampling rate
results in erroneous readings for CH1.

Work around

Bring the analog signal into the device using both
AN0 and AN3, connect externally, and then assign
one input to CH0 and the other to CH1.

If selecting AN0 on CH1 (CH123Sx = 0), select
AN3 on CH0 (CH0Sx = 3). Conversely, if selecting
AN3 on CH1 (CH123Sx = 1), select AN0 on CH0
(CH0Sx = 0).

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

17. Module: ADC

Selection of channels for channel scan operation
is limited to those available in the AD1CSSL
register (AN0 through AN15). Selections in the
AD1CSSH register, (OA1 through OA3, CTMU
TEMP and CTMU Open) are not available.

Work around

There is no work around of the CTMU TEMP and
CTMU Open selections. OA1 through OA3 can be
scanned using AN3, AN0 and AN6 for Op Amp 1,
Op Amp 2 and Op Amp 3, respectively.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

18. Module: Output Compare

Under certain circumstances, an output compare
match may cause the Output Compare Interrupt
Flag (OCxIF) to become set prior to the
Change-of-State (COS) of the OCx pin. This has
been observed when all of the following are true:

• The module is in One-Shot mode 
(OCM<2:0> = 001, 010 or 100);

• One of the timer modules is being used as the
time base; and

• A timer prescaler other than 1:1 is selected

If the module is re-initialized by clearing
OCM<2:0> after the One-Shot compare, the OCx
pin may not be driven as expected.

Work around

After OCxIF is set, allow an interval (in CPU
cycles) of at least twice the prescaler factor to
elapse before clearing OCM<2:0>. For example,
for a prescaler value of 1:8, allow 16 CPU cycles
to elapse after the interrupt.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

19. Module: ECAN™

When DMA is used with the ECAN module, and
the CPU and DMA write to an ECAN Special
Function Register (SFR) at the same time, the
DMAC error trap is not occurring. In addition,
neither the PWCOL<3:0> bits of the DMAPWC
SFR or the DMACERR bit of the INTCON1 SFR
are being set. Since the PWCOLx bits are not set,
subsequent DMA requests to that channel are not
ignored.

Work around

There is no work around; however, under normal
circumstances, this situation should not arise.
When DMA is used with the ECAN module, the
application should not be writing to the ECAN
SFRs.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

DS80533D-page 10  2011-2012 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

Altdtr_by2 = ALTDTRx / 2;
if (PDCtemp < Altdtr_by2)
{

PDCx = Altdtr_by2;
}

else
{

PDCx = PDCtemp;

}

20. Module: PWM

The PWM generator may not assert dead time on
the edges of transitions. This has been observed
when all of the following conditions are present:

• The PWM generator is configured to operate
in Complementary mode with independent
time base or master time base;

• Immediate update is enabled; and

• The value in the PDC register is updated in
such a manner that the PWMxH and PWMxL
outputs make an immediate transition.

Work around

None.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

21. Module: PWM

In Center-Aligned Complementary mode with
independent time-base, the PWM generator may
assert the PWMxH output for 100% of the duty
cycle. This has been observed when the value in
its PDC register is less than one-half the value in
its ALTDTR register.

Work around

Include a software routine to check that the duty
cycle value written to the PDCx register is always
at least one-half of the value in ALTDTRx.

Example 2 shows one way of doing this, with

PDCtemp representing the value to be witten to the
PDCx register.

EXAMPLE 2:

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

 2011-2012 Microchip Technology Inc. DS80533D-page 11

22. Module: PWM

This issue is applicable when a PWM generator is
configured to operate in Independent Time Base
mode with either Center-Aligned Complementary
mode or Edge-Aligned Complementary mode.
When dead time is non-zero, PWMxL is not
asserted for 100% of the time when PDCx is zero.
Similarly, when dead time is non-zero, PWMxH is
not asserted for 100% of the time when PDCx is
equal to PHASEx. This issue applies to Master
Time Base mode as well.

Work around

In Center-Aligned mode:

• To obtain 0% duty cycle, first zero out the
ALTDTRx register, then write zero to the
PDCx register.

• To obtain 100% duty cycle, first zero out the
ALTDTRx register, then write (PHASEx + 2) to
the PDCx register.

In Edge-Aligned mode:

• To obtain 0% duty cycle, first zero out the
registers, DTRx and ALTDTRx, then write
zero to the PDCx register.

• To obtain 100% duty cycle, first zero out the
registers, DTRx and ALTDTRx, then write
(PHASEx + 1) to the PDCx register.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

23. Module: CPU

An unexpected address error trap may occur
during accesses to program memory addresses,
0x001 through 0x200. This has been observed
when one or more interrupt requests are asserted
while reading or writing program memory
addresses, using TBLRDx, TBLWTx or PSV-based
instructions.

Work around

Before executing instructions that read or write
program memory addresses, 0x001 through
0x200, disable interrupts using the DISI
instruction.

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

24. Module:PWM

In Center-Aligned mode, updates to active
MDC/PDCx/ALTDTRx/PHASEx registers occur
only once every two PWM periods; that is, when
the PWM timer matches the PHASEx register.

Work around

None

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

25. Module:PWM

Under certain circumstances, if the IOCONx
register is updated from 0xC300 to 0xC000,
PWMxH or PWMxL outputs may stop functioning.

Work around

None

Affected Families and Silicon Revisions

24EP32/33EP32 devices A3

24EP64/33EP64 devices A3

24EP128/33EP128 devices A3

24EP256/33EP256 devices A3

DS80533D-page 12  2011-2012 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

Data Sheet Clarifications

The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70657E)

Note: Corrections are shown in bold. Where

1. Module: Packaging

The device data sheet provides drawing
C04-149C (2 pages) to describe the 64-pin QFN
package for this family. The drawing indicates an
exposed center pad of 7.15
nominal.

The actual packaging used for 64-pin QFN devices is
described by drawing C04-154A (2 pages), which
indicates an exposed center pad of 5.4
nominal. Key package dimensions (9 x 9 x 0.9 mm)
are the same for both packages, as are the landing
drawing (C04-2149A) and the board footprint.

The correct drawing, C04-154A, is shown on the
following pages.

:

possible, the original bold text formatting
has been removed for clarity.

mm x 7.15 mm

mm x 5.4 mm

2. Module: High-Speed PWM Module

In the description of Register 16-7:
PWMCONx, updates to the active
MDC/PDCx/DTx/ALTDTRx/PHASEx registers are
synchronized to the PWM period boundary,
regardless of the state of bit 0 (IUE). In addition,
when bit 0 (IUE) is set to ‘1’, updates to the active
MDC/PDCx/DTx/ALTDTRx/PHASEx registers are
immediate.

 2011-2012 Microchip Technology Inc. DS80533D-page 13

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS80533D-page 14  2011-2012 Microchip Technology Inc.

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011-2012 Microchip Technology Inc. DS80533D-page 15

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X

APPENDIX A: REVISION HISTORY

Rev A Document (11/2011)

Initial release of this document; issued for revision A2
silicon.

Includes silicon issues 1 (CPU), 2, (CPU) 3 (SPI),
4 (SPI), 5 (UART), 6 (Power System), 7 (ADC), 8 (PTG),
9 (Op Amp), 10 (Op Amp), 11 (PWM), 12 (Flash),
13 (QEI), 14 (QEI) and 15 (PWM).

Rev B Document (4/2012)

Updated silicon issues 9 (Op Amp), 10 (Op Amp), and
12 (Flash).

Added silicon issues 16 (ADC), 17 (ADC), 18 (Output

Compare), and 19 (ECAN™).

Rev C Document (6/2012)

Updated document to include all related device families
(program memory sizes of 32, 128, 256 and 512 Kbytes)
in this superfamily. In the process, revised the document
format to accommodate the different silicon revision
levels across the different families.

Added silicon issues 20, 21 and 22 (PWM), and
23 (CPU) to all device families.

Added data sheet clarification 1 (Packaging).

Rev D Document (8/2012)

Updated Ta ble 1 to include both A2 and A3 silicon
revision device IDs and removed
PIC24EP512/dsPIC32EP512 (A4). Updated all Affected
Families and Silicon Revisions tables. Added silicon
issues 24
clarification 2 (High-Speed PWM Module).

(PWM) and 25 (PWM). Added data sheet

DS80533D-page 16  2011-2012 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC

logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2011-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.

Printed on recycled paper.

QUALITY MANAGEMENT S

 2011-2012 Microchip Technology Inc. DS80533D-page 17

ISBN: 978-1-62076-486-2

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

Worldwide Sales and Service

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11/ 29/11

DS80533D-page 18  2011-2012 Microchip Technology Inc.