Datasheet DSP1627 Datasheet (AGERE)

Page 1
Data Sheet March 2000
DSP1627 Digital Signal Processor

1 Features

Optimized for digital cellular applications with a bit mani p-
ulation unit for higher coding efficiency.
On-chip, programmable, PLL clock synthesizer.
struction cycle time at 3.0 V, and 20 ns and 12.5 ns in­struction cycle times at 2.7 V, respectively.
Mask-programmable memory map option: The
DSP1627x36 features 36 Kwords on-chip ROM. The DSP1627x32 features 32 Kwords on-chip ROM and ac­cess to 16 Kwords external ROM in the same map. Both feature 6 Kwords on-chip, dual-port RAM and a secure option for on-chip ROM.
Low power consumption:
— <5.5 mW/MIPS typical at 5 V. — <1.5 mW/MIPS typical at 2.7 V.
Flexible power management modes:
— Standard sleep: 0.5 mW/MIPS at 5 V.
0.12 mW/MIPS at 2.7 V.
— Sleep with slow internal clock: 1.4 mW at 5 V.
0.4 mW at 2.7 V.
— Hardware STOP (pin halts DSP): <20 µA.
Mask-programmable clock options: crystal oscillator,
small signal, and CMOS.
Low-profile TQFP package (1.5 mm) available.
Sequenced accesses to X and Y external memory.
Object code compatible with the DSP1617.
Single-cycle squaring.
16 x 16-bit multiplication and 36-bit accumulation in one
instruction cycle.
Instruction cache for high-speed, program-efficient, zero-
overhead looping.
Dual 25 Mbits/s serial I/O ports with multiprocessor capa-
bility—16-bit data channel, 8-bit protocol channel.
8-bit parallel host interface:
— Supports 8- or 16-bit transfers. —
Motorola
8-bit control I/O interface.
256 memory-mapped I/O ports.
IEEE
*
Motorola Intel
is a registered trademark of Intel Corp.
† ‡
IEEE
and Electronics Engineers, Inc.
*
or
P1149.1 test port (JTAG boundary scan).
is a registered trademark of Motorola, Inc.
is a registered trademark of The Institute of Electrical
Intel
compatible.
Full-speed in-circuit emulation hardware development
system on-chip.
Supported by DSP1627 software and hardware develop-
ment tools.

2 Description

The DSP1627 is Lucent Technologies Microelectronics Group first digital signal processor offering 100 MIPS oper­ation at 3.0 V and 80 MIPS operation at 2.7 V with a reduc­tion in power consumption. Designed specifically for applications requiring low power dissipation in digital cellu­lar systems, the DSP1627 is a signal-coding device that can be programmed to perform a wide variety of fixed-point sig­nal processing functions. The device is based on the DSP1600 core with a bit manipulation unit for enhanced sig­nal coding efficiency. The DSP1627 includes a mix of pe­ripherals specifically intended to support processing­intensive but cost-sensitive applications in the area of digital wireless communications.
The DSP1627x36 contains 36 Kwords of internal ROM (IROM), but it doesn’t support the use of IROM and external ROM (EROM) in the same memory map. The DSP1627x32 supports the use of 32 Kwords of IROM with 16 Kwords of EROM in the same map. Both devices contain 6 Kwords of dual-port RAM (DPRAM), which allows simultaneous ac­cess to two RAM locations in a single instruction cycle.
The DSP1627 is object code compatible wi th the DSP1617, while providing more memory and architectural enhance­ments including an on-chip clock synthesizer and an 8-bit parallel host interface for hardware flexibility.
The DSP1627 supports 2.7 V, 3.0 V, and 5 V operation and flexible power management modes required for portable cellular terminals. Several control mechanis ms achieve low­power operation, including a STOP pin for placing the DSP into a fully static, halted state and a programmable power control register used to power down unused on-chip I/O units. These power management modes allow for trade-offs between power reduction and wake-up latency require­ments. During system standby, power consumption is re­duced to less than 20 µA.
The on-chip clock synthesizer can be driv en by an external clock whose frequency is a fraction of the instruction rate.
The device is packaged in a 100-pin BQFP or a 100-pin TQFP and is available with 14 ns and 11 ns instruction cycle times at 5 V, 10 ns instruction cycle times at 3.0 V, and 20 ns and 12.5 ns instruction cycle times at 2.7 V, respec­tively.
Page 2
Data Sheet
DSP1627 Digital Signal Processor March 2000

Table of Contents

Contents Page Contents Page
1 Features.............................................................. 1
2 Description.......................................................... 1
3 Pin Information........................... ...... ....... ...... ...... 3
4 Hardware Architecture........................................ 7
4.1 DSP1627 Architectural Overview............. 7
4.2 DSP1600 Core Architectural Overview .. 10
4.3 Interrupts and Trap................................. 11
4.4 Memory Maps and Wait-States.............. 16
4.5 External Memory Interface (EMI)............ 18
4.6 Bit Manipulation Unit (BMU)................... 19
4.7 Serial I/O Units (SIOs)............................ 19
4.8 Parallel Host Interface (PHIF)................. 22
4.9 Bit Input/Output Unit (BIO)...................... 23
4.10 Timer ...................................................... 23
4.11 JTAG Test Port....................................... 24
4.12 Clock Synthesis...................................... 26
4.13 Power Management ............................... 29
5 Software Architecture ....................................... 36
5.1 Instruction Set......................................... 36
5.2 Register Settings .................................... 45
5.3 Instruction Set Formats .......................... 55
6 Signal Descriptions ........................................... 61
6.1 System Interface..................................... 61
6.2 External Memory Interface ..................... 63
6.3 Serial Interface #1 .................................. 64
6.4 Parallel Host Interface or Serial
Interface #2 and Control I/O Interface.... 65
6.5 Control I/O Interface ............................... 65
6.6 JTAG Test Interface ............................... 66
7 Mask-Programmable Options ........................... 67
7.1 Input Clock Options ................................ 67
7.2 Memory Map Options ............................. 67
7.3 ROM Security Options............................ 67
8 Device Characteristics ...................................... 68
8.1 Absolute Maximum Ratings.................... 68
8.2 Handling Precautions ............................. 68
8.3 Recommended Operating Conditions .... 68
8.4 Package Thermal Considerations .......... 69
9 Electrical Characteristics and Requirements .... 70
9.1 Power Dissipation................................... 73
10 Timing Characteristics for 5 V Operation.......... 75
10.1 DSP Clock Generation ........................... 76
10.2 Reset Circuit........................................... 77
10.3 Reset Synchronization............................ 78
10.4 JTAG I/O Specifications.......................... 79
10.5 Interrupt .................................................. 80
10.6 Bit Input/Output (BIO) ............................. 81
10.7 External Memory Interface...................... 82
10.8 PHIF Specifications ................................ 86
10.9 Serial I/O Specifications.......................... 92
10.10 Multiprocessor Communication .............. 97
11 Timing Characteristics for 3.0 V Operation ....... 98
11.1 DSP Clock Generation............................ 99
11.2 Reset Circuit......................................... 100
11.3 Reset Synchronization....... ...... ....... ...... 101
11.4 JTAG I/O Specifications........................ 102
11.5 Interrupt ................................................ 103
11.6 Bit Input/Output (BIO) ........................... 104
11.7 External Memory Interface.................... 105
11.8 PHIF Specifications .............................. 109
11.9 Serial I/O Specifications........................ 115
11.10 Multiprocessor Communication ............ 120
12 Timing Characteristics for 2.7 V Operation ..... 121
12.1 DSP Clock Generation.......................... 122
12.2 Reset Circuit......................................... 123
12.3 Reset Synchronization....... ...... ....... ...... 124
12.4 JTAG I/O Specifications........................ 125
12.5 Interrupt ................................................ 126
12.6 Bit Input/Output (BIO) ........................... 127
12.7 External Memory Interface.................... 128
12.8 PHIF Specifications .............................. 132
12.9 Serial I/O Specifications........................ 138
12.10 Multiprocessor Communication ............ 143
13 Crystal Electrical Characteristics and
Requirements.................................................. 144
13.1 External Components for the Crystal
Oscillator............................................... 144
13.2 Power Dissipation................................. 144
13.3 LC Network Design for Third
Overtone Crystal Circuits...................... 147
13.4 Frequency Accuracy Considerations.... 149
14 Outline Diagrams ............................................ 152
14.1 100-Pin BQFP (Bumpered Quad
Flat Pack).............................................. 152
14.2 100-Pin TQFP (Thin Quad Flat Pack)... 153
2 Lucent Technologies Inc.
Page 3
Data Sheet March 2000 DSP1627 Digital Signal Processor

3 Pin Information

SS
V DB4 DB3 DB2 DB1 DB0
IO
ERAMHI
DD
V
ERAMLO
EROM
RWN
SS
V
EXM AB15 AB14
DD
V
AB13 AB12 AB11 AB10
AB9 AB8 AB7
SS
V
20
30
DD
V
DB5
40
DB6
V
SS
DB10
DB9
DB8
DB7
DB11
DB12
DB13
10
DB14
DB15
VDDIBF1
100
OBE1
SS
V
DI1
ILD1
OLD1
OCK1
ICK1
DO1
SYNC1
90
SS
V
DD
V SADD1 DOEN1
PIN #1 IDENTIFIER ZONE
OCK2/PCSN DO2/PSTAT SYNC2/PBSEL ILD2/PIDS OLD2/PODS
80
IBF2/PIBF OBE2/POBE ICK2/PB0 DI2/PB1
SS
DSP1627
V DOEN2/PB2 SADD2/PB3
DD
V IOBIT0/PB4 IOBIT1/PB5
70
IOBIT2/PB6 IOBIT3/PB7 VEC3/IOBIT4 VEC2/IOBIT5 VEC1/IOBIT6 VEC0/IOBIT7
SS
50
60
V
DD
V
SS
AB0
AB1
AB2
AB3
AB4
AB5
AB6
V
INT0
INT1
IACK
TRAP
STOP
DD
V
TCK
CKO
RSTB
TMS
TDO
DDA
TDI
V
CKI
CKI2
SSA
V
5-4218 (F).b
Figure 1. DSP1627 BQFP Pin Diagram
Lucent Technologies Inc. 3
Page 4
Data Sheet
DSP1627 Digital Signal Processor March 2000
3 Pin Information
VDDDB5
SS
1
V
DB4 DB3
DB2 DB1 DB0
ERAMHI
V
ERAMLO
EROM
RWN
V
EXM
AB15 AB14
V
AB13 AB12
AB11 AB10
AB9 AB8
AB7
V
IO
DD
10
SS
DD
20
SS
100
(continued)
DB6
DB7
DB8
30
DO1
SYNC1
SS
V
DD
V
DB9
DB10
VSSDB11
DB12
DB13
DB14
DB15
VDDOBE1
IBF1
VSSDI1
ILD1
90
OLD1
ICK1
OCK1
80
SADD1 DOEN1
OCK2/PCSN DO2/PSTAT
SYNC2/PBSEL
70
ILD2/PIDS OLD2/PODS IBF2/PIBF OBE2/POBE ICK2/PB0 DI2/PB1
SS
DSP1627
V DOEN2/PB2
SADD2/PB3
DD
V
60
IOBIT0/PB4 IOBIT1/PB5
IOBIT2/PB6 IOBIT3/PB7 VEC3/IOBIT4 VEC2/IOBIT5
VEC1/IOBIT6 VEC0/IOBIT7
SS
40
50
V
DD
V
AB6
AB5
AB4
AB3
AB2
AB0
AB1
SS
V
INT1
INT0
IACK
STOP
TRAP
RSTB
DD
V
TCK
CKO
TMS
TDO
DDA
TDI
V
CKI
CKI2
SSA
V
5-4219 (F).b
Figure 2. DSP1627 TQFP Pin Diagram
4 Lucent Technologies Inc.
Page 5
Data Sheet March 2000 DSP1627 Digital Signal Processor
3 Pin Information
(continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of pins 61 and 62 (TQFP pins 48 and 49) are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on all I and I/O type pins are designed to remain at full CMOS levels when not driven by the DSP.
Table 1. Pin Descriptions
BQFP Pin TQFP Pin Symbol Type Name/Function
1, 2, 3, 4,
5, 7, 8, 9, 10, 11, 12, 15, 16, 17,
18, 19
88, 89, 90, 91, 92, 94, 95, 96, 97,
98, 99, 2,
3, 4, 5, 6 20 7 IO 21 8 ERAMHI 23 10 ERAMLO 24 11 EROM 25 12 RWN
DB[15:0] I/O* External Memory Data Bus DB[15:0].
Data Address 0x4000 to 0x40FF I/O Enable.
O
Data Address 0x8000 to 0xFFFF External RAM Enable.
O
Data Address 0x4100 to 0x7FFF External RAM Ena ble.
O
Program Address External ROM Enable.
O
Read/Write Not.
O
27 14 EXM I External ROM Enable.
28, 29, 31, 32, 33, 34, 35, 36, 37, 40, 41, 42, 43, 44, 45,
46
15, 16, 18, 19, 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32,
33
AB[15:0] O* External Memory Address Bus 15—0.
47 34 INT1 I Vectored Interrupt 1. 48 35 INT0 I Vectored Interrupt 0. 50 37 IACK O* Interrupt Acknowledge. 51 38 STOP I STOP Inpu t Clock. 52 39 TRAP I/O* Nonmaskable Program Trap/Breakpoint Indication. 53 40 RSTB I Reset Bar. 54 41 CKO
Processor Clock Output.
O
56 43 TCK I JTAG Text Clock.
57 44 TMS 58 45 TDO 59 46 TDI
JTAG Test Mode Select.
I
§
JTAG Test Data Output.
O
JTAG Test Data Input.
I
Mask-Programmable Input Clock Option
CMOS Small
Signal
61 48 CKI** I CKI V 62 49 CKI2** I V
SSA
AC
V
CM
XLO, 10 pF capacitor to V
XHI, 10 pF capacitor to V
Crystal
Oscillator CMOS
CKI
SS
Open
SS
65 52 VEC0/IOBIT7 I/O* Vectored Interrupt Indication 0/Status/Control Bit 7. 66 53 VEC1/IOBIT6 I/O* Vectored Interrupt Indication 1/Status/Control Bit 6. 67 54 VEC2/IOBIT5 I/O* Vectored Interrupt Indication 2/Status/Control Bit 5. 68 55 VEC3/IOBIT4 I/O* Vectored Interrupt Indication 3/Status/Control Bit 4.
* 3-states when RSTB = 0, or by JTAG control. † 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running. ‡ Pull-up devices on input.
§ 3-states by JTAG control. ** See Section 7, Mask-Programmable Options. †† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
Lucent Technologies Inc. 5
Page 6
Data Sheet
DSP1627 Digital Signal Processor March 2000
3 Pin Information
(continued)
Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions.
Table 1. Pin Descriptions
(continued)
BQFP Pin TQFP Pin Symbol Type Name/Function
69 56 IOBIT3/PB7 I/O* Status/Control Bit 3/PHIF Data Bus Bit 7. 70 57 IOBIT2/PB6 I/O* Status/Control Bit 2/PHIF Data Bus Bit 6. 71 58 IOBIT1/PB5 I/O* Status/Control Bit 1/PHIF Data Bus Bit 5. 72 59 IOBIT0/PB4 I/O* Status/Control Bit 0/PHIF Data Bus Bit 4. 74 61
SADD2/PB3
††
I/O* SIO2 Multiprocessor Address/PHIF Data Bus Bit 3. 75 62 DOEN2/PB2 I/O* SIO2 Data Output Enable/PHIF Data Bus Bit 2. 77 64 DI2/PB1 I/O* SIO2 Data Input/PHIF Data Bus Bit 1. 78 65 ICK2/PB0 I/O* SIO2 Input Clock/PHIF Data Bus Bit 0. 79 66 OBE2/POBE O* SIO2 Output Buffer Empty/PHIF Output Buffer Empty. 80 67 IBF2/PIBF O* SIO2 Input Buffer Full/PHIF Input Buffer Full. 81 68 OLD2/PODS I/O* SIO2 Output Load/PHIF Output Data Strobe. 82 69 ILD2/PIDS I/O* SIO2 Input Load/PHIF Input Data Strobe. 83 70 SYNC2/PBSEL I/O* SIO2 Multiprocessor Synchronization/PHIF Byte Select. 84 71 DO2/PSTAT I/O* SIO2 Data Output/PHIF Status Register Select. 85 72 OCK2/PCSN I/O* SIO2 Output Clock/PHIF Chip Select Not. 86 73 DOEN1 I/O* SIO1 Data Output Enable. 87 74
SADD1
††
I/O* SIO1 Multiprocessor Address. 90 77 SYNC1 I/O* SIO1 Multiprocessor Synchronization. 91 78 DO1 O* SIO1 Data Output. 92 79 OLD1 I/O* SIO1 Output Load. 93 80 OCK1 I/O* SIO1 Output Clock. 94 81 ICK1 I/O* SIO1 Input Clock. 95 82 ILD1 I/O* SIO1 Input Load. 96 83 DI1 I SIO1 Data Input. 98 85 IBF1 O* SIO1 Input Buffer Full. 99 86 OBE1 O* SIO1 Output Buffer Empty.
6, 15, 26,
38, 49, 64,
76, 89, 97
14, 22, 30, 39, 55, 73,
88, 100
60 47 V 63 50 V
93, 1, 13,
25, 36, 51,
63, 76, 84
100, 9, 17, 26, 42, 60,
75, 87
V
V
DDA SSA
SS
DD
P Ground.
P Power Supply.
P Analog Power Supply. P Analog Ground.
* 3-states when RSTB = 0, or by JTAG control. † 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0.
§ Pull-up devices on input. ‡ 3-states by JTAG control. ** See Section 7, Mask-Programmable Options. †† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.
6 Lucent Technologies Inc.
Page 7
Data Sheet March 2000 DSP1627 Digital Signal Processor

4 Hardware Architecture

The DSP1627 device is a 16-bit, fixed-point program­mable digital signal processor (DSP). The DSP1627 consists of a DSP1600 core to ory and peripherals. Added architectural features give the DSP1627 high program efficiency for signal coding applications.

4.1 DSP1627 Architectural Overview

Figure 3 shows a block diagram of the DSP1627. The fol­lowing modules make up t he D SP1627.

DSP1600 Core

The DSP1600 core is the heart of the DSP1627 chip. The core contains data and address arithmetic units, an d control for on-chip memory and peripherals. The core provides support for external memory wait-states and on­chip, dual-port RAM and features vectored interrupts and a trap mechanism.

Dual-Port RAM (DPRAM)

This module contains six banks of zero wait-state mem­ory. Each bank consists of 1K 16-bit words and has sep­arate address and data ports to the instruction/coefficient and data memory space s. A program can reference memory from either space. The DSP1600 core automat­ically performs the required multiplexing. If references to both ports of a single bank are made simultaneously, the DSP1600 core automatically inserts a wait-state and per­forms the data port access first, followed by the instruc­tion/coefficient port access.
A program can be downloaded from slow, off-chip mem­ory into DPRAM, and then executed without wait-states. DPRAM is also useful for improving convolution perf or­mance in cases where the coefficients are adaptive. Since DPRAM can be dow nloaded through the JTAG port, full-speed remote in -c irc uit em ulation is possible. DPRAM can also be used for downloading self-test code via the JTAG port.

Read-Only Memory (ROM)

The DSP1627x36 contains 36K 16-bit words of zero wait-state mask-progr am m able ROM for program and fixed coefficients. Simila rly , the DS P1627x32 has 32K 16-bit words of ROM and acc es s to 16 Kw ords of exter­nal ROM.

External Memory Multiplexer (EMUX)

The EMUX is used to connec t the DS P1627 to external memory and I/O devices. I t supports read/write opera ­tions from/to instruction/coefficient memory (X memory space) and data memory (Y memory space). The DSP1600 core automatically controls the EMUX. Instruc-
ether with on-chip mem-
g
tions can transparently refere nc e ex t ernal memory from either set of internal buses. A sequencer allows a single instruction to access both the X and the Y external mem­ory spaces.

Clock Synthesis

The DSP powers up with a 1X input clock (CKI/CKI2) as the source for the processor clock. An on-chip clock syn­thesizer (PLL) can also be used to generate the system clock for the DSP, which will run at a freque nc y mu lti ple of the input clock. The clock s y nt hes iz er is deselected and powered down on reset. For low-power operation, an internally generated slow clo c k can be used to drive the DSP. If both the clock synthesizer and the internally gen­erated slow clock are selec t ed, th e s low c loc k wi ll driv e the DSP; however, the synt hesizer will continue to run.
The clock synthesizer and other programmable cloc k sources are discussed in Section 4.12. The use of these programmable clock so urc es f or power management is discussed in Section 4.13.

Bit Manipulation Unit (BMU)

The BMU extends the DSP1600 core instruction set to provide more efficient bit operations on accumula to rs . The BMU contains logic for barrel shifting, normalization, and bit field insertion/extraction. The unit also contains a set of 36-bit alternate accu m ulators. The data in the al­ternate accumulators can be shuffled with the data in the main accumulators. Flags returned by the BMU mesh seamlessly with the DSP1600 conditional instructions.

Bit Input/Output (BIO)

The BIO provides conve nient and efficient monitorin g and control of eight individually configurable pins. When configured as outputs, th e pins can be individually set, cleared, or toggled. When configured as inputs, individu­al pins or combinations of pins can be tested for patterns. Flags returned by the BIO me s h se am lessly with condi­tional instructions.

Serial Input/Output Units (SIO and SIO2)

SIO and SIO2 offer asynchronous, full-duplex, do uble­buffered channels that operate at up to 25 Mbits/s (for 20 ns instruction cycle in a nonmultiprocessor configura­tion), and easily interface with other Lucent Technologies fixed-point DSPs in a multiple-processor environm ent. Commercially availab le c odecs and time-division mu lti ­plex (TDM) channels can be interfaced to the serial I/O ports with few, if any, additional components. SIO2 is identical to SIO.
An 8-bit serial protocol channel may be transmitted in ad­dition to the address of the ca lled processor in multipro­cessor mode. This feature is useful for transmitting high­level framing informatio n or f or error detection and cor­rection. SIO2 and BIO are pin-multiplexed with the PHIF.
Lucent Technologies Inc. 7
Page 8
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
AB[15:0]DB[15:0]
ioc
DUAL-PORT
RAM
6K x 16
CKI
CKI2
CKO RSTB STOP TRAP
INT[1:0]
IACK
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSTAT OLD2 OR PODS OCK2 OR PCSN OBE2 OR POBE
SYNC2 OR PBSEL
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF DOEN2 OR PB2 SADD2 OR PB3
IO BIT[3:0] OR PB[7:4]
M U X
(continued)
RWN EXM EROM ERAMHI
EXTERNAL MEMORY INTERFACE & EMUX
YAB YDB XDB XAB BMU
DSP1600 CORE
PHIF phifc
*
PSTAT
pdx0(IN)
pdx0(OUT)
I/O
IDB
powerc
BIO
sbit cbit
36K/32K x 16
aa0 aa1
ar0 ar1 ar2 ar3
pllc
ERAMLO
ROM
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
JTAG
BOUNDARY SCAN
jtag
*
JCON
*
ID
*
BYPASS
HDS
BREAKPOINT
TRACE
TIMER
timerc timer0
sdx(OUT)
sdx(IN)
*
*
SIO
srta
tdms
sioc
saddx
*
TDO TDI
TCK TMS
TRST
DI1 ICK1 ILD1 IBF1 DO1 OCK1 OLD1 OBE1 SYNC1 SADD1 DOEN1
5-4142 (F).f
* These registers are accessible through the pins only. † 36K x 16 for the DSP1627x36; 32K x 16 for the DSP1627x32.
Figure 3. DSP1627 Block Diagram
8 Lucent Technologies Inc.
Page 9
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
Table 2. DSP1627 Block Diagram Legend
Symbol Name
aa<0—1> Alternate Accumulators.
ar<0—3> Auxiliary BMU Registers.
BIO Bit Input/Output Unit.
BMU Bit Manipulation Unit .
BREAKPOINT Four Instruction Breakpoint Registers.
BYPASS JTAG Bypass Register.
cbit Control Register for BIO.
EMUX External Memory Multiplexer.
HDS Hardware Development System.
ID JTAG Device Identification Register.
IDB Internal Data Bus.
ioc I/O Configuration Register.
JCON JTAG Configuration Registers.
jtag 16-bit Serial/Parallel Register.
pdx0(in) Parallel Data Transmit Input Register 0.
pdx0(out) Parallel Data Transmit Output Register 0.
PHIF Parallel Host Interface. phifc Parallel Host Interface Control Register.
pllc Phase-Locked Loop Control Register.
powerc Power Control Register.
PSTAT Parallel Host Interface Status Register.
ROM Internal ROM (36 Kwords for DSP1627x36, 32 Kwords for DSP1627x32).
saddx Multiprocessor Protocol Register.
saddx2 Multiprocessor Protocol Register for SIO2.
sbit Status Register for BIO.
sdx(in) Serial Data Transmit Input Register. sdx2(in) Serial Data Transmit Input Register for SIO2. sdx(out) Serial Data Transmit Output Register.
sdx2(out) Serial Data Transmit Output Register for SIO2.
SIO Serial Input/Output Unit.
SIO2 Serial Input/Output Unit #2.
sioc Serial I/O Control Register.
sioc2 Serial I/O Control Register for SIO2.
srta Serial Receive/Transmit Address Register. srta2 Serial Receive/Transmit Address Register for SIO2. tdms Serial I/O Time-division Multiplex Signal Control Register.
tdms2 Serial I/O Time-division Multiplex Signal Control Register for SIO2.
TIMER Programmab le Time r.
timer0 Timer Running Count Register.
timerc Timer Control Register.
TRACE Program Discontinuity Trace Buffer.
XAB Program Memory Address Bus. XDB Program Memory Data Bus. YAB Data Memory Address Bus. YDB Data Memory Data Bus.
(continued)
Lucent Technologies Inc. 9
Page 10
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture

Parallel Host Interface (PHIF)

The PHIF is a passive, 8-bit parallel port which can in­terface to an 8-bit bus containing other Lucent Technol­ogies DSPs (e.g., DSP1620, DSP1627, DSP1628, DSP1629, DSP1611, DSP1616, DSP1617, DSP1618), microprocessors, or peripheral I/O devices. The PHIF port supports either as 8-bit or 16-bit transfers, configured in software. The port data rate depends upon the instruction cycle rate. A 25 ns instruction cycle allows the PHIF to support data rates up to 11.85 Mbytes/s, assuming the external host device can transfer 1 byte of data in 25 ns.
The PHIF is accessed in two basic modes: 8-bit or 16-bit mode. In 16-bit mode, the host determines an ac­cess of the high or low byte. In 8-bit mode, only the low byte is accessed. Software-programmable features al­low for a glueless host interfac e to microprocessors (see Section 4.8, Parallel Host Interface).

Timer

Motorola
or
Intel
(continued)
protocols, as well
In systems with multiple processors, the processors may be configured such that any processor reaching a breakpoint will cause all the other processors to be trapped (see Section 4.3, Interrupts and Trap).

Pin Multiplexing

In order to allow flexible device interfacing while main­taining a low package pin count, the DSP1627 multi­plexes 16 package pins between BIO, PHIF, VEC[3:0], and SIO2.
Upon reset, the vectored interrupt indication signals, VEC[3:0], are connected to the package pins while IOBIT[4:7] are disconnected. Setting bit 12, EBIOH, of the ioc register connects IOBIT[4:7] to the package pins and disconnects VEC[3:0].
Upon reset, the parallel host interface (PHIF) is con­nected to the package pins while the second serial port (SIO2) and IOBIT[3:0] are disconnected. Setting bit 10, ESIO2, of the ioc register connects the SIO2 and IOBIT[3:0] and disconnects the PHIF.

Power Management

The timer can be used to provide an interrupt at the ex­piration of a programmed interval. The interrupt may be single or repetitive. More than nine orders of magnitude of interval selection are provided. The timer may be stopped and restarted at any time.

Hardware Development System (HDS) Module

The on-chip HDS performs instruction breakpointing and branch tracing at full speed without additional off­chip hardware. Using the JTAG port, the breakpointing is set up, and the trace history is read back. The port works in conjunction with the HDS code in the on-chip ROM and the hardware and software in a remote com­puter. The HDS code must be linked to the user's appli­cation code and reside in the first 4 Kwords of ROM. The on-chip HDS cannot be used with the secure ROM masking option (see Section 7.3, ROM Security Op­tions).
Four hardware breakpoints can be set on instruction ad­dresses. A counter can be preset with the number of breakpoints to receive before trapping the core. Break­points can be set in interrupt service routines. Alternate­ly, the counter can be preset with the number of cache instructions to execute before trapping the core.
Every time the program branches instead of executing the next sequential instruction, the addresses of the in­structions executed before and after the branch are caught in circular memory. The memory contains the last four pairs of program discontinuities for hardware tracing.
Many applications, such as portable cellular terminals, require programmable sleep modes for power manage­ment. There are three different control mechanisms for achieving low-power operation: the powerc control reg­ister, the STOP pin, and the AWAIT bit in the alf register. The AWAIT bit in the alf r egister al lows the pr ocessor to go into a power-saving standby mode until an interrupt occurs. The powerc register configures various power­saving modes by controlling internal clocks and periph­eral I/O units. The STOP pin controls the internal pro­cessor clock. The various power management options may be chosen based on power consumption and/or wake-up latency requirements.

4.2 DSP1600 Core Architectural Overview

Figure 4 shows a block diagram of the DSP1600 core.

System Cache and Control Section (SYS)

This section of the core contains a 15-word cache mem­ory and controls the instruction sequencing. It handles vectored interrupts and traps, and also provides decod­ing for registers outside of the DSP1600 core. SYS stretches the processor cycle if wait-states are required (wait-states are programmable for external memory ac­cesses). SYS sequences downloading via JTAG of self­test programs to on-chip, dual-port RAM.
The cache loop iteration count can be specified at run time under program control as well as at assembly time.
10 Lucent Technologies Inc.
Page 11
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture

Data Arithmetic Unit (DAU)

The data arithmetic unit (DAU) contains a 16 x 16-bit parallel multiplier that generates a full 32-bit product in one instruction cycle. The product can be accumulated with one of two 36-bit accumulators. The accumulator data can be directly loaded from, or stored to, memory in two 16-bit words with optional saturation on overflow. The arithmetic logic unit (ALU) supports a full set of arithmetic and logical operations on either 16- or 32-bit data. A standard set of flags can be tested for condition­al ALU operations, branches, and subroutine calls. This procedure allows the processor to perform as a power­ful 16- or 32-bit microprocessor for logical and control applications. The available instruction set is fully com­patible with the DSP1617 instruction set. See Section
5.1 for more information on the instruction set. The user also has access to two additional DAU regis-
ters. The psw register contains status information from the DAU (see Table 26, Processor Status Word Regis­ter). The arithmetic control register, auc, is used to con­figure some of the features of the DAU (see Table 27) including single-c ycle squar i ng. Th e auc regis ter align­ment field supports an arithmetic shift left by one and left or right by two. The auc register is cleared by reset.
The counters c0 to c2 are signed, 8 bits wide, and may be used to count events such as the number of times the program has executed a sequence of code. They are controlled by the conditional instructions and pro­vide a convenient method of program looping.
(continued)
The YAAU allows direct (or indexed) addressing of data memory. In direct addressing, the 16-bit base register (ybase) supplies the 11 most significant bits of the ad­dress. The direct data instruction supplies the remaining 5 bits to form an address to Y memory space and also specifies one of 16 registers for the source or destina­tion.

X Space Address Arithmetic Unit (XAAU)

The XAAU supports high-speed, register-indirect, in­struction/coefficient memory addressing with postmodi­fication of the register. The 16-bit pt register is used for addressing coefficients. The signed register i holds a user-defined postincrement. A fixed postincrement of +1 is also available. Register PC is the program counter. Registers pr and pi hold the return address for subroutine calls and interrupts, respectively.
The XAAU decodes the 16-bit instruction/coefficient ad­dress and produces enable signals for the appropriate X memory segment. The addressable X segments are internal ROM (up to 36 Kwords for the DSP1627x36, up to 32 Kwords for the DSP1627x32), six 1K banks of DPRAM, and external ROM.
The locations of these memory segments depend upon the memory map selected (see Table 5). A security mode can be selected by mask option. This prevents unauthorized access to the contents of on-chip ROM (see Section 7, Mask-Programmable Options).

4.3 Interrupts and Trap

Y Space Address Arithmetic Unit (YAAU)

The YAAU supports high-speed, register-indirect, com­pound, and direct addressing of data (Y) memory. Four general-purpose, 16-bit registers, r0 to r3, are available in the YAAU. These registers can be used to supply the read or write addresses for Y space data. The YAAU also decodes the 16-bit data memory address and out­puts individual memory enables for the data access. The YAAU can address the six 1 Kword banks of on­chip DPRAM or three external data memory segments. Up to 48 Kwords of off-chip RAM are addressable, with 16K addresses reserved for internal RAM.
Two 16-bit registers, rb and re, allow zero-overhead modulo addressing of data for efficient filter implemen­tations. Two 16-bit signed registers, j and k, are used to hold user-defined postmodification increments. Fixed increments of +1, –1, and +2 are also available. Four compound-addressing modes are provided to make read/write operations more effi cient.
Lucent Technologies Inc. 11
The DSP1627 supports prioritized, vectored interrupts and a trap. The device has eight internal hardware sources of program interrupt and two external interrupt pins. Additionally, there is a trap pin and a trap signal from the hardware development system (HDS). A soft­ware interrupt is available through the
icall
The Each of these sources of interrupt and trap has a unique vector address and priority assigned to it. DSP16A in­terrupt compatibility is not maintained.
The software interrupt and the traps are always enabled and do not have a corresponding bit in the ins register. Other vectored interrupts are enabled in the inc register (see Table 29, Interrupt Control (inc) Register) and monitored in the ins register (see Table 30, Interrupt Status (ins) Register). When the DSP1627 goes into an interrupt or trap service routine, the IACK pin is assert­ed. In addition, pins VEC[3:0] encode which interrupt/ trap is being serviced. Table 4 details the encoding used for VEC[3:0].
instruction is reserved for use by the HDS.
icall
instruction.
Page 12
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
CONTROL
ins (16) inc (16)
x (16)
16 x 16 MPY
SHIFT (–2, 0, 1, 2)
yh (16)
p (32)
yl (16)
32
(continued)
CACHE
cloop (7)
alf (16)
mwait (16)
DAU
SYS
ADDER
pc (16)
pt (16)
i (16)
MUX
j (16)
k (16)
1
pr (16) pi (16)
MUX
XAAU
BRIDGE
–1, 0, 1, 2
XDB
XAB
IDB
YDB
YAAU
MUX
ALU/SHIFT
a0 (36) a1 (36)
16
EXTRACT/SAT
c0 (8)
36
c1 (8) c2 (8)
auc (16) psw (16)
re (16)
CMP
ybase (16)
Figure 4. DSP1600 Core Block Diagram
ADDER
YAB
rb (16)
MUX
r0 (16) r1 (16) r2 (16) r3 (16)
5-1741 (F).b
12 Lucent Technologies Inc.
Page 13
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
Table 3. DSP1600 Core Block Diagram Legend
Symbol Name
16 x 16 MPY 16-bit x 16-bit Multiplier.
a0—a1
alf AWAIT, LOWPR, Flags.
ALU/SHIFT Arithmetic Logic Unit/Shifter.
auc Arithmetic Unit Control.
c0—c2 Counters 0—2.
cloop Cache Loop Count.
CMP Comparator.
DAU Digital Arithmetic Unit.
i Increment Register for the X Address Space.
IDB Internal Data Bus.
inc Interrupt Control. ins Interrupt Status.
j Increment Register for the Y Address Space.
k Increment Register for the Y Address Space.
MUX Multiplexer.
mwait External Memory Wait-states Register.
p Product Register (16-bit halves specified as p, pl).
PC Program Counter.
pi Program Interrupt Return Register. pr Program Return Register.
psw Processor Status Word.
pt X Address Space Pointer.
r0—r3 Y Address Space Pointers.
rb Modulo Addressing Register (begin address ). re Modulo Addressing Register (end addres s).
SYS System Cache and Control Section.
x Multiplier Input Register.
XAAU X Space Address Arithmetic Unit.
XAB X Space Address Bus. XDB X Space Data Bus.
YAAU Y Space Address Arithmetic Unit.
YAB Y Space Address Bus. YDB Y Space Data Bus.
ybase Direct Addressing Base Register.
y DAU Register (16-bit halves sp ec ifi ed as y, yl ).
* F3 ALU instructions with immediates require specifying the high half of the accumulators as a0h and a1h.
Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l)
(continued)
*
.
Lucent Technologies Inc. 13
Page 14
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture

Interruptibility

Vectored interrupts are serviced only after the execution of an interruptible instruction. If more than one vectored interrupt is asserted at the same time, the interrupts are serviced sequentially according to their assigned priori­ties. See Table 4 for the priorities assigned to the vec­tored interrupts. Interrupt service routines, branch and conditional branch instructions, cache loops, and in­structions that only decrement one of the RAM pointers, r0 to r3 (e.g., *r3
A trap is similar to an interrupt, but it gains control of the processor by branching to the trap service routine even when the current instruction is noninterruptible. It may not be possible to return to normal instruction execution from the trap service routine since the machine state cannot always be saved. In particular, program execu­tion cannot be continued from a trapped cache loop or interrupt service routine. While in a trap service routine, another trap is ignored.
When set to 1, the status bits in the ins register indicate that an interrupt has occurred. The processor must reach an interruptible state (completion of an interrupt­ible instruction) before an enabled vectored interrupt will be acted on. An interrupt will not be serviced if it is not enabled. Polled interrupt service can be implemented by disabling the interrupt in the inc register and then polling the ins register for the expected event.

Vectored Interrupts

Tables 29 and 30 show the inc and ins registers. A logic 1 written to any bit of inc enables (or unmasks) the as­sociated interrupt. If the bit is cleared to a logic 0, the in­terrupt is masked. Note that neither the software interrup t nor traps can be masked.
The occurrence of an interrupt that is not masked will cause the program execution to transfer to the memory location pointed to by that interrupt's vector address, as­suming no other interrupt is being serviced (see Table 4, Interrupt Vector Table). The occurrence of an inter­rupt that is masked causes no automatic processor ac­tion, but will set the corresponding status bit in the ins register. If a masked interrupt occurs, it is latched in the ins register, but the interrupt is not taken. When un­latched, this latched interrupt will initiate automatic pro­cessor interrupt action. See the
Digital Signal Processor Information Manual
detailed description of the interrupts.
− −
), are not interruptible.
(continued)
DSP1611/17/18/27
for a more

Signaling Interrupt Service Status

Five pins of DSP1627 are devoted to signaling interrupt service status. The IACK pin goes high while any inter­rupt or user trap is being serviced, and goes low when the iretur n instruct ion fr om the se rvice ro utine is issued. Four pins, VEC[3:0], carry a code indicating which of the interrupts or trap is being serviced. Table 4 contains the encodings used by each interrupt.
Traps due to HDS breakpoints have no effect on either the IACK or VEC[3:0] pins. Instead, they show the inter­rupt state or interrupt source of the DSP when the trap occurred.

Clearing Interrupts

The PHIF interrupts (PIBF and POBE) are cleared by reading or writing the parallel host interface data trans­mit registers pdx0[in] and pdx0[out], respectively. The SIO and SIO2 interrupts (IBF, IBF2, OBE, and OBE 2) are cleared by reading or writing, as appropriate, the se­rial data registers sdx[in], sdx2[in], sdx[out], and sdx2[out]. The JTAG interrupt (JINT) is cleared by read­ing the jtag register.
Three of the vectored interrupts are cleared by writing to the ins register. Writing a 1 to the INT0, INT1, or TIME bits in the ins will cause the corresponding interrupt sta­tus bit to be cleared to a logic 0. The status bit for these vectored interrupts is also cleared when the ireturn in­struction is executed, leaving set any other vectored in­terrupts that are pending.

Traps

The TRAP pin of the DSP1627 is a bidirectional signal. At reset, it is configured as an input to the processor. Asserting the TRAP pin will force a user trap. The trap mechanism is used for two purposes. It can be used by an application to rapidly gain control of the processor for asynchronous tim e-cr it ical event hand li ng (typi c all y for catastrophic error recovery). It is also used by the HDS for breakpointing and gaining control of the processor. Separate vectors are provided for the user trap (0x46) and the HDS trap (0x3). Traps are not maskable.
14 Lucent Technologies Inc.
Page 15
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
Table 4. Interrupt Vector Table
Source Vector Priority VEC[3:0] Issued by
No Interrupt 0x0
Software Interrupt 0x2 1 0x1 icall
INT0 0x1 2 0x2 pin
JINT 0x42 3 0x8 jtag in
INT1 0x4 4 0x9 pin
TIME 0x10 7 0xc timer
IBF2 0x14 8 0xd SIO2 in
OBE2 0x18 9 0xe SIO2 out Reserved 0x1c 10 0x0 — Reserved 0x20 11 0x1 — Reserved 0x24 12 0x2
IBF 0x2c 14 0x3 SIO in
OBE 0x30 15 0x4 SIO out
PIBF 0x34 16 0x5 PHIF in
POBE 0x38 17 0x6 PHIF out
TRAP from HDS 0x3 18 TRAP from User 0x46 19 = highest 0x7 pin
* Traps due to HDS breakpoints have no effect on VEC[3:0] pins.
(continued)
*
breakpoint, jtag, or pin
A trap has four cycles of latency. At most, two instruc­tions will execute from the time the trap is received at the pin to when it gains control. An instruction that is ex­ecuting when a trap occurs is allowed to complete be­fore the trap service routine is entered. (Note that the instruction could be lengthened by wait-states.) During normal program execution, the pi register contains ei­ther the address of the next instruction (two-cycle in­struction executing) or the address following the next instruction (one-cycle instruction executing). In an inter­rupt service routine, pi contains the interrupt return ad­dress. When a trap occurs during an interrupt service routine, the value of the pi register may be overwritten. Specifically, it is not possible to return to an interrupt service routine from a user trap (0x46) service routine. Continuing program execution when a trap occurs du r­ing a cache loop is also not possible.
The HDS trap causes circuitry to force the program memory map to MA P1 (with on-chi p ROM starting at ad­dress 0x0) when the trap is taken. The previous memo­ry map is restored when the trap service routine exits by issuing an ireturn. The map is forced to MAP1 because the HDS code, if present, resides in the on-chip ROM.
Using the Lucent Technologies development tools, the TRAP pin may be configured to be an output, or an input vectoring to address 0x3. In a multiprocessor environ­ment, the TRAP pins of all the DSPs present can be tied together. During HDS operations, one DSP is selected by the host software to be the master. The master pro­cessor's TRAP pin is configured to be an output.
The TRAP pins of the slave processors are configured as inputs. When the master processor reaches a break­point, the master's TRAP pin is asserted. The slave pro­cessors will respond to their TRAP input by beginning to execute the HDS code.

AWAIT Interrupt (Standby or Sleep Mode)

Setting the AWAIT bit (bit 15) of the alf register (alf = 0x8000) caus es th e proc esso r to go in to a po wer ­saving standby or sleep mode. Only the minimum cir­cuitry on the chip required to process an incoming inter­rupt remains active. After the AWAIT bit is set, one additional instruction will be executed before the stand­by power-s av in g m ode is ent e re d. A PH IF or SI O w or d transfer will complete if already in progress. The AWAIT bit is reset when the first interrupt occurs. The chip then wakes up and continues executing.
nop
Two AWAIT bit is set. The first cuted before sleeping; the second will be executed after the interrupt signal awakens the DSP and before the in­terrupt service routine is executed.
The AWAIT bit should be set from within the cache if the code which is executing resides in external ROM where more than one wait-state has been programmed. This ensures that an interrupt will not disturb the device from completely entering the sleep state.
instructions should be programmed after the
nop
(one cycle) will be exe-
Lucent Technologies Inc. 15
Page 16
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
For additional power savings, set ioc = 0x0180 and tim­erc = 0x0040 in addition to setting alf = 0x8000. This will hold the CKO pin low and shut down the timer and pres­caler (see Table 38 and Table 31).
For a description of the control mechanisms for putting the DSP into low-power modes, see Section 4.13, Pow­er Management.
(continued)

4.4 Memory Maps and Wait-States

The DSP1600 core implements a modified Harvard ar­chitecture that has separate on-chip 16-bit address and data buses for the instruction/coefficient (X) and data (Y) memory spaces. Table 5 shows the instruction/coef­ficient memory space maps for both the DSP1627x36 and DSP1627x32.
The differences between the x36 and x32 memory maps can be seen by comparing the respective MAP1 and MAP3. For instance, MAP1 of the x36 provides for 36 Kwords of IROM and 6 Kwords of dual-port RAM (DPRAM), whereas MAP1 of the x32 provides for 32 Kwords of IROM, 6 Kwords of DPRAM, and 16 Kwords of EROM.
The DSP1627 provides a multiplexed external bus which accesses external RAM (ERAM) and ROM (ER­OM). Programmable wait-states are provided for exter­nal memory accesses. The instruction/coefficient memory map is configurable to provide application flex­ibility. Table 6 shows the data memory space, which has one map.

Instruction/Coefficient Memory Map Selection

In determining which memory map to use, the proces­sor evaluates the state of two parameters. The first is the LOWPR bit (bit 14) of the alf register. The LOWPR bit of the alf register is initialized to 0 automatically at re­set. LOWPR controls the starting address in memory assigned to the six 1K banks of dual-port RAM. If LOW­PR is low, internal dual-port RAM begins at address 0xC000. If LOWPR is high, internal dual-port RAM be­gins at address 0x0. LOWPR also moves IROM from 0x0 in MAP1 to 0x4000 in MAP3, and EROM from 0x0 in MAP2 to 0x4000 in MAP4.
The second parameter is the value at reset of the EXM pin (pin 27 or pin 14, depending upon the package type). EXM determines whether the internal 36 Kwords ROM (IROM) will be addressable in the memory map.
The Lucent Technologies development system tools, together with the on-chip HDS circuitry and the JTAG port, can independently set the memory map. Specifi­cally, during an HDS trap, the memory map is forced to
16 Lucent Technologies Inc.
MAP1. The user's map selection is restored when the trap service routine has completed execution.

MAP1

MAP1 has the IROM starting at 0x0 and six 1 Kword banks of DPRAM starting at 0xC000. Additionally, MAP1 for the x32 has 16 Kwords of EROM starting at 0x8000. MAP1 is used if DSP1627 has EXM low at re­set and the LOWPR parameter is programmed to zero. It is also used during an HDS trap.

MAP2

MAP2 differs from MAP1 in that the lowest 48 Kwords referenc e extern al ROM (ERO M). MAP2 i s used if EX M is high at reset, the LOWPR parameter is programmed to zero, and an HDS trap is not in progress.

MAP3

MAP3 has the six 1 Kword banks of DPRAM starting at address 0x0. In MAP3 of the x36, the 36 Kwords of IROM start at 0x4000. Similarly, for the x32, 32 Kwords of IROM start at 0x4000. Additionally, MAP3 for the x32 has 16 Kwords of EROM starting at 0xC000. MAP3 is used if EXM is low at reset, the LOWPR bit is pro­grammed to 1, and an HDS trap is not in progress. Note that this map is not available if the secure mask-pro­grammable option has been ordered.

MAP4

MAP4 differs from MAP3 in that addresses above 0x4000 reference external ROM (EROM). This map is used if the LOWPR bit is programmed to 1, an HDS trap is not in progress, and, either EXM is high during reset, or the secure mask-programmable option has been or­dered.
Whenever the chip is reset using the RSTB pin, the de­fault memory map will be MAP1 or MAP2, depending upon the state of the EXM pin at reset. A reset through the HDS will not reinitialize the alf register, so the previ­ous memory map is retained.

Boot from External ROM

After RSTB goes from low to high, the DSP1627 comes out of reset and fetches an instruction from address zero of the inst ruction/coefficient space. The physical location of address zero is determined by the memory map in effect. If EXM is high at the rising edge of RSTB, MAP2 is selected. MAP2 has EROM at location zero; thus, program execution begins from external memory. If EXM is high and INT1 is low when RSTB rises, the mwait register defaults to 15 wait-states for all external memory segments. If INT1 is high, the mwait register defaults to 0 wait-states.
Page 17
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
(continued)
Table 5. Instruction/Coefficient Memory Maps DSP1627x36
X Address AB[0:15] MAP 1
EXM = 0
LOWPR = 0
00x0000
4K 0x1000
IROM
(36K)
*
MAP 2
EXM = 1
LOWPR = 0
EROM
(48K)
LOWPR = 1
DPRAM
6K 0x1800 Reserved
12K 0x3000
MAP 3
EXM = 0
(6K)
(10K)
LOWPR = 1
Reserved
16K 0x4000 IROM 20K 0x5000
(36K)
24K 0x6000 28K 0x7000 32K 0x8000 36K 0x9000 Reserved 40K 0xA000
(12K) 44K 0xB000 48K 0xC000 DPRAM 52K 0xD000 Reserved
(6K) 54K 0xD800 Reserved 56K 0xE000
(10K)
DPRAM
(6K)
Reserved
(10K)
(12K)
60K—64K 0xFFFF
* MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. † LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map. ‡ MAP3 is not available if the secure mask-programmable option is selected.
MAP 4
EXM = 1
DPRAM
(6K)
(10K)
EROM
(48K)
DSP1627x32
X Address AB[0:15] MAP 1
EXM = 0
LOWPR = 0
0 0x0000
4K 0x1000
IROM (32K)
*
MAP 2
EXM = 1
LOWPR = 0
EROM
(48K)
LOWPR = 1
6K 0x1800 Reserved
12K 0x3000
DPRAM
MAP 3
EXM = 0
(6K)
(10K)
LOWPR = 1
Reserved
16K 0x4000 IROM 20K 0x5000
(32K)
24K 0x6000 28K 0x7000 32K 0x8000 EROM 36K 0x9000
(16K) 40K 0xA000 44K 0xB000 48K 0xC000 DPRAM 52K 0xD000
(6K)
54K 0xD800 Reserved 56K 0xE000
(10K)
DPRAM
(6K)
Reserved
(10K)
EROM
(16K)
60K—64K 0xFFFF
* MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine. † LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map. ‡ MAP3 is not available if the secure mask-programmable option is selected.
MAP 4
EXM = 1
DPRAM
(6K)
(10K)
EROM
(48K)
Lucent Technologies Inc. 17
Page 18
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
Data Memory Mapping Table 6. Data Memory Map (Not to Scale)
Decimal
Address
0 0x0000 DPRAM[1:6]
6K 0x1800 Reserved
16K 0x4000 IO
Address in
r0, r1, r2, r3
(continued)
Segment

4.5 External Memory Interface (EMI)

The external memory interface supports read/write op­erations from instruction/coefficient memory, data memory, and memory-mapped I/O devices. The DSP1627 provides a 16-bit external address bus, AB[15:0], and a 16-bit external data bus, DB[15:0]. These buses are multiplexed between the internal bus­es for the instruction/coefficient memory and the data memory. Four external memory segment enables, ERAMLO, IO, ERAMHI, and EROM, select the external memory segment to be addressed.
If a data memory location with an address between 0x4100 and 0x7FFF is addressed, ERAMLO is asserted low.
(10K)
If one of the 256 external data memory locations, with an address greater than or equal to 0x4000, and less than or equal to 0x40FF, is addressed, IO is asserted low. IO is intended for memory-mapped I/O.
If a data memory location with an address greater than or equal to 0x8000 is addressed, ERAMHI is asserted low. When the external instruction/coefficient memory is addressed, EROM is asserted low.
16,640 0x4100 E RA MLO
32K 0x8000 ERAMHI
64K – 1 0xFFFF
On the data memory side (see Table 6), the six 1K banks of dual-port RAM are located starting at address
0. Addresses from 0x4000 to 0x40FF reference a 256­word memory-mapped I/O segment (IO). Addresses from 0x4100 to 0x7FFF reference the low external data RAM segment (ERAMLO). Addresses above 0x8000 reference high external data RAM (ERAMHI).

Wait-States

The number of wait-states (from 0 to 15) used when ac­cessing each of the four external memory segments (ERAMLO, IO, ERAMHI, and EROM) is programmable in the mwait register (see Table 36). When the program references memory in one of the four external seg­ments, the internal multiplexer is automatically switched to the appropriate set of internal buses, and the associ­ated external enable of ERAMLO, IO, ERAMHI, or EROM is issued. The external memory cycle is auto­matically stretched by the number of wait-states config­ured in the appropriate field of the mwait register.
The flexibility provided by the programmable options of the external memory interface (see Table 36, mwait Register and Table 38, ioc Register) allows the DSP1627 to interface g luelessly with a variety of com­mercial memory chips.
Each of the four external memory segments, ERAMLO, IO, ERAMHI, and EROM, has a number of wait-states that is programmable (from 0 to 15) by writing to the mwait register. When the program references memory in one of the four external segments, the internal multi­plexer is automatically switched to the appropriate set of internal buses, and the associated external enable of ERAMLO, IO, ERAMHI, or EROM is issued. The exter­nal memory cycle is automatically stretched by the num­ber of wait-states in the appropriate field of the mwait register.
When writing to external memory, the RWN pin goes low for the external cycle. The external data bus, DB[15:0], is driven by the DSP1627 starting halfway through the cycle. The data driven on the external data bus is automatically held after the cycle unless an exter­nal read cycle immediately follows.
The DSP1627 has one external address bus and one external data bus for both memory spaces. Since some instructions provide the capability of simultaneous ac­cess to both X space and Y space, some provision must be made to avoid collisions for external accesses. The DSP1627 has a sequencer that does the external X ac­cess first, and then the external Y access, transparently to the programmer. Wait-states are maintained as
18 Lucent Technologies Inc.
Page 19
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
programmed in the mwait register. For example, let two instructions be executed: the first reads a coefficient from EROM and writes data to ERAM; the second reads a coefficient from EROM and reads data from ERAM. The sequencer carries out the following steps at the ex­ternal memory interface: read EROM, write ERAM, read EROM, and read ERAM. Each step is done in sequen­tial one-instruction cycle steps, assuming zero wait­states are programmed. Note that the number of in­struction cy cles taken by th e two in str uct ions is four . Al­so, in this case, the write hold time is zero.
The DSP1627 allows writing into external instruction/ coefficient memory. By setting bit 11, WEROM, of the ioc register (see Table 38), writing to (or reading from) data memory or memory-mapped I/O asserts the EROM strobe instead of ERAMLO, IO, or ERAMHI. Therefore, with WEROM set, EROM appears in both Y space (replacing ERAM) and X space, in its normal po­sition.
Bit 14 of the ioc register (see Table 38), EXTROM, may be used with WEROM to download to a full 64K of ex­ternal memory. When WEROM and EXTROM are both asserted, address bit 15 (AB15) is held low, aliasing the upper 32K of external memory into the lower 32K.
When an access to internal memory is made, the AB[15:0] bus holds the last valid external memory ad­dress. Asserting the RSTB pin low 3-states the AB[15:0] bus. After reset, the AB[15:0] value is undefined.
(continued)

4.6 Bit Manipulation Unit (BMU)

The BMU interfaces directly to the main accumulators in the DAU providing the following features:
Barrel shifting—logical and arithmetic, left and right shift
Normalization and extraction of exponent
Bit-field extraction and insertion
These features increase the efficiency of the DSP in ap­plications such as control or data encoding and decod­ing. For example, data packing and unpacking, in which short data words are packed into one 16-bit word for more efficient memory storage, is very easy.
In addition, the BMU provides two auxiliary accumula­tors, aa0 and aa1. In one instruction cycle, 36-bit data can be shuffled, or swapped, between one of the main accumulators and one of the alternate accumulators. The ar<0—3> registers are 16-bit registers that control the operations of the BMU. They store a value that de­termines the amount of shift or the width and offset fields for bit extraction or insertion. Certain operations in the BMU set flags in the DAU psw register and the alf register (see Table 26, Processor Status Word (psw) Register, and Table 35, alf Register). The ar<0—3> reg­isters can also be used as general-purpose registers.
The BMU instructions are detailed in Section 5.1. For a thorough description of the BMU, see the
18/27 Digital Signal Processor Information Manual
DSP1611/17/
.
The leading edge of the memory segment enables can be delayed by approximately one-half a CKO period by programming the ioc register (see Table 38). This is used to avoid a situation in which two devices drive the data bus simultaneously.
Bits 7, 8, and 13 of the ioc register select the mode of operation for the CKO pin (see Table 38). Available op­tions are a free-running unstretched clock, a wait-stated sequenced clock (runs through two complete cycles during a sequenced external memory access), and a wait-stated clock based on the internal instruction cycle. These clocks drop to the low-speed internal ring oscilla­tor when SLOWCKI is enabled (see 4.13, Power Man­agement). The high-to-low transitions of the wait-stated clock are synchronized to the high-to-low transition of the free-running clock. Also, the CKO pin provides ei­ther a continuously high level, a continuously low level, or changes at the rate of the internal processor clock. This last option, only available with the crystal and small-signal input clock options, enables the DSP1627 CKI input buffer to deliver a full-rate clock to other devic­es while the DSP1627 itself is in one of the low-power modes.

4.7 Serial I/O Units (SIOs)

The serial I/O ports on the DSP1627 device provide a serial interface to many codecs and signal processors with little, if any, external hardware required. Each high­speed, double-buffered port (sdx and sdx2) supports back-to-back transmissions of data. SIO and SIO2 are identical. The output buffer empty (OBE and OBE2) and input buffer full (IBF and IBF2) flags facilitate the read­ing and/or writing of each serial I/O port by program­or interrupt-driven I/O. There are four selectable active clock speeds.
A bit-reversal mode provi des comp atib ility with either the most significant bit (MSB) first or least significant bit (LSB) first serial I/O formats (see Table 22, Serial I/O Control Registers (sioc and sioc2)). A multiprocessor I/O configuration is supported. This feature allows up to eight DSP161X devices to be connected together on an SIO port without requiring external glue logic.
Lucent Technologies Inc. 19
Page 20
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
The serial data may be internally looped back by setting the SIO loopback control bit, SIOLBC, of the ioc regis­ter. SIOLBC affects both the SIO and SIO2. The data output signals are wrapped around internally from the output to the input (DO1 to DI1 and DO2 to DI2). To ex­ercise loopback, the SIO clocks (ICK1, ICK2, OCK1, and OCK2) should either all be in the active mode, 16-bit condition, or each pair should be driven from one external source in passive mode. Similarly, pins ILD1 (ILD2) and OLD1 (OLD2) must both be in active mode or tied together and driven from one external frame clock in passive mode. During loopback, DO1, DO2, DI1, DI2, ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1, OLD2, SADD1, SADD2, SYNC1, SYNC2, DOEN1, and DOEN2 are 3-stated.
Setting DODLY = 1 (sioc and sioc2) delays DO by one phase of OCK so that DO changes on the falling edge of OCK instead of the rising edge (DODLY = 0). This re­duces the time available for DO to drive DI and to be val­id for the rising edge of ICK, but increases the hold time on DO by half a cycle on OCK.

Programmable Modes

Programmable modes of operation for the SIO and SIO2 are controlled by the serial I/O control registers (sioc and sioc2). These registers, shown in Table 22, are used to set the ports into various configurations. Both input and output operations can be independently configured as either active or passive. When active, the DSP1627 generates load and clock signals. When pas­sive, load and clock signal pins are inputs.
Since input and output can be independently config­ured, each SIO has four different modes of operation. Each of the sioc registers is also used to select the fre­quency of active clocks for that SIO. Finally, these reg­isters are used to configure the serial I/O data formats. The data can be 8 or 16 bits long, and can also be input/ output MSB first or LSB first. Input and output data for­mats can be independently configured.

Multiprocessor Mode

The multiprocessor mode allows up to eight processors (DSP1629, DSP1628, DSP1627, DSP1620, DSP1618, DSP1617, DSP1616, DSP1611) to be connected to­gether to provide data transmission among any of the DSPs in the system. Either SIO port (SIO or SIO2) may be independently used for the multiprocessor mode. The multiprocessor interface is a four-wire interface, consisting of a data channel, an address/protocol channel, a transmit/receive clock, and a sync signal (see Figure 5). The DI1 and DO1 pins of all the DSPs are connected to transmit and receive the data channel. The SADD1 pins of all the DSPs are connected to trans-
20 Lucent Technologies Inc.
(continued)
mit and receive the address/protocol channel. ICK1 and OCK1 should be tied together and driven from one source. The SYNC1 pins of all the DSPs are connected.
In the configuration shown in Figure 5, the master DSP (DSP0) generates active SYNC1 and OCK1 signals while the slave DSPs use the SYNC1 and OCK1 signals in passive mode to synchronize operations. In addition, all DSPs must have their ILD1 and OLD1 signals in ac­tive mode.
While ILD1 and OLD1 are not required externally for multiprocessor operation, they are used internally in the DSP's SIO. Setting the LD field of the master's sioc reg­ister to a logic level 1 will ensure that the active genera­tion of SYNC1, ILD1, and OLD1 is derived from OCK1 (see Table 22). With this configuration, all DSPs should use ICK1 (tied to OCK1) in passive mode to avoid con­flicts on th e cloc k (CK) l ine (s ee th e
Digital Signal Processor Information Manual
information). Four registers (per SIO) configure the multiprocessor
mode: the time-division multiplexed slot register (tdms or tdms2), the serial receive and transmit address reg­ister (srta or srta2), the serial data transmit register (sdx or sdx2), and the multiprocessor serial address/protocol register (saddx or saddx2).
Multiprocessor mode requires no external logic and uses a TDM interface with eight 16-bit time slots per frame. The transmission in any time slot consists of 16 bits of serial data in the data channel and 16 bits of address and protocol information in the address/proto­col channel. The address information consists of the transmit address field of the srta register of the transmit­ting device. The address information is transmitted con­currently with the transmission of the first 8 bits of data. The protocol information consists of the transmit proto­col field written to the saddx register and is transmitted concurrently with the last 8 bits of data (see Table 25, Multiprocessor Protocol Register). Data is received or recognized by other DSP(s) whose receive address matches the address in the address/protocol channel. Each SIO port has a user-programmable receive ad­dress and transmit address associated with it. The transmit and receive addresses are programmed in the srta register.
In multiprocessor mode, each device can send data in a unique time slot designated by the tdms register trans­mit slot field (bits 7—0). The tdms register has a fully de­coded transmit slot field in order to allow one DSP1627 device to transmit in more than one time slot. This pro­cedure is useful for multiprocessor systems with less than eight DSP1627 devices when a higher bandwidth is necessary between certain devices in that system. The DSP operating during time slot 0 also drives SYNC1.
DSP1611/17/18/27
for more
Page 21
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
(continued)
In order to prevent multiple bus drivers, only one DSP can be programmed to transmit in a particular time slot. In addition, it is important to note that the address/pro­tocol channel is 3-stated in any time slot that is not being driven.
Therefore, to prevent spurious inputs, the address/pro­tocol channel should be pulled up to V
with a 5 kΩ re-
DD
sistor, or it should be guaranteed that the bus is driven in every time slot. (If the SYNC1 signal is externally gen­erated, then this pull-up is required for correct initializa­tion.)
Each SIO also has a fully decoded transmitting address specified by the srta register transmit address field (bits 7—0). This is used to transmit information regarding the destination(s) of the data. The fully decoded receive ad­dress specified by the srta register receive address field (bits 15—8) determines which data will be received.
The SIO protocol channel data is controlled via the sad­dx register. When the saddx register is written, the
lower 8 bits contain the 8-bit protocol field. On a read, the high-order 8 bits read from saddx are the most re­cently received protocol field sent from the transmitting DSP's saddx output register. The low-order 8 bits are read as 0s.
An example use of the protocol channel is to use the top 3 bits of the saddx value as an encoded source address for the DSPs on the multiprocessor bus. This leaves the remaining 5 bits available to convey additional control information, such as whether the associated field is an opcode or data, or whether it is the last word in a trans­fer, etc. Th ese bits c an also be us ed to transf er parit y in­formation about the data. Alternatively, the entire field can be used for data transmission, boosting the band­width of the port by 50%.

Using SIO2

The SIO2 functions the same as the SIO. Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
DO
DI
DSP 0
ICK
OCK
SADD
SYNC
DATA CHANNEL
CLOCK
ADDRESS/PROTOCOL CHANNEL
SYNC SIGNAL
Figure 5. Multiprocessor Communication and Connections
DO
DI
DSP 1
ICK
OCK
SADD
SYNC
DO
DI
DSP 7
ICK
OCK
SADD
SYNC
5 k
5-4181 (F).a
DD
V
Lucent Technologies Inc. 21
Page 22
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
(continued)

4.8 Parallel Host Interface (PHIF)

The DSP1627 has an 8-bit parallel host interface for rap­id transfer of data with external devices. This parallel port is passive (data strobes provided by an external device) and supports either tocols. The PHIF also provides for 8-bit or 16-bit data transfers. As a flexible hos t int erf ac e, it requires little or no glue logic to interface to other devices (e.g., microcon­trollers, microprocesso rs , o r another DSP).
The data path of the PHIF consists of a 16-bit input buff-
pdx0
er, output pins, parallel input buffer full (PIBF) and parallel output buffer empty (POBE), indicate the state of the buffers. In addition, there are two registers used to con­trol and monitor the PHIF's operation: the parallel host in­terface control register ( PHIF status register (PSTAT, see Table 8). The PSTAT register, which reflects the state of the PIBF and POBE flags, can only be read by an external device when the PSTAT input pin is asserted. The the programmable optio ns fo r th is port .
The function of the pins, PIDS and PODS, is programma­ble to support both the pin, PCSN, is an input that, when low, enables PIDS and PODS (or PRWN and PDS, depending on the protocol used). While PCSN is high, the DSP1627 ignores any ac­tivity on PIDS and/or PODS. If a DSP1627 is intended to be continuously accessed through the PHIF port, PCSN should be grounded. If PCSN is low and their respective bits in the PODS by an external device causes the DSP1627 de­vice to recognize an interru pt .

Programmability

(in), and a 16-bit output bu ffer,
inc
Motorola
register are set, the assertion of PIDS and
or
Intel
microcontroller pro-
phifc
, see Table 28), and the
phifc
Intel
and
Motorola
pdx0
(out). Tw o
register defines
protocols. The
register. Setting PMODE selects 16-bit transfer mode. An input pin controlled by the host, PBSEL, determines an access of either the high or low bytes. The assertion level of the PBSEL input pin is configurable in software using bit 3 of the marizes the port's functionality as controlled by the PSTAT and PBSEL pins and the PBSELF and PMO DE fields.
For 16-bit transfers, if PBS ELF is zero, the PIBF and POBE flags are set after the high byte is transferred. If PBSELF is one, the flags a re s et after the low byte is transferred. In 8-bit mode, only the low byte is accessed, and every completion of an input or output access sets PIBF or POBE.
Bit 1 of the to operate either with an chip select (PCSN) and either of the data strobes (PIDS or PODS) are needed to make an access, or with a
torola
protocol where the chip se lec t (PC SN ), a data strobe (PDS), and a read/write strobe (PRWN) are need­ed. PIDS and PODS are negative assertion data strobes while the assertion level o f PDS is programmable through bit 2, PSTRB, of the
Finally, the assertion leve l of th e out put pins, PIBF and POBE, is controlled through bit 4, PFLAG. When PFLAG is set low, PIBF and POBE output pins have positive as­sertion levels. By setting bit 5, PF LAGSEL, the logical OR of PIBF and POBE flags (positive assertion) is seen at the output pin PIBF. By setting bit 7 in the polarity of the POBE fla g in t he s t at us register, PSTAT, can be changed. PSOBEF has no effect on the POBE pin.

Pin Multiplexing

Please refer to Pin Multiplex ing in Section 4.1 for a de­scription of BIO, PHIF, VE C [3 :0 ], and SIO2 pins.
phifc
register, PBSELF. Table 7 sum-
phifc
register, PSTROBE, configures the port
Intel
protocol where only the
phifc
register.
phifc
Mo-
, PSOBEF,
The parallel host interfac e c an be programmed for 8-bit or 16-bit data transfers using bit 0, PMODE, of the
phifc
Table 7. PHIF Function (8-bit and 16-bit Modes)
PMODE Field PSTAT Pin PBSEL Pin PBSELF Field = 0 PBSELF Field = 1
0 (8-bit) 0 0 pdx0 low byte reserved
0 0 1 reserved pdx0 low byte 010PSTATreserved 0 1 1 reserved PSTAT
1 (16-bit) 0 0 pdx0 low byte pdx0 high byte
1 0 1 pdx0 high byte pdx0 low byte 110PSTATreserved 1 1 1 reserved PSTAT
Table 8. pstat Register as Seen on PB[7:0]
Bit
Field
76543 2 1 0
RESERVED PIBF POBE
22 Lucent Technologies Inc.
Page 23
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
(continued)

4.9 Bit Input/Output Unit (BIO)

The BIO controls the directions of eight bidirectional con­trol I/O pins, IOBIT[7:0]. If a pin is configured as an output, it can be individually set, c leared, or toggled. If a pin is configured as an input , it ca n be read and/or tested.
The lower half of the current values (VALUE[7:0]) of the eight bidirectional pins IOBIT[7:0]. The uppe r half of th e REC[7:0]) controls the direction of each of the pins. A log­ic 1 configures the corresponding pin as an output; a logic 0 configures it as an input. The upper half of the ister is cleared upon reset .
cbit
The MODE/MASK[7:0] and DATA/PAT[7:0]. The values of DATA/PAT[7:0] are cleared upon reset. The meaning of a bit in either field depends on w hether it has been config­ured as an input or an output in figured to be an output, th e m eanings are MODE and DATA. For an input, the m eanings are MASK and PAT (pattern). Table 9 show s the functionality of the MOD E/ MASK and DATA/PAT bit s bas ed on the direction select­ed for the associated IOBIT pin.
Those bits that have been configured as inputs can be in­dividually tested for 1 or 0. For those inputs that are being tested, there are four flags produced: allt (all true), allf (all false), somet (some true), and somef (some false). These flags can be used for cond it ional branch or special in­structions. The state of these flags can be saved and re­stored by reading and writing bits 0 to 3 of the (see Table 35).
register (see Table 34) contains two 8-bit fields,
sbit
register (see Table 33) contains
sbit
register (DI-
sbit
. If a pin has been con-
alf
sbit
reg-
register

4.10 Timer

The interrupt timer is composed of the timerc (control) register, the timer0 register, the prescaler, and the counter itself. The timer control register (see Table 31, timerc Register) sets up the operational state of the timer and prescaler. The timer0 register is used to hold the counter reload value (or period register) and to set the initial value of the counter. The prescaler slows the clock to the timer by a number of binary divisors to allow for a wide range of interrupt delay periods.
The counter is a 16-bit down counter that can be loaded with an arbitrary number from software. It counts down to 0 at the clock rate provided by the prescaler. Upon reaching 0 count, a vectored interrupt to program ad­dress 0x10 is issued to the DSP1627, providing the in­terrupt is enabled (bit 8 of inc and ins registers). The counter will then either wait in an inactive state for anoth­er command from software, or will automatically repeat the last interrupting period, depending upon the state of the RELOAD bit in the timerc register.
When RELOAD is 0, the counter counts down from its initial value to 0, interrupts the DSP1627, and then stops, remaining inactive until another value is written to the timer0 register. Writing to the timer0 register causes both the counter and the period register to be written with the specified 16-bit number. When RELOAD is 1, the counter counts down from its initial value to 0, interrupts the DSP1627, automatically reloads the specified initial value from the period register into the counter, and re­peats indefinitely. This provides for either a single timed interrupt event or a regular interrupt clock of arbitrary pe­riod.
Table 9. BIO Operations
DIREC[n]
MODE/
MASK[n]
DATA/
PAT[n]
Action
*
1 (Output) 0 0 Clear 1 (Output) 0 1 Set 1 (Output) 1 0 No Change 1 (Output) 1 1 Toggle
0 (Input) 0 0 No Test 0 (Input) 0 1 No Test 0 (Input) 1 0 Test for Zero 0 (Input) 1 1 Test for One
*0 ≤ n ≤ 7.
If a BIO pin is switched from being configured as an out­put to being configured as an input and then back to be­ing configured as an output, the pin retains the previous
The timer can be stopped and started by software, and can be reloaded with a new period at any time. Its count value, at the time of the read, can also be read by soft­ware. Due to pipeline stages, stopping and starting the timer may result in one inaccurate count or prescaled pe­riod. When the DSP1627 is reset, the bottom 6 bits of the timerc register and the timer0 register and counter are initialized to 0. This sets the prescaler to CKO/2*, turns off the reload feature, disables timer counting, and initial­izes the timer to its inactive state. The act of resetting the chip does not cause a timer interrupt. Note that the peri­od register is not initialized on reset.
The T0EN bit of the timerc register enables the clock to the timer. When T0EN is a 1, the timer counts down to­wards 0. When T0EN is a 0, the timer holds its current count.
output val ue.

Pin Multiplexing

Please refer to Pin Multiplexing in Section 4.1 for a description of BIO, PHIF, VEC[3:0], and SIO2 pins.
* Frequency of CKO/2 is equivalent to either CKI/2 for the PLL by-
passed or related to CKI by the PLL multiplying factors. See Section
4.12, Clock Synthesis.
Lucent Technologies Inc. 23
Page 24
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
(continued)
The PRESCALE field of the timerc register selects one of 16 possible clock rates for the timer input clock (see Table 31, timerc Register).
Setting the DISABLE bit of the timerc register to a logic 1 shuts down the timer and the prescaler for power sav­ings. Setting the TIMERDIS, bit 4, in the powerc register has the same effect of shutting down the timer. The DISABLE bit and the TIMERDIS bit are cleared by writ­ing a 0 to their respective registers to restore the normal operating mode.

4.11 JTAG Test Port

The DSP1627 uses a JTAG/ wire test port for self-test and hardware emulation. There is no separate TRST input pin. An instruction reg­ister, a boundary-scan register, a bypass register, and a device identification register have been implemented. The device identification register coding for the DSP1627 is shown in Table 37. The instruction register (IR) is 4 bits long. The instruction for accessing the de­vice ID is 0xE (1110). The behavior of the instruction register is summarized in Table 10. Cell 0 is the LSB (closest to TDO).
IEEE
1149.1 standard four-
The first line shows the cells in the IR that capture from a parallel input in the capture-IR controller state. The second line shows the cells that always load a logic 1 in the capture-IR controller state. The third line shows the cells that always load a logic 0 in the capture-IR control­ler state. Cell 3 (MSB of IR) is tied to status signal PINT, and cell 2 is tied to status signal JINT. The state of these signals can therefore be captured during capture-IR and shifted out during SHIFT-IR controller states.

Boundary-Scan Register

All of the chip's inputs and outputs are incorporated in a JTAG scan path shown in Table 11. The types of boundary-scan cells are as follows:
I = input cell
O = 3-state output cell
B = bidirectional (I/O) cell
OE = 3-state control cell
DC = bidirectional control cell
Table 10. JTAG Instruction Register
IR Cell #: 3 2 1 0
Parallel Input? Y Y N N Always Logic 1? N N N Y Always Logic 0? N N Y N
24 Lucent Technologies Inc.
Page 25
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
(continued)
Note that the direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO.
Table 11. JTAG Boundary-Scan Register
Cell Type Signal Name/Function Cell Type Signal Name/Function
0 OE Controls cells 1, 27—31 69 B OCK2/PCSN* 1 O CKO 70 DC Controls cell 71 2IRSTB 71BDO2/PSTAT* 3 DC Controls cell 4 72 DC Controls cell 73 4 B TRAP 73 B SYNC2/PBSEL* 5I
STOP
74 DC Controls cell 75 6 O IACK 75 B ILD2/PIDS* 7 I INT0 76 DC Controls cell 77 8 OE Controls cells 6, 10—25, 49, 50, 78, 79 77 B OLD2/PODS* 9 I INT1 78 O IBF2/ PIBF*
10—25 O AB[0:15] 79 O OBE2/POBE*
26 I EXM 80 DC Controls cell 81
27 O RWN 81 B ICK2/PB0* 28—31 O EROM, ERAMLO, ERAMHI, IO 82 DC Controls cell 83 32—36 B DB[0:4] 83 B DI2/PB1*
37 DC Controls cells 32—36, 38—48 84 DC Controls cell 85 38—48 B DB[5:15] 85 B DOEN2/PB2*
49 O OBE1 86 DC Controls cell 87
50 O IBF1 87 B SADD2/PB3*
51 I DI1 88 DC Controls cell 89
52 DC Controls cell 53 89 B IOBIT0/PB4*
53 B ILD1 90 DC Controls cell 91
54 DC Controls cell 55 91 B IOBIT1/PB5*
55 B ICK1 92 DC Controls cell 93
56 DC Controls cell 57 93 B IOBIT2/PB6*
57 B OCK1 94 DC Controls cell 95
58 DC Controls cell 59 95 B IOBIT3/PB7*
59 B OLD1 96 DC Controls cell 97
60 OE Controls cell 61 97 B VEC3/IOBIT4*
61 O DO1 98 DC Controls cell 99
62 DC Controls cell 63 99 B VEC2/IOBIT5*
63 B SYNC1 100 DC Controls cell 101
64 DC Controls cell 65 101 B VEC1/IOBIT6*
65 B SADD1 102 DC Controls cell 103
66 DC Controls cell 67 103 B VEC0/IOBIT7*
67 B DOEN1 104 I
CKI
68 DC Controls cell 69
* Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2. † Note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as the STOP pin will. ‡ When the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin.
Lucent Technologies Inc. 25
Page 26
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture

4.12 Clock Synthesis

CKI INPUT CLOCK
CKI
f
÷ N
Nbits[2:0]
PHASE
DETECTOR
(continued)
RING
OSCILLATOR
LOCK
(FLAG TO INDICATE LOCK CONDITION OF PLL)
CHARGE
PUMP
÷ M
LOOP
FILTER
powerc
VCO
VCO CLOCK
VCO
f
SLOWCKI
SLOW CLOCK
f
÷ 2
PLLEN
INTERNAL
PROCESSOR
M
CKI
f
U X
CLOCK
INTERNAL CLOCK
f
PLLSEL
pllc
PLL/SYNTHESIZER
LF[3:0]Mbits[4:0]
Figure 6. Clock Source Block Diagram
The DSP1627 provides an on-chip, programmable clock synthesizer. Figure 6 is the clock source diagram. The 1X CKI input clock, the output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal DSP clock. The clock synthesizer is based on a phase-locked loop (PLL), and the terms clock synthesizer and PLL are used interchangeably.
On powerup, CKI is used as the clock source for the DSP. This clock is used to generate the internal proces­sor clocks and CKO, where f
CKI
= f
. Setting the ap-
CKO
propriate bits in the pllc control register (described in Table 32) will enable the clock synthesizer to become the clock source. The powerc register, which is dis­cussed in Section 4.13, can override the selection to stop clocks or force the use of the slow clock for low­power operation.
5-4520 (F)

PLL Control Signals

The input to the PLL comes from one of the three mask­programmable clock options: CMOS, crystal, or small­signal. The PLL cannot operate without an external in­put clock.
To use the PLL, the PLL must first be allowed to stabi­lize and lock to the programmed frequency. After the PLL has locked, the LOCK flag is set and the lock detect circuitry is disabled. The synthesizer can then be used as the clock source. Setting the PLLSEL bit in the pllc register will switch sources from f
CKI
to f
/2 without
VCO
glitching. It is important to note that the setting of the pllc register must be maintained. Otherwise, the PLL will seek the new set point. Every time the pllc register is written, the LOCK flag is reset.
26 Lucent Technologies Inc.
Page 27
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
The frequency of the PLL output clock, f
(continued)
, is deter-
VCO
mined by the values loaded into the 3-bit N divider and the 5-bit M divider. When the PLL is selected and locked, the frequency of the internal processor clock is related to the frequency of CKI by the following equa­tions:
f
= f
.
CKI
* M/N
= f
CKO
VCO
= f
÷ 2
, must fall within the
VCO
VCO
must be at
VCO
INTERNAL CLOCK
f
The frequency of the VCO, f range listed in Table 63. Also note that f least twice f
CKI
The coding of the Mbits and Nbits is described as fol­lows:
Mbits = M − 2 if (N == 1)
Nbits = 0x7
else
Nbits = N − 2 where N ranges from 1 to 8 and M ranges from 2 to 20. The loop filter bits LF[3:0] should be programmed ac-
cording to Table 64.
Two other bits in the pllc register control the PLL. Clear­ing the PLLEN bit powers down the PLL; setting this bit powers up the PLL. Clearing the PLLSEL bit deselects the PLL so that the DSP is clocked by a 1X version of the CKI input; setting the PLLSEL bit selects the PLL­generated clock for the source of the DSP internal pro­cessor clock. The pllc register is cleared on reset and powerup. Therefore, the DSP comes out of reset with the PLL deselected and powered down. M and N should be changed only while the PLL is deselected. The val­ues of M and N should not be changed when powering down or deselecting the PLL.
As previously mentioned, the PLL also provides a user flag, LOCK, to indicate when the loop has locked. When this flag is not asserted, the PLL output is unstable. The DSP should not be switched to the PLL-based clock without first checking that the lock flag is set. The lock flag is cleared by writing to the pllc register. When the PLL is deselected, it is necessary to wait for the PLL to relock before the DSP can be switched to the PLL­based clock. Before the input clock is stopped, the PLL should be powered down. Otherwise, the LOCK flag will not be reset and there may be no way to determine if the PLL is stable, once the input clock is applied again.
The lock-in time depends on the frequency of operation and the values programmed for M and N (see Table 64).
Lucent Technologies Inc. 27
Page 28
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
(continued)

PLL Programming Examples

The following section of code illustrates how the PLL would be initialized on powerup, assuming the following oper­ating conditions:
CKI input frequency = 10 MHz
Internal clock and CKO frequency = 50 MHz
VCO frequency = 100 MHz
Input divide down count N = 2 (Set
Feedback down count M = 20 (Set
Nbits[2:0]
Mbits[4:0]
= 000 to get N = 2, as described in Table 32.) = 10010 to get M = 18 + 2 = 20, as described in Table 32.)
The device would come out of reset with the PLL disabled and deselected.
pllinit: pllc = 0x2912 /* Running CKI input clock at 10 MHz, set up counters in PLL */
pllc = 0xA912 /* Power on PLL, but PLL remains deselected */ call pllwait /* Loop to check for LOCK flag assertion */ pllc = 0xE912 /* Select high-speed, PLL clock */ goto start /* User's code, now running at 50 MHz */
pllwait: if lock return
goto pllwait
Programming examples which illustrate how to use the PLL with the various power management modes are listed in Section 4.13.

Latency

The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the actual switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be executed, but it will be at the previous clock rate. Table 12 shows the latency times for switching between CKI-based and PLL­based clocks. In the example given, the delay to switch to the PLL source is 1—4 CKO cycles and to switch back is 11—31 CKO cycles.
Table 12. Latency Times for Switching Between CKI and PLL-Based Clocks
Minimum Latency (Cycles) Maximum Latency (Cycles)
Switch to PLL-based clock 1 N + 2
Switch from PLL-based clock M/N + 1 M + M/N + 1
Frequency Accuracy and Jitter
When using the PLL to multiply the input clock frequency up to the instruction clock rate, it is important to realize that although the average frequency of the internal clock and CKO will have about the same relative accuracy as the input clock, noise sources within the DSP will produce jitter on the PLL clock such that each individual clock period will have some error associated with it. The PLL is guaranteed only to have sufficiently low jitter to operate the DSP, and thus, this clock should not be used as an input to jitter-sensitive devices in the system.
V
and V
DDA
The PLL has its own power and ground pins, V form of a ferrite bead connected from V a 0.01 µF ceramic) from V
Connections
SSA
to VSS. V
DDA
and V
DDA
to VDD and two decoupling capacitors (4.7 µF tantalum in parallel with
DDA
can be connected directly to the main ground plane. This recommen-
SSA
. Additional filtering should be provided for V
SSA
DDA
in the
dation is subject to change and may need to be modified for specific applications depending on the characteristics of the supply noise.
Note:
For devices with the CMOS clock input option, the CKI2 pin should be connected to V
SSA
.
28 Lucent Technologies Inc.
Page 29
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
(continued)

4.13 Power Management

There are three different control mechanisms for putting the DSP1627 into low-power modes: the powerc control register, the STOP pin, and the AWAIT bit in the alf reg­ister. The PLL can also be disabled with the PLLEN bit of the pllc register for more power saving.

Powerc Control Register Bits

The powerc register has 10 bits that power down vari­ous portions of the chip and select the clock source:
XTLOFF:
crystal oscillator or the small-signal input circuit, dis­abling the internal processor clock. Assertion of the XTLOFF bit to disable the crystal oscillator also pre­vents its use as a noninverting buffer. Since the oscilla­tor and the small-signal input circuits take many cycles to stabilize, care must be taken with the turn-on se­quence, as described later.
SLOWCKI:
ring oscillator as the clock source for the internal pro­cessor clock instead of CKI or the PLL. When CKI or the PLL is selected, the ring oscillator is powered down. Switching of the clocks is synchronized so that no par­tial or short clock pulses occur. Two the instruction that sets or clears SLOWCKI.
NOCK:
off the internal processor clock, regardless of whether its source is provided by CKI, the PLL, or the ring oscil­lator. The NOCK bit can be cleared by resetting the chip with the RSTB pin, or asserting the INT0 or INT1 pins. Two The PLL remains running, if enabled, while NOCK is set.
INT0EN:
clear the NOCK bit, thereby allowing the device to con­tinue program execution from where it left off without any loss of state. No chip reset is required. It is recom­mended that, when INT0EN is to be used, the INT0 interrupt be disabled in the inc register so that an unin­tended interrupt does not occur. After the program re­sumes, the INT0 interrupt in the ins register should be cleared.
INT1EN:
NOCK clear, exactly like INT0EN previously described. The following control bits power down the peripheral
I/O units of the DSP. These bits can be used to further reduce the power consumption during standard sleep mode.
Assertion of the XTLOFF bit powers down the
Assertion of the SLOWCKI bit selects the
nop
s should follow
Assertion of the NOCK bit synchronously turns
nop
s should follow the instruction that sets NOCK.
This bit allows the INT0 pin to asynchronously
This bit enables the INT1 pin to be used as the
SIO1DIS:
unit. It disables the clock input to the unit, thus eliminat­ing any sleep power associated with the SIO1. Since the gating of the clocks may result in incomplete trans­actions, it is recommended that this option be used in applications where the SIO1 is not used or when reset may be used to reenable the SIO1 unit. Otherwise, the first transaction after reenabling the unit may be corrupt­ed.
SIO2DIS:
way SIO1DIS powers down the SIO1.
PHIFDIS:
host interface. It disables the clock input to the unit, thus eliminating any sleep power associated with the PHIF. Since the gating of the clocks may result in incomplete transactions, it is recommended that this option be used in applications where the PHIF is not used, or when re­set may be used to reenable the PHIF. Otherwise, the first transaction after reenabling the unit may be corrupt­ed.
TIMERDIS:
the clock input to the timer unit. Its function is identical to the DISABLE field of the timerc control register. Writ­ing a 0 to the TIMERDIS field will continue the timer op­eration.
Figure 7 shows a functional view of the effect of the bits of the powerc register on the clock circuitry. It shows only the high-level operation of each bit. Not shown are the bits that power down the peripheral units.

STOP Pin

Assertion (active-low) of the STOP pin has the same ef­fect as setting the NOCK bit in the powerc register. The internal processor clock is synchronously disabled until the STOP pin is returned high. Once the STOP pin is re­turned high, program execution will continue from where it left off without any loss of state. No chip reset is required. The PLL remains running, if enabled, during STOP assertion.

The pllc Register Bits

The PLLEN bit of the pllc register can be used to power down the clock synthesizer circuitry. Before shutting down the clock synthesizer circuitry, the system clock should be switched to either CKI using the PLLSEL bit of pllc, or to the ring oscillator using the SLOWCKI bit of powerc.
This is a powerdown signal to the SIO1 I/O
This bit powers down the SIO2 in the same
This is a powerdown signal to the parallel
This is a timer disable signal which disables
Lucent Technologies Inc. 29
Page 30
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture
CKI2
CKI
STOP
RSTB
XTLOFF
OSCILLATOR,
SMALL SIGNAL
MASK-PROGRAMMABLE
CMOS INPUT CLOCK
HW STOP
NOCK
CLEAR NOCK
OFF
CRYSTAL
OR
CLOCK
OPTION
SW STOP
(continued)
PLLSEL
PLLEN
PLL
CKI
f
DEEP
SLEEP
DISABLE
RING
OSCILLATOR
VCO/2
f
SYNC.
MUX
SYNC.
GATE
INTERNAL CLOCK
f
SLOW CLOCK
f
ON
DEEP
SLEEP
SLOWCKI
INT0
INT0EN
INT1
INT1EN
Notes: The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control register.
Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock. The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur. When the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is pow-
ered down. PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
INTERNAL
PROCESSOR
CLOCK
5-4124 (F).h
Figure 7. Power Management Using the powerc and the pllc Registers
30 Lucent Technologies Inc.
Page 31
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture

Await Bit of the alf Register

Setting the AWAIT bit of the alf register causes the pro­cessor to go into the standard sleep state or power-sav­ing standby mode. Operation of the AWAIT bit is the same as in the DSP1610, DSP1611, DSP1616, DSP1617, and DSP1618. In this mode, the minimum circuitry required to process an incoming interrupt re­mains active, and the PLL remains active if enabled. An interrupt will return the processor to the previous state, and program execution will continue. The action result­ing from setting the AWAIT bit and the action resulting from setting bits in the powerc register are mostly inde­pendent. As long as the processor is receiving a clock, whether slow or fast, the DSP may be put into standard sleep mode with the AWAIT bit. Once the AWAIT bit is set, the STOP pin can be used to stop and later restart the processor clock, returning to the standard sleep state. If the processor clock is not running, however, the AWAIT bit cannot be set.

Power Management Sequencing

There are important considerations for sequencing the power management modes. Both the crystal oscillator and the small-signal clock input circuits have start-up delays which must be taken into account, and the PLL requires a delay to reach lock-in. Also, the chip may or may not need to be reset following a return from a low­power state.
Devices with a crystal oscillator or small-signal input clocking option may use the XTLOFF bit in the powerc register to power down the on-chip oscillator or small­signal circuitry, thereby reducing the power dissipation. When reenabling the oscillator or the small-signal cir­cuitry, it is important to bear in mind that a start-up inter­val exists during which time the clocks are not stable.
(continued)
Two scenarios exist here:
1. Immediate Turn-Off, Turn-On with RSTB: This sce­nario applies to situations where the target device is not required to execute any code while the crystal os­cillator or small-signal input circuit is powered down and where restart from a reset state can be tolerated. In this case, the processor clock derived from either the oscillator or the small-signal input is running when XTLOFF is asserted. This effectively stops the inter­nal processor clock. When the system chooses to re­enable the oscillator or small-signal input, a reset of the device will be required. The reset pulse must be of sufficient duration for the oscillator start-up interval to be satisfied. A similar interval is required for the small-signal input circuit to reach its dc operating point. A minimum reset pulse of 20 ms will be ade­quate. The falling edge of the reset signal, RSTB, will asynchronously clear the XTLOFF field, thus re-en­abling the power to the oscillator or small-signal cir­cuitry. The target DSP will then start execution from a reset state, following the rising edge of RSTB.
2. Running from Slow Clock While XTLOFF Active: The second scenario applies to situations where the de­vice needs to continue execution of its target code when the crystal oscillator or small-signal input is powered down. In this case, the device switches to the slow ring oscillator clock first, by enabling the SLOWCKI field before writing a 1 to the XTLOFF field. Two operations to the powerc register. The target device will then continue execution of its code at slow speed, while the crystal oscillator or small-signal input clock is turned off. Switching from the slow clock back to the high-speed crystal oscillator clock is then accom­plished in three user steps. First, XTLOFF is cleared. Then, a user-programmed routine sets the internal timer to a delay to wait for the crystal's oscillations to become stable. When the timer counts down to zero, the high-speed clock is selected by clearing the SLOWCKI field, either in the timer's interrupt service routine or following a timer polling loop. If PLL opera­tion is desired, then an additional routine is neces­sary to enable the PLL and wait for it to lock.
nop
s are needed in between the two write
Lucent Technologies Inc. 31
Page 32
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture

Power Management Examples Without the PLL

The following examples show the more significant options for reducing the power dissipation. These are valid only if the pllc register is set to disable and deselect the PLL (PLLEN = 0, PLLSEL = 0).
Standard Sleep Mode.
CKI, the alf register's AWAIT bit is set. Peripheral units may be turned off to further reduce the sleep power.
powerc = 0X00F0 /* Turn off peripherals, core running with CKI */
sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* Needed for bedtime execution. Only sleep power */
nop /* consumed here until.... interrupt wakes up the device */
cont: . . . /* User code executes here */
powerc = 0x0 /* Turn peripheral units back on */
Sleep with Slow Internal Clock.
is put to sleep. This will reduce the power dissipation while waiting for an interrupt to continue program execution.
powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for it to take effect */
sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* Needed for bedtime execution. Reduced sleep power */
nop /* consumed here.... Interrupt wakes up the device */
cont: . . . /* User code executes here */
powerc = 0x00F0 /* Select high-speed clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */
This is the standard sleep mode. While the processor is clocked with a high-speed clock,
(continued)
In this case, the ring oscillator is selected to clock the processor before the device
Note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock.
Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled.
crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be selected first.
powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for it to take effect */ powerc = 0xC0F0 /* Turn off the crystal oscillator */
sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* Needed for bedtime execution. Reduced sleep power */
nop /* consumed here.... Interrupt wakes up the device */
powerc = 0x40F0 /* Clear XTLOFF, reenable oscillator/small-signal */ call xtlwait /* Wait until oscillator/small-signal is stable */
cont: powerc = 0x00F0 /* Select high-speed clock */
2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */
Note that, in this case, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. 32 Lucent Technologies Inc.
If the target device contains the
Page 33
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
Software Stop.
In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the
(continued)
clocks. If the device uses the crystal oscillator or small-signal clock option, the power management must be done in correct sequence.
powerc = 0x4000 /* SLOWCKI asserted */ 2*nop /* Wait for it to take effect */ powerc = 0xD000 /* XTLOFF asserted if applicable and INT0EN asserted */ inc = NOINT0 /* Disable the INT0 interrupt */
sopor:powerc = 0xF000 /* NOCK asserted, all clocks stop */
/* Minimum switching power consumed here */
3*nop /* Some nops will be needed */
/* INT0 pin clears the NOCK field, clocking resumes */
cont: powerc = 0x4000 /* INT0EN cleared and XTLOFF cleared, if applicable*/
call waitxtl /* Wait for the crystal oscillator/small-signal to */
/* stabilize, if applicable*/ powerc = 0x0 /* Clear SLOWCKI field, back to high speed */ 2*nop /* Wait for it to take effect */ ins = 0x0010 /* Clear the INT0 status bit */
In this case also, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. The previous examples do not provide an exhaustive list of options available to the user. Many different clocking
possibilities exist for which the target device may be programmed, depending on:
The clock source to the processor.
Whether the user chooses to power down the peripheral units.
The operational state of the crystal oscillator/small-signal clock input, powered or unpowered.
Whether the internal processor clock is disabled through hardware or software.
The combination of power management modes the user chooses.
Whether or not the PLL is enabled.
An example subroutine for xtlwait follows:
xtlwait: timer0 = 0x2710 /* Load a count of 10,000 into the timer */
timerc = 0x0010 /* Start the timer with a PRESCALE of two */ inc = 0x0000 /* Disable the interrupts */
loop1: a0 = ins /* Poll the ins register */
a0 = a0 & 0x0100 /* Check bit 8 (TIME) of the ins register */ if eq goto loop1 /* Loop if the bit is not set */ ins = 0x0100 /* Clear the TIME interrupt bit */ return /* Return to the main program */
Lucent Technologies Inc. 33
Page 34
Data Sheet
DSP1627 Digital Signal Processor March 2000
4 Hardware Architecture

Power Management Examples with the PLL

The following examples show the more significant options for reducing power dissipation if operation with the PLL clock synthesizer is desired.
Standard Sleep Mode, PLL Running.
the input to the clock synthesizer, CKI, remains running, the alf register's AWAIT bit is set. The PLL will continue to run and dissipate power. Peripheral units may be turned off to further reduce the sleep power.
powerc = 0x00F0 /* Turn off peripherals, core running with PLL */
sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* Needed for bedtime execution. Only sleep power plus PLL */
nop /* power consumed here.... Interrupt wakes up the device */
cont: . . . /* User code executes here */
powerc = 0x0 /* Turn peripheral units back on */
Sleep with Slow Internal Clock, PLL Running
before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program execution.
powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for slow clock to take effect */
sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* Needed for bedtime execution. Reduced sleep power, PLL */ nop /* power, and ring oscillator power consumed here... */
cont: . . . /* User code executes here */
powerc = 0x00F0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */
(continued)
This mode would be entered in the same manner as without the PLL. While
. In this case, the ring oscillator is selected to clock the processor
/* Interrupt wakes up the device */
34 Lucent Technologies Inc.
Page 35
Data Sheet March 2000 DSP1627 Digital Signal Processor
4 Hardware Architecture
Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled, PLL Disabled
vice contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be selected first, and then the PLL must be disabled, since the PLL cannot run without the clock input circuitry being active.
powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for slow clock to take effect */ pllc = 0x29F2 /* Disable PLL (assume N = 1,M = 20, LF = 1001) */ powerc = 0xC0F0 /* Disable crystal oscillator */
sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* Needed for bedtime execution. Reduced sleep power
nop /* consumed here.... Interrupt wakes up device */
powerc = 0x40F0 /* Clear XTLOFF, leave PLL disabled */ call xtlwait /* Wait until crystal oscillator/small-signal is stable */ pllc = 0xE9F2 /* Enable PLL, continue to run off slow clock */ call pllwait /* Loop to check for LOCK flag assertion */
cont: powerc = 0x00F0 /* Select high-speed PLL based clock */
2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripherals back on */
(continued)
. If the target de-
Software Stop, PLL Disabled
reenable the clocks. If the device uses the crystal oscillator or small-signal clock option, the power management must be done in the correct sequence, with the PLL being disabled before shutting down the clock input buffer.
powerc = 0x4000 /* SLOWCKI asserted */ 2*nop /* Wait for slow clock to take effect */ pllc = 0x29F2 /* Disable PLL (assume N = 1, M = 20, LF = 1001) */ powerc = 0xD000 /* XTLOFF asserted, if applicable and INT0EN
sopor:powerc = 0xF000 /* NOCK asserted, all clocks stop */
3*nop /* Some nops will be needed */
cont: powerc = 0x4000 /* INTOEN cleared and XTLOFF cleared, if applicable */
call xtlwait /* Wait until crystal oscillator/small-signal is stable */
pllc = 0xE9F2 /* Enable PLL, continue to run off slow clock */ call pllwait /* Loop to check for LOCK flag assertion */ powerc = 0x0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ ins = 0x0010 /* Clear the INT0 status bit */
. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to
/* asserted */
/* Minimum switching power consumed here */
/* INT0 pin clears NOCK field, clocking resumes */
/* if applicable */
Lucent Technologies Inc. 35
Page 36
Data Sheet
DSP1627 Digital Signal Processor March 2000

5 Software Architecture

5.1 Instruction Set

The DSP1627 processor has seven types of instruc­tions: multiply/ALU, special function, control, F3 ALU, BMU, cache, and data move. The multiply/ALU instruc­tions are the primary instructions used to implement sig­nal processing algorithms. Statements from this group can be combined to generate multiply/accumulate, log­ical, and other ALU functions and to transfer data be­tween memory and registers in the data arithmetic unit. The special function instructions can be conditionally executed based on flags from the previous ALU or BMU operation, the condition of one of the counters, or the value of a pseudorandom bit in the DSP1627 device. Special function instructions perform shift, round, and complement functions. The F3 ALU instructions enrich the operations available on accumulators. The BMU in­structions provide high-performance bit manipulation. The control instructions implement the goto and call commands. Control instructions can also be executed conditionally. Cache instructions are used to implement low-overhead loops, conserve program memory, and decrease the execution time of certain multiply/ALU in­structions. Data move instructions are used to transfer data between memory and registers or between accu­mulators and registers. See the
Digital Signal Processor Information Manual
tailed description of the instruction set. The following operators are used in describing the in-
struction set:
* 16 x 16-bit –> 32-bit multiplication
direct addressing when used as a prefix to an ad­dress register
or
denotes direct addressing
when used as a prefix to an immediate
+ 36-bit addition
36-bit subtraction
>> Arithmetic right shift
>>> Logical right shift
<< Arithmetic left shift
<<< Logical left shift
| 36-bit bitwise OR
& 36-bit bitwise AND
^ 36-bit bitwise EXCLUSIVE OR
: Compound address swapping, accumulator
shuffling
~ One's complement
DSP1611/17/18/27
for a de-
or
register-in-

Multiply/ALU Instructions

Note that the function statements and transfer state­ments in Table 13 are chosen independently. Any func­tion statement (F1) can be combined with any transfer statement to form a valid multiply/ALU instruction. If ei­ther statement is not required, a single statement from either column also constitutes a valid instruction. The number of cycles to execute the instruction is a function of the transfer column. (An instruction with no transfer statement executes in one instruction cycle.) Whenever PC, pt, or rM is used in the instruction and points to ex­ternal memory, the programmed number of wait-states must be added to the instruction cycle count. All multi­ply/ALU instructions require one word of program mem­ory. The no-operation (
nop
) instruction is a special­case encoding of a multiply/ALU instruction and exe­cutes in one cycle. The assembly-language representa­tion of a
nop
is either
nop
or a single semicolon.
A single-cycle squaring function is provided in DSP1627. By setting the X = Y = bit in the auc register, any instruction that loads the high half of the y register also loads the x register with the same value. A subse­quent instruction to multiply the x register and y register results in the square of the value being placed in the p register. The instruction a0 = p p = x*y y = *r0++ with the X = Y = bit set to one will read the value pointed to by r0, load it to both x and y, multiply the previously fetched value of x and y, and transfer the previous prod­uct to a0. A table of values pointed to by r0 can thus be squared in a pipeline with one instruction cycle per each value. Multiply/ALU instructions that use x = X transfer statements (s uch as a 0 = p p = x*y y = *r0 ++ x = *pt ++) are not recommended for squaring because pt will be incremented even though x is not loaded from the value pointed to by pt. Also, the same conflict wait occurrenc­es from reading the same bank of internal memory or reading from external memory apply, since the X space fetch occurs (even though its value is not used).
† These are 36-bit operations. One operand is 36-bit data in an ac-
cumulator; the other operand may be 16, 32, or 36 bits.
36 Lucent Technologies Inc.
Page 37
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)
Table 13. Multiply/ALU Instructions
Function Statement
Transfer Statement
Cycles (Out/In Cache)
p = x * y y = Y x = X 2/1
aD = p p = x * y y = aT x = X 2/1 aD = aS + p p = x * y y[l] = Y 1/1 aD = aS – p p = x * y aT[l] = Y 1/1
aD = p x = Y 1/1 aD = aS + p Y 1/1 aD = aS – p Y = y[ l] 2/2
aD = y Y = aT[l] 2/2 aD = aS + y Z:y x = X 2/2 aD = aS – y Z:y[l] 2/2 aD = aS & y Z:aT[l] 2/2
aD = aS | y
aD = aS ^ y
aS – y
aS & y
† The l in [ ] is an optional argument that specifies the low 16 bits of aT or y. ‡ Add cycles for:
1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.
2. If an X space access and a Y space access are made to the same bank of DPRAM in one instruction, add one cycle.
Note:
For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corre­sponding CLR bit in the auc register is zero. auc is cleared by reset.
Table 14. Replacement Table for Multiply/ALU Instructions
Replace Value Meaning
aD, aS, aT a0, a1 One of two DAU accumulators.
X *pt++, *pt++i X memory space location pointed to by pt. pt is postmodified by +1 and
i, respectively.
Y *rM, *rM++, *rM--, rM++j RAM location pointed to by rM (M = 0, 1, 2, 3). rM is postmodified by
0, +1, –1, or j, respectively.
Z *rMzp, *rMpz, *rMm2, *rMjk Read/Write compound addressing. rM (M = 0, 1, 2, 3) is used twice.
First, postmodified by 0, +1, –1, or j, respectively; and, second, post­modified by +1, 0, +2, or k, respectively.
Lucent Technologies Inc. 37
Page 38
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture

Special Function Instructions

All forms of the special function require one word of program memory and execute in one instruction cycle. (If PC points to external memory, add programmed wait-states.)
aD = aS >> 1 aD = aS >> 4 aD = aS >> 8 aD = aS >> 16
aD = aS Load destination accumulator from source accumulator aD = –aS 2's complement
aD = ~aS aD = rnd(aS) Round upper 20 bits of accumulator aDh = aSh + 1 — Increment upper half of accumulator (lower half cleared) aD = aS + 1 Increment accumulator aD = y Load accumulator with 32-bit y register value with sign extend aD = p Load accumulator with 32-bit p register value with sign extend
aD = aS << 1 aD = aS << 4 aD = aS << 8 aD = aS << 16
}
Arithmetic right shift (sign preserved) of 36-bit accumulators
*
1's complement
}
Arithmetic left shift (sign not preserved) of the lower 32 bits of accumulators (upper 4 bits are sign-bit-extended from bit 31 at the completion of the shift)
(continued)
The above special functions can be conditionally executed, as in:
if CON instruction
and with an event counter
ifc CON instruction
which means:
if CON is true then
c1 = c1 + 1 instruction c2 = c1
else
c1 = c1 + 1
The above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1.
Table 15. Replacement Table for Special Function Instructions
Replace Value Meaning
aD aS
CON mi, pl, eq, ne, gt, le, lvs, lvc, mvs, mvc, c0ge,
c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf,
somet, somef, oddp, evenp , mns1, nmns1, npint,
a0, a1 One of two DAU accumulators.
See Table 17 for definitions of mnemonics.
njint, lock
* This function is not available for the DSP16A.
38 Lucent Technologies Inc.
Page 39
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)

Control Instructions

All control instructions executed unconditionally execute in two cycles, except
icall
which takes three cycles. Control instructions executed conditionally execute in three instruction cycles. (If PC, pt, or pr point to external memory, add programmed wait-states.) Control instructions executed unconditionally require one word of program memory, while control instructions executed conditionally require two words. Control instructions cannot be executed from the cache.
goto JA
goto pt call JA
call pt icall
return (goto pr) ireturn (goto pi)
goto JA
†The
goto
the to the desired current page.
‡The
or
icall
instruction is reserved for development system use.
The above control instructions, with the exception of
call JA
and
call
is placed there, the program counter will have incremented to the next page and the jump will be to the next page, rather than
instructions should not be placed in the last or next-to-last instruction before the boundary of a 4 Kwords page. If
ireturn
and
icall
, can be conditionally executed. For example:
if le goto 0x0345
Table 16. Replacement Table for Control Instructions
Replace Value Meaning
CON mi, pl, eq, ne, gt, le, nlvs, lvc, mvs, mvc, c0ge, c0lt,
See Table 17 for definitions of mnemonics.
c1ge, c1lt, heads, tails, true, false, allt, allf, somet,
somef, oddp, evenp, mns1, nmns1, npint, njint, lock
JA 12-bit value Least significant 12 bits of absolute address
within the same 4 Kwords memory section.
Lucent Technologies Inc. 39
Page 40
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)

Conditional Mnemonics (Flags)

Table 17 lists mnemonics used in conditional execution of special function and control instructions.
Table 17. DSP1627 Conditional Mnemonics
Test Meaning Test Meaning
pl Result is nonnegative (sign bit is bit 35). ≥ 0 mi Result is negative. < 0
eq Result is equal to 0. = 0 ne Result is not equal to 0. ≠ 0
gt Result is greater than 0. > 0 le Result is less than or equal to 0. ≤ 0
lvs Logical overflow set.
mvs Mathematical overflow set.
*
lvc Logical overflow clear.
mvc Mathematical overflow clear. c0ge Counter 0 greater than or equal to 0. c0lt Counter 0 less than 0. c1ge Counter 1 greater than or equal to 0. c1lt Counter 1 less than 0.
heads Pseudorandom sequence bit set. tails Pseudorandom sequence bit clear.
true The condition is always satisfied in an if in-
struction.
allt All True, all BIO input bits tested compared
successfully.
somet Some True, some BIO input bits tested com-
pared successfully.
false The condition is never satisfied in an if instruc-
tion.
allf All False, no BIO input bits tes ted com par ed
successfully.
somef Some False, some BIO input bits tested did
not compare successfully.
oddp Odd Parity, from BMU operation. evenp Even Parity, from BMU operation.
mns1 Minus 1, result of BMU operation. nmns1 Not Minus 1, result of BMU operation.
npint Not PINT, used by hardware development
system.
njint Not JINT, used by hardware development
system.
lock The PLL has achieved lock and is stable.
* Result is not representable in the 36-bit accumulators (36-bit overflow). † Bits 35—31 are not the same (32-bit overflow).
Notes: Testing the state of the counters (c0 or c1) automatically increments the counter by one.
The heads or tails condition is determined by a randomly set or cleared bit, respectively. The bit is randomly set with a probability of 0.5. A random rounding function can be implemented with either heads or tails. The random bit is generated by a ten-stage pseudorandom sequence generator (PSG) that is updated after either a heads or tails test. The pseudorandom sequence may be reset by writing any value to the pi register, except during an interrupt service routine (ISR). While in an ISR, writing to the pi register updates the register and does not reset the PSG. If not in an ISR, writing to the pi register resets the PSG. (The pi register is updated, but will be written with the contents of the PC on the next instruction.)
Interrupts must be disabled when writing to the pi register.
value, the resets the PSG.
ireturn
instruction will not return to the correct location. If the RAND bit in the auc register is set, however, writing the pi regist er never
If an interrupt is taken after the pi write, but before pi is updated with the PC
40 Lucent Technologies Inc.
Page 41
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)

F3 ALU Instructions

These instructions are implemented in the DSP1600 core. They allow accumulator two-operand operations with ei­ther another accumulator, the p register, or a 16-bit immediate operand (IM16). The result is placed in a destination accumulator that can be independently specified. All operations are done with the full 36 bits. For the accumulator with accumulator operations, both inputs are 36 bits. For the accumulator with p register operations, the p register is sign-extended into bits 35—32 before the operation. For the accumulator high with immediate operations, the im­mediate is sign-extended into bits 35—32 and the lower bits 15—0 are filled with zeros, except for the AND opera­tion, for which they are filled with ones. These conventions allow the user to do operations with 32-bit immediates by programming two consecutive 16-bit immediate operations. The F3 ALU instructions are shown in Table 18.
Table 18. F3 ALU Instructions
F3 ALU Instructions
Cachable (One-Cycle)
aD = aS + aT aD = aS – aT aD = aS & aT
aD = aS | aT aD =aS ^ aT
aS – aT
aS & aT aD = aS + p aD = aS – p aD = aS & p
aD = aS | p
aD = aS ^ p
aS – p aS & p
Not Cachable (Two-Cycle)
aD = aSh + IM16 aD = aSh – IM16 aD = aSh & IM16
aD = aSh | IM16
aD = aSh ^ IM16
aSh – IM16
aSh & IM16 aD = aSl + IM16 aD = aSl – IM16
aD = aSl & IM16
aD = aSl | IM16
aD = aSl ^ IM16
aSl – IM16
aSl & IM16
Note: The F3 ALU instructions that do not have a destination accumulator are used to set flags for conditional
operations, i.e., bit test operations.
† If PC points to external memory, add programmed wait-states. ‡ The h and l are required notation in these instructions.

F4 BMU Instructions

The bit manipulation unit in the DSP1627 provides a set of efficient bit manipulation operations on accumulators. It contains four auxiliary registers, ar<0—3> (arM, M = 0, 1, 2, 3), two alternate accumulators (aa0—aa1), which can be shuffled with the working set, and four flags (oddp, evenp, mns1, and nmns1). The flags are testable by condi­tional instructions and can be read and written via bits 4—7 of the alf register. The BMU also sets the LMI, LEQ, LLV, and LMV flags in the psw register.
LMI = 1 if negative (i.e., bit 35 = 1)
LEQ = 1 if zero (i.e., bits 35—0 are 0)
LLV = 1 if (a) 36-bit overflow, or if (b) illegal shift on field width/offset condition
LMV = 1 if bits 31—35 are not the same (32-bit overflow)
The BMU instructions and cycle times follow. (If PC points to external memory, add programmed wait-states.) All BMU instructions require 1 word of program memory unless otherwise noted. Please refer to the
27 Digital Signal Processor Information Manual
for further discussion of the BMU instructions.
DSP1611/17/18/
Lucent Technologies Inc. 41
Page 42
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
Barrel Shifter:
(continued)
aD = aS >> IM16 Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word. aD = aS >> arM Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle. aD = aS
>> aS Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.
aD = aS >>> IM16 Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS >>> arM Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle. aD = aS
aD = aS << IM16 Arithmetic left shift aD = aS << arM Arithmetic left shift aD = aS << aS Arithmetic left shift
>>> aS Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle.
by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
by arM (36-bit shift, 0s filled in); 1-cycle.
by aS (36-bit shift, 0s filled in); 2-cycle.
aD = aS <<< IM16 Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS <<< arM Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle. aD = aS
† Not the same as the special function arithmetic left shift. Here, the guard bit s in the destination accumulator are shifted in to, not sign-extended.
Normalization and Exponent Computation:
<<< aS Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle.
aD = exp(aS) Detect the number of redundant sign bits in accumulator; 1-cycle. aD = norm(aS, arM) Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.
Bit Field Extraction and Insertion:
aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word. aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle.
aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word. aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle.
aD = insert(aS, IM16) Bit field insertion, field specified as immediate; 2-cycle, 2-word. aD = insert(aS, arM) Bit field insertion, field specified in arM; 2-cycle.
Note:
The bit field to be inserted or extracted is specified as follows. The width (in bits) of the field is the upper byte of the operand (immediate or arM), and the offset from the LSB is in the lower byte.
Alternate Accumulator Set:
aD = aS:aa0 Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle. aD = aS:aa1 Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle.
Note:
The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator.
Table 19. Replacement Table for F3 ALU Instructions and F4 BMU Instructions
Replace Value Meaning
aD, aT, aS a0 or a1 One of the two accumulators.
IM16 immediate 16-bit data, sign-, zero-, or one-extended as appropriate.
arM ar<0—3> One of the auxiliary BMU registers.
42 Lucent Technologies Inc.
Page 43
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)

Cache Instruction s

Cache instructions require one word of program memory. The do instruction executes in one instruction cycle, and
redo
the
instruction executes in two instruction cycles. (If PC points to external memory, add programmed wait­states.) Control instructions and long immediate values cannot be stored inside the cache. The instruction formats are as follows:
do K {
instr1
instr2
.
.
.
instrN
}
redo K
Table 20. Replacement Table for Cache Instructions
Replace Instruction
Meaning
Encoding
K
cloop
Number of times the instructions are to be executed taken from bits 0—6 of the
cloop
register.
1 to 127 Number of times the instructions to be executed is encoded in the instruction.
N 1 to 15 1 to 15 instructions can be included.
† The assembly-language statement, do
register. K is encoded as 0 in the instruction encoding to select
cloop
(or redo
cloop
), is used to specify that the number of iterations is to be taken from the
cloop
.
cloop
When the cache is used to execute a block of instructions, the cycle timings of the instructions are as follows:
1. In the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of-
cache values, except for the last instruction in the block of NI instructions. This instruction executes in two cycles.
2. During pass two through pass K – 1, each instruction is fetched from cache and the in-cache timings apply.
3. During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except
that the timing of the last instruction is the same as if it were out-of-cache.
4. If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.
redo
The Using the
The number of iterations, K, for a do or
cloop
value of
instruction treats the instructions currently in the cache memory as another loop to be executed K times.
redo
instruction, instructions are reexecuted from the cache without reloading the cache.
redo
can be set at run time by first moving the number of iterations into the
register (7 bits unsigned), and then issuing the do
cloop
is decremented to 0; hence,
cloop
needs to be written before each
cloop
or redo
cloop
. At the completion of the loop, the
do cloop or redo cloop
.
Lucent Technologies Inc. 43
Page 44
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)

Data Move Instructions

Data move instructions normally execute in two instruction cycles. (If PC or rM point to external memory, any pro­grammed wait-states must be added. In addition, if PC and rM point to the same bank of DPRAM, then one cycle must be added.) Immediate data move instructions require two words of program memory; all other data move in­structions require only one word. The only exception to these statements is a special case immediate load (short immediate) instruction. If a YAAU register is loaded with a 9-bit short immediate value, the instruction requires only one word of memory and executes in one instruction cycle. All data move instructions, except those doing long im­mediate loads, can be executed from within the cache. The data move instructions are as follows:
R = IM16
aT[l] = R
SR = IM9
Y = R
R = Y
Z : R
R = aS[l]
DR = *(OFFSET)
(OFFSET) = DR
*
Table 21. Replacement Table for Data Move Instructions
Replace Value Meaning
R Any of the registers in Table 51
DR r<0—3>, a0[l], a1[l], y[l], p, pl, x,
Subset of registers accessible with direct addressing.
pt, pr, psw
aS, aT a0, a1 High half of accumulator.
Y Z
rM, *rM++, *rM--, *rM++j Same as in multiply/ALU instructions.
*
rMzp, *rMpz, *rMm2, *rMjk Same as in multiply/ALU instructions.
*
IM16 16-bit value Long immediate data.
IM9 9-bit value Short immediate data for YAAU registers.
OFFSET 5-bit value from instruction
11-bit value in base register
Value in bits [15:5] of ybase register form the 11 most significant bits of the base address. The 5-bit offset is concatenated to this to form a 16-bit address.
SR r<0—3>, rb, re, j, k Subset of registers for short immediate.
Notes: sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable.
When signed registers less than 16 bits wide (c0, c1, c2) are read, their contents are sign-extended to 16 bits. When unsigned registers less than 16 bits wide are read, their contents are zero-extended to 16 bits.
Loading an accumulator with a data move instruction does not affect the flags.
44 Lucent Technologies Inc.
Page 45
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)

5.2 Register Settings

Tables 22 through 38 describe the programmable registers of the DSP1627 device. Table 40 describes the register settings after reset.
Note that the following abbreviations are used in the tables:
x = don't care
R = read only
W = read/write
The reserved (RSVD) bits in the tables should always be written with zeros to make the program compatible with future chip versions.
Table 22. Serial I/O Control Registers sioc
Bit
Field
* See tdms register, SYNC field.
10987654321 0
DODLY LD CLK MSB OLD ILD OCK ICK OLEN ILEN
Field Value Description
DODLY 0
DO changes on the rising edge of OCK.
1
DO changes on the falling edge of OCK. This delay in driving DO increases the hold time on DO by half a cycle of OCK.
LD 0
CLK 00
MSB 0
OLD 0
ILD 0
OCK 0
ICK 0
OLEN 0
ILEN 0
In active mode, ILD1 and/or OLD1 = ICK1/16, active SYNC1 = ICK1/[128/256*].
1
In active mode, ILD1 and/or OLD1 = OCK1/16, active SYNC1 = OCK1/[128/256*]. Active clock = CKI/2 (1X).
Active clock = CKI/6 (1X).
01
Active clock = CKI/8 (1X).
10
Active clock = CKI/10 (1X).
11
LSB first.
1
MSB first. OLD1 is an input (passive mode).
1
OLD1 is an output (active mode). ILD1 is an input (passive mode).
1
ILD1 is an output (active mode). OCK1 is an input (passive mode).
1
OCK1 is an output (active mode). ICK1 is an input (passive mode).
1
ICK1 is an output (active mode). 16-bit output.
1
8-bit output. 16-bit input.
1
8-bit input.
sioc2
Bit
Field
† See tdms register, SYNC field. ‡ The bit definitions of the sioc2 register are identical to the sioc register bit definitions.
109876543210
DODLY2 LD2 CLK2 MSB2 OLD2 ILD2 OCK2 ICK2 OLEN2 ILEN2
Lucent Technologies Inc. 45
Page 46
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)
Table 23. Time-Division Multiplex Slot Registers tdms
Bit
Field
9 8 7654321 0
SYNCSP MODE TRANSMIT SLOT SYNC
Field Value Description
SYNCSP
0‡
SYNC1 = ICK1/128 if LD = 0 SYNC1 = OCK1/128 if LD = 1*.
1
SYNC1 = ICK1/256 if LD = 0*. SYNC1 = OCK1/256 if LD = 1*.
MODE 0 Multiprocessor mode off; DOEN1 is an input (passive mode).
1 Multiprocessor mode on; DOEN1 is an output (active mode).
TRANSMIT SLOT 1xxxxxx Transmit slot 7.
x1xxxxx Transmit slot 6. xx1xxxx Transmit slot 5. xxx1xxx Transmit slot 4. xxxx1xx Transmit slot 3. xxxxx1x Transmit slot 2. xxxxxx1 Transmit slot 1.
SYNC 1 Transmit slot 0, SYNC1 is an output (active mode).
0 SYNC1 is an input (passive mode).
* See sioc register, LD field. ‡ Select this mode when in multiprocessor mode.
*
.
§
tdms2
Bit
Field
† See sioc register, LD field. ‡ Select this mode when in multiprocessor mode.
§ The tdms2 register bit definitions are identical to the tdms register bit definitions.
9 8 7654321 0
SYNCSP2
MODE2 TRANSMIT SLOT2 SYNC2
46 Lucent Technologies Inc.
Page 47
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)
Table 24. Serial Receive/Transmit Address Registers srta
Bit
Field
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RECEIVE ADDRESS TRANSMIT ADDRESS
Field Value Description
RECEIVE ADDRESS 1xxxxxxx Receive address 7.
x1xxxxxx Receive address 6. xx1xxxxx Receive address 5. xxx1xxxx Receive address 4. xxxx1xxx Receive address 3. xxxxx1xx Receive address 2. xxxxxx1x Receive address 1. xxxxxxx1 Receive address 0.
TRANSMIT ADDRESS 1xxxxxxx Transmit address 7.
x1xxxxxx Transmit addre ss 6. xx1xxxxx Transmit address 5. xxx1xxxx Transmit address 4. xxxx1xxx Transmit address 3. xxxxx1xx Transmit address 2. xxxxxx1x Transmit address 1. xxxxxxx1 Transmit address 0.
srta2
Bit
Field
† The srta2 field definitions are identical to the srta register field definitions.
1514131211109876543210
RECEIVE ADDRESS2 TRANSMIT ADDRESS2
Table 25. Multiprocessor Protocol Registers saddx
Bit Field
Write Read
saddx2
Read Protocol Field [7:0] 0
Bit Field
Write Read
‡ The saddx2 field definitions are identical to the saddx register field definitions.
Read Protocol2 Field [7:0] 0
15—8 7—0
X Write Protocol Field [7:0]
15—8 7—0
X Write Protocol2 Field [7:0]
Lucent Technologies Inc. 47
Page 48
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)
Table 26. Processor Status Word (psw) Register
Bit
Field
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAU FLAGS X X a1[V] a1[35:32] a0[V] a0 [35 :32]
Field V alue Description
DAU FLAGS
*
Wxxx LMI — logical minus when set (bit 35 = 1). xWxx LEQ — logical equal when set (bit [35:0] = 0). xxWx LLV — logical overflow when set. xxxW LMV — mathematical overflow when set.
a1[V] W Accumulator 1 (a1) overflow when set.
a1[35:32] Wxxx Accumulator 1 (a1) bit 35.
xWxx Accumulator 1 (a1) bit 34. xxWx Accumulator 1 (a1) bit 33. xxxW Accumulator 1 (a1) bit 32.
a0[V] W Accumulator 0 (a0) overflow when set.
a0[35:32] Wxxx Accumulator 0 (a0) bit 35.
xWxx Accumulator 0 (a0) bit 34. xxWx Accumulator 0 (a0) bit 33. xxxW Accumulator 0 (a0) bit 32.
* The DAU flags can be set by either BMU or DAU operations.
Table 27. Arithmetic Unit Control (auc) Register
Bit
Field
8 7654321 0
RAND X=Y= CLR SAT ALIGN
Field Value Description
RAND 0
Pseudorandom sequence generator (PSG) reset by writing the pi register only outside an interrupt service routine.
1
X=Y= 0
1
PSG never reset by writing the pi register. Normal operation.
All instructions which load the high half of the y register also load the x regis­ter, allowing single-cycle squaring with p = x * y.
CLR 1xx Clearing yl is disabled (enabled when 0).
x1x Clearing a1l is disabled (enabled when 0). xx1 Clearing a0l is disabled (enabled when 0).
SAT 1x a1 saturation on overflow is disabled (enabled when 0).
x1 a0 saturation on overflow is disabled (enabled when 0).
ALIGN 00 a0, a1
p. 01 a0, a1 ← p/4. 10 a0, a1 ← p x 4 (and zeros written to the two LSBs). 11 a0, a1 ← p x 2 (and zero written to the LSB).
† The auc is 9 bits [8:0]. The upper 7 bits [15:9] are always zero when read and should always be written with zeros to make the program
compatible with future chip versions. The auc register is cleared at reset.
48 Lucent Technologies Inc.
Page 49
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
Table 28. Parallel Host Interface Control (phifc) Register
Bit
Field
PMODE 0
PSTROBE 0
PSTRB 0
PBSELF 0
PFLAG 0
PFLAGSEL 0
PSOBEF 0
15—7 6 5 4 3 2 1 0 RSVD PSOBEF PFLAGSEL PFLAG PBSELF PSTRB PSTROBE PMODE
Field Value Description
1
1
1
1
1
1
1
(continued)
8-bit data transfers. 16-bit data transfers.
Intel
protocol: PIDS and PODS data strobes.
Motorola
When PSTROBE = 1, PODS pin (PDS) active-low. When PSTROBE = 1, PODS pin (PDS) active-high.
In either mode, PBSEL pin = 0 → pdx0 low byte. See Table 7. If PMODE = 0, PBSEL pin = 1 → pdx0 low byte. If PMODE = 1, PBSEL pin = 0 → pdx0 high byte.
PIBF and POBE pins active-high. PIBF and POBE pins active-low.
Normal. PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin un­changed (output buffer empty).
Normal. POBE flag as read through PSTAT register is active-low.
protocol: PRWN and PDS data strobes.
Table 29. Interrupt Control (inc) Register
Bit
Field
* JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.
Encoding: A 0 disables an interrupt; a 1 enables an interrupt.
Table 30. Interrupt Status (ins) Register
Bit
Field
Encoding: A 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being serviced. If a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared.
15 14—11 10 9 8 7—6 5—4 3 2 1 0
*
JINT
15 14—11 10 9 8 7—6 5—4 3 2 1 0
JINT RSVD OBE2 IBF2 TIME RSVD INT[1:0] PIBF POBE OBE IBF
RSVD OBE2 IBF2 T IME RSVD INT[1:0] PIBF POBE OBE IBF
Lucent Technologies Inc. 49
Page 50
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)
Table 31. timerc Register
Bit
Field
15—7 6 5 4 3—0 RSVD DISABLE RELOAD T0EN PRESCALE
Field Value Description
DISABLE 0
1
RELOAD 0
1
T0EN 0
1
Timer enabled. Timer and prescaler disabled. The period register and timer0 are not reset.
Timer stops after counting down to 0. Timer automatically reloads and repeats indefinitely.
Timer holds current count. Timer counts down to 0.
PRESCALE See table below.
PRESCALE Field
PRESCALE Frequency of
PRESCALE Frequency of
Timer Interrupts
0000 CKO/2 1000 CKO/512 0001 CKO/4 1001 CKO/1024 0010 CKO/8 1010 CKO/2048 0011 CKO/16 1011 CKO/4096 0100 CKO/32 1100 CKO/8192 0101 CKO/64 1101 CKO/16384 0110 CKO/128 1110 CKO/32768 0111 CKO/256 1111 CKO/65536
Timer Interrupts
Table 32. Phase-Locked Loop Control (pllc) Register
Bit
Field
15 14 13 12 11—8 7—5 4—0
PLLEN PLLSEL ICP SEL5V LF[3:0] Nbits[2:0] Mbits[4:0]
Field Value Description
PLLEN 0
1
PLLSEL 0
1
PLL powered down. PLL powered up.
DSP internal clock taken directly from CKI. DSP internal clock taken from PLL.
ICP Charge pump current selection (see Table 64 for proper value).
SEL5V 0
1
3 V operation (see Table 64 for proper value). 5 V operation (see Table 64 for proper value).
LF[3:0] Loop filter setting (see Table 64 for proper value). Nbits[2:0] Encodes N, 1 ≤ N ≤ 8, where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111, then N = 1. Mbits[4:0] Encodes M, 2 ≤ M ≤ 20, where M = Mbits[4:0] + 2, f
INTERNAL CLOCK
= f
CKI
x (M/(2N)).
50 Lucent Technologies Inc.
Page 51
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
Table 33. sbit Register
Bit
Field
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field Value Description
DIREC 1xxxxxxx IOBIT7 is an output (input when 0).
x1xxxxxx IOBIT6 is an output (input when 0). xx1xxxxx IOBIT5 is an output (input when 0). xxx1xxxx IOBIT4 is an output (input when 0). xxxx1xxx IOBIT3 is an output (input when 0). xxxxx1xx IOBIT2 is an output (input when 0). xxxxxx1x IOBIT1 is an output (input when 0). xxxxxxx1 IOBIT0 is an output (input when 0).
VALUE Rxxxxxxx Reads the current value of IOBIT7.
xRxxxxxx Reads the current value of IOBIT6. xxRxxxxx Reads the current value of IOBIT5. xxxRxxxx Reads the current value of IOBIT4. xxxxRxxx Reads the current value of IOBIT3. xxxxxRxx Reads the current value of IOBIT2. xxxxxxRx Reads the current value of IOBIT1. xxxxxxxR Reads the current value of IOBIT0.
(continued)
DIREC[7:0] VALUE[7:0]
Table 34. cbit Register
Bit
Field
*0 ≤ n ≤ 7.
1514131211109876543210
MODE/MASK[7:4] MODE/MASK[3:0] DATA/PAT[7:4] DATA/PAT[3:0]
DIREC[n]
1 (Output) 0 0 Clear 1 (Output) 0 1 Set 1 (Output) 1 0 No Change 1 (Output) 1 1 Toggle
0 (Input) 0 0 No Test 0 (Input) 0 1 No Test 0 (Input) 1 0 Test for Zero 0 (Input) 1 1 Test for One
*
MODE/MASK[n] DATA/PAT[n] Action
Lucent Technologies Inc. 51
Page 52
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
Table 35. alf Register
Bit
Field
Field Value Action
AWAIT 1
LOWPR 1
FLAGS See table below.
Bit Flag Use
13—8 Reserved
7 nmns1 NOT-MINUS-ONE from BMU 6 mns1 MINUS-ONE from BMU 5 evenp EVEN PA RITY fro m BMU 4 oddp ODD PARITY from BMU 3 somef SOME FALSE from BIO 2 somet SOME TRUE from BIO 1 allf ALL FALSE from BIO 0 allt ALL TRUE from BIO
15 14 13—0
A WAIT LOWPR FLAGS
0
0
(continued)
Power-saving standby mode or standard sleep enabled. Normal operation.
The internal DPRAM is addressed beginning at 0x0000 in X space. The internal DPRAM is addressed beginning at 0xc000 in X space.
Table 36. mwait Register
Bit
Field
If the EXM pin is high and the INT1 is low upon reset, the mwait register is initialized to all 1s (15 wait-states for all external memory). Otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset.
Table 37. DSP1627 32-Bit JTAG ID Register
Bit
Field
RESERVED 0
SECURE 0
CLOCK 01
ROMCODE Users ROMCODE ID:
PART ID 0x1C DSP1627x36 with 36K IROM and no EROM in MAP1 or MAP3.
RESERVED SECURE CLOCK ROMCODE PART ID 0x03B
Field Value Mask-Programmable Features
15—12 11—8 7—4 3—0
EROM[3:0] ERAMHI[3:0] IO[3:0] ERAMLO[3:0]
31 30 29—28 27—19 18—12 11—0
Nonsecure ROM option.
1
10 11
0x2C DSP1627x32 with 32K IROM and 16K EROM in MAP1 and MAP3.
Secure ROM option. Small-signal input clock option.
Crystal oscill ator input clock o ption. CMOS level input clock option.
The ROMCODE ID is the 9-bit binary value of the following expression: (20 x value for first letter) + (value of second letter), where the values of the letters are in the following table. For example, ROMCODE GK is (20 x 6) + (9) = 129 or 0 1000 0001.
ROMCODE Letter
Value
52 Lucent Technologies Inc.
ABCDEFGHJKLMNPRSTUWY
012345678910111213141516171819
Page 53
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
Table 38. ioc Register
Bit
Field
* The field definitions for the ioc register are different from the DSP1610.
15 14 13 12 11 10 9 8—7 6—4 3—0
RSVD EXTROM CKO2 EBIOH WEROM ESIO2 SIOLBC CKO[1:0] RSVD DENB[3:0]
*
(continued)
ioc Fields
ioc Field Description
EXTROM If 1, sets AB15 low during external memory accesses when WEROM = 1.
CKO2 CKO configuration (see below).
EBIOH If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins.
WEROM If 1, allows writing into external program (X) memory.
ESIO2 If 1, enables SIO2 and low half of BIO, and disables PHIF from pins.
SIOLBC If 1, DO1 and DO2 looped back to DI1 and DI2.
CKO[1:0] CKO configuration (see below).
DENB3 If 1, delay EROM. DENB2 If 1, delay ERAMHI. DENB1 If 1, delay IO. DENB0 If 1, delay ERAMLO.
CKO2 CKO1 CKO0 CKO Output Description
1X PLL — 0 0 0 CKI CKI x M/(2N) Free-running clock. 0 0 1 CKI/(1 + W) CKI x (M/(2N)) / [1 + W]
010 1 1
Wait-state d clock. Held high.*,
*, †
, 0 1 1 0 0 Held low. 1 0 0 CKI CKI Output of CKI buffer. 1 0 1 CKI/(1 + W) CKI x (M/(2N)) / [1 + W]
Sequenced, wait-stated clock.*,
†, ‡, §
1 1 0 Reserved 1 1 1 Reserved
* The phase of CKI is synchronized by the rising edge of RSTB. † When SLOWCKI is enabled in the powerc register, these options reflect the low-speed internal ring oscillator. ‡ The wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see Table 36). During
sequenced external memory accesses, it completes one cycle.
§ The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based on the mwait register setting (see Table 36).
Lucent Technologies Inc. 53
Page 54
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)
Table 39. powerc Register
powerc
The
Bit
Field
Note: The reserved (RSVD) bits should always be written with zeros to make the program compatible with future chip versions.
register configures various power management modes.
15 14 13 12 11 10 9—8 7 6 5 4 3—0
XTLOFF SLOWCKI NOCK INT0EN RSVD INT1EN RSVD SIO1DIS SIO2DIS PHIFDIS TIMERDIS RSVD
powerc fields
Field Description
XTLOFF 1 = powerdown crystal oscillator or small-signal clock input.
SLOWCKI 1 = select ring oscillator clock (internal slow clock).
NOCK 1 = disable internal processor clock. INT0EN 1 = INT0 clears NOCK field. INT1EN 1 = INT1 clears NOCK field.
SIO1DIS 1 = disable SIO1. SIO2DIS 1 = disable SIO2. PHIFDIS 1 = disable PHIF.
TIMERDIS 1 = disable timer.
A • indicates that this bit is unknown on powerup reset and unaffected on subsequent reset. An S indicates that this bit shadows the PC. P indicates the value on an input pin, i.e., the bit in the register reflects the value on the corre­sponding input pin.
Table 40. Register Settings After Reset
Register Bits 15—0 Register Bits 15—0
r0 •••••••••••••••• inc 0000000000000000
r1 •••••••••••••••• ins 0000010000000110
r2 •••••••••••••••• sdx2 ••••••••••••••••
r3 •••••••••••••••• saddx ••••••••••••••••
j •••••••••••••••• cloop 000000000•••••••
k •••••••••••••••• mwait
rb 0000000000000000 saddx2 ••••••••••••••••
re 0000000000000000 sioc2 ••••••0000000000
pt •••••••••••••••• cbit ••••••••••••••••
pr •••••••••••••••• sbit 00000000PPPPPPPP
pi SSSSSSSSSSSSSSSS ioc 0000000000000000
i •••••••••••••••• jtag ••••••••••••••••
p ••••••••••••••••
pl •••••••••••••••• a0 ••••••••••••••••
x •••••••••••••••• a0l •••••••••••••••• y •••••••••••••••• a1 ••••••••••••••••
yl •••••••••••••••• a1l •••••••••••••••• auc 0000000000000000 timerc ••••••••00000000 psw ••••00•••••••••• timer0 0000000000000000
c0 •••••••••••••••• tdms2 ••••••0000000000 c1 ••••••••••••••• srta2 •••••••••••••••• c2 •••••••••••••••• powerc 0000000000000000
sioc ••••••0000000000 pllc 0000000000000000
srta •••••••••••••••• ar0 •••••••••••••••• sdx •••••••••••••••• ar1 ••••••••••••••••
tdms ••••••0000000000 ar2 •••••••••••••••• phifc 0000000000000000 ar3 •••••••••••••••• pdx0 0000000000000000
ybase •••••••••••••••• alf 00000000••••••••
0000000000000000
† If EXM is high and INT1 is low when RSTB goes high, mwait will contain all ones instead of all zeros.
54 Lucent Technologies Inc.
Page 55
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
(continued)

5.3 Instruction Set Formats

This section defines the hardware-level encoding of the DSP1627 device instructions.

Multiply/ALU Instructions

Format 1: Multiply/ALU Read/Write Group
Field
Bit
Format 1a: Multiply/ALU Read/Write Group
Field
Bit
Format 2: Multiply/ALU Read/Write Group
Field
Bit
Format 2a: Multiply/ALU Read/Write Group
Field
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDSF1XY
TaTSF1XY
TDSF1XY
TaTSF1XY

Special Function Instructions

Format 3: F2 ALU Special Functions
Field
Bit
Format 3a: F3 ALU Operations
Field
Bit
Format 3b: BMU Operations
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDSF2 CON
T D S F3 SRC2 aT 0 1
T D S F4[3—1] 0 F4[0] AR
Immediate Operand (IM16)
Immediate Operand (IM16)
Lucent Technologies Inc. 55
Page 56
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture

Control Instructions

Format 4: Branch Direct Group
Field
Bit
Format 5: Branch Indirect Group
Field
Bit
Format 6: Conditional Branch Qualifier/Software Interrupt (icall)
Field
Bit
Note: A branch instruction immediately follows except for a software interrupt (icall).

Data Move Instructions

Format 7: Data Move Group
Field
Bit
1514131211109876543210
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TJA
TB Reserved0
T SI Reserved CON
TaT R Y/Z
(continued)
Format 8: Data Move (immediate operand—2 words)
Field
Bit
Format 9: Short Immediate Group
Field
Bit
Format 9a: Direct Addressing
Field
Bit

Cache Instruction s

Format 10: Do/Redo
Field
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1514131211109876543210
T D R Reserved
Immediate Operand (IM16)
T I Short Immediate Operand (IM9)
T R/W DR 1 OFFSET
TNI K
56 Lucent Technologies Inc.
Page 57
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
Field Descriptions Table 41. T Field
Specifies the type of instruction.
T Operation Format
0000x goto JA 4 00010 Short imm j, k, rb, re 9 00011 Short imm r0, r1, r2, r3 9 00100 Y = a1[l] F1 1 00101 Z : aT[l] F1 2a 00110 Y F1 1 00111 aT[l] = Y F1 1a 01000 Bit 0 = 0, aT = R 7 01000 Bit 0 = 1, aTl = R 7 01001 Bit 10 = 0, R = a0 7 01001 Bit 10 = 1, R = a0l 7 01010 R = IM16 8 01011 Bit 10 = 0, R = a1 7 01011 Bit 10 = 1, R = a1l 7 01100 Y = R 7 01101 Z : R 7 01110 do, redo 10 01111 R = Y 7
1000x call JA 4 10010 ifc CON F2 3 10011 if CON F2 3 10100 Y = y[l] F1 1 10101 Z : y[l] F1 2 10110 x = Y F1 1 10111 y[l] = Y F1 1 11000 Bit 0 = 0, branch indirect 5 11000 Bit 0 = 1, F3 ALU 3a 11001 y = a0 x = X F1 1 11010 Cond. branch qualifier 6 11011 y = a1 x = X F1 1 11100 Y = a0[l] F1 1 11101 Z : y x = X F1 2 11110 Bit 5 = 0, F4 ALU (BMU) 3b 11110 Bit 5 = 1, direct addressing 9a 11111 y = Y x = X F1 1
Table 42. D Field
Specifies a destination accumulator.
DRegister
0 Accumulator 0 1 Accumulator 1
(continued)
Table 43.
Specifies transfer accumulator.
Table 44. S Field
Specifies a source accumulator.
Table 45. F1 Field
Specifies the multiply/ALU function.
Table 46. X Field
Specifies the addressing of ROM data in two-operand multiply/ALU instructions. Specifies the high or low half of an accumulator or the y register in one-operand mul­tiply/ALU instructions.
Field
aT
aT Register
0 Accumulator 1 1 Accumulator 0
SRegister
0 Accumulator 0 1 Accumulator 1
F1 Operation
0000 aD = pp = x * y 0001 aD = aS + pp = x * y
pt++
*
pt++i
*
y
0010 p = x * 0011 aD = aS – pp = x * y 0100 aD = p 0101 aD = aS + p 0110 nop 0111 aD = aS – p 1000 aD = aS | y 1001 aD = aS ^ y 1010 aS & y 1011 aS – y 1100 aD = y 1101 aD = aS + y 1110 aD = aS & y 1111 aD = aS – y
X Operation
Two-Operand Multiply/ALU
0 1
One-Operand Multiply/ALU 0aTl, yl 1aTh, yh
Lucent Technologies Inc. 57
Page 58
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture
(continued)
Table 47. Y Field
Specifies the form of register indirect addressing with postmodification.
Y Operation
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
r0
*
r0++
*
r0--
* r0++j
*
r1
*
r1++
*
r1--
* r1++j
*
r2
*
r2++
*
r2--
* r2++j
*
r3
*
r3++
*
r3--
* r3++j
*
Table 48. Z Field
Specifies the form of register indirect compound ad­dressing with postmodification.
ZOperation
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
r0zp
*
r0pz
*
r0m2
*
r0jk
*
r1zp
*
r1pz
*
r1m2
*
r1jk
*
r2zp
*
r2pz
*
r2m2
*
r2jk
*
r3zp
*
r3pz
*
r3m2
*
r3jk
*
Table 49. F2 Field
Specifies the special function to be performed.
F2 Operation
0000 aD = aS >> 1 0001 aD = aS << 1 0010 aD = aS >> 4 0011 aD = aS << 4 0100 aD = aS >> 8 0101 aD = aS << 8 0110 aD = aS >> 16 0111 aD = aS << 16 1000 aD = p 1001 aDh = aSh + 1 1010 aD = ~aS 1011 aD = rnd(aS) 1100 aD = y 1101 aD = aS + 1 1110 aD = aS 1111 aD = – aS
Table 50. CON Field
Specifies the condition for special functions and condi­tional control instructions.
CON Condition CON Condition
00000 mi 01110 true 00001 pl 01111 false 00010 eq 10000 gt 00011 ne 10001 le 00100 lvs 10010 allt 00101 lvc 10011 allf 00110 mvs 10100 somet 00111 mvc 10101 somef 01000 heads 10110 oddp 01001 tails 10111 evenp 01010 c0ge 11000 mns1 01011 c0lt 11001 nmns1 01100 c1ge 11010 npint 01101 c1lt 11011 njint
11100 lock
Other
Reserved
codes
58 Lucent Technologies Inc.
Page 59
Data Sheet March 2000 DSP1627 Digital Signal Processor
5 Software Architecture
Table 51. R Field
Specifies the register for data move instructions.
R Register R Register
000000 r0 100000 inc 000001 r1 100001 ins 000010 r2 100010 sdx2 000011 r3 100011 saddx 000100 j 100100 cloop 000101 k 100101 mwait 000110 rb 100110 saddx2 000111 re 100111 sioc2 001000 pt 101000 cbit 001001 pr 101001 sbit 001010 pi 101010 ioc 001011 i 101011 jtag 001100 p 101100 Reserved 001101 pl 101101 Reserved 001110 pllc 101110 Reserved 001111 Reserved 101111 Reserved 010000 x 110000 a0 010001 y 110001 a0l 010010 yl 110010 a1 010011 auc 110011 a1l 010100 psw 110100 timerc 010101 c0 110101 timer0 010110 c1 110110 tdms2 010111 c2 110111 srta2 011000 sioc 111000 powerc 011001 srta 111001 Reserved 011010 sdx 111010 ar0 011011 tdms 111011 ar1 011100 phifc 111100 ar2 011101 pdx0 111101 ar3 011110 Reserved 111110 Reserved 011111 ybase 111111 alf
(continued)
Table 52. B Field
Specifies the type of branch instruction (except software interrupt).
B Operation
000 return 001 ireturn 010 goto pt 011 call pt 1xx R eserved
Table 53. DR Field
DR Value Register
0000 r0 0001 r1 0010 r2 0011 r3 0100 a0 0101 a0l 0110 a1 0111 a1l 1000 y 1001 yl 1010 p 1011 pl 1100 x 1101 pt 1110 pr 1111 psw
Table 54. I Field
Specifies a register for short immediate data move in­structions.
IRegister
00 r0/j 01 r1/k 10 r2/rb 11 r3/re
Table 55. SI Field
Specifies when the conditional branch qualifier instruc­tion should be interpreted as a software interrupt in­struction.
SI Operation
0 Not a software interrupt 1 Software interrupt
Lucent Technologies Inc. 59
Page 60
Data Sheet
DSP1627 Digital Signal Processor March 2000
5 Software Architecture

NI Field

Number of instructions to be loaded into the cache. Zero implies redo operation.

K Field

Number of times the NI instructions in cache are to be executed. Zero specifies use of value in

JA Field

12-bit jump address.

R/W Field

A zero specifies a write, *(O) = DR. A one specifies a read, DR = *(O).
Table 56. F3 Field
Specifies the operation in an F3 ALU instruction.
F3 Operation
1000 aD = aS[h, l] | {aT, IM16, p} 1001 aD = aS[h, l] ^ {aT, IM16, p} 1010 aS[h, l] & {aT, IM16, p} 1011 aS[h, l] {aT, IM16, p} 1101 aD = aS[h, l] + {aT, IM16, p} 1110 aD = aS[h, l] & {aT, IM16, p} 1111 aD = aS[h, l] {aT, IM16, p}
(continued)
cloop
register.
Table 58. BMU Encodings
F4 AR Operation
0000 00xx aD = aS >> arM 0001 00xx aD = aS << arM 0000 10xx aD = aS >>> arM 0001 10xx aD = aS <<< arM 1000 0000 aD = aS 1001 0000 aD = aS 1000 1000 aD = aS 1001 1000 aD = aS 1100 0000 aD = aS >> IM16 1101 0000 aD = aS << IM16 1100 1000 aD = aS >>> IM16 1101 1000 aD = aS <<< IM16 0000 1100 aD = exp(aS) 0001 11xx aD = norm(aS, arM) 1110 0000 aD = extracts(aS, IM16) 0010 00xx aD = extracts(aS, arM) 1110 0100 aD = extractz(aS, IM16) 0010 01xx aD = extractz(aS, arM) 1110 1000 aD = insert(aS, IM16) 1010 10xx aD = insert(aS, arM) 0111 0000 aD = aS:aa0 0111 0001 aD = aS:aa1
Note: xx encodes the auxiliary register to be used. 00 (ar0), 01(ar1),
10 (ar2), or 11(ar3).
>> aS
<< aS >>> aS <<< aS
Table 57. SRC2 Field
Specifies operands in an F3 ALU instruction.
SRC2 Operands
00 aS l, IM16 10 aSh, IM16 01 aS, aT 11 aS, p
60 Lucent Technologies Inc.
Page 61
Data Sheet March 2000 DSP1627 Digital Signal Processor

6 Signal Descriptions

EXTERNAL
MEMORY
INTERFACE
SERIAL
INTERFACE #1
AB[15:0] DB[15:0]
RWN EXM
EROM
ERAMHI
ERAMLO
DO1
OLD1
OCK1
OBE1
DI1 ILD1 ICK1
IBF1
SYNC1 SADD1 DOEN1
16 16
IO
DSP1627
RSTB CKO CKI2 CKI STOP
2
INT[1:0]
4
VEC[3:0] OR IOBIT[4:7] IACK TRAP
PSTAT OR DO2 PODS OR OLD2 PCSN OR OCK2 POBE OR OBE2 PBSEL OR SYNC2 PB0 OR ICK2 PIDS OR ILD2
PB1 OR DI2 PIBF OR IBF2 PB2 OR DOEN2 PB3 OR SADD2
4
PB[7:4] OR IOBIT[3:O]
TDI TDO
TCK TMS
SYSTEM
INTERFACE
OR
CONTROL I/O
INTERFACE
PARALLEL HOST
INTERFACE
SERIAL INTERFACE #2
OR
AND CONTROL I/O
INTERFACE
JTAG TEST
INTERFACE
Figure 8. DSP1627 Pinout by Interface
Figure 8 shows the pinout for the DSP1627. The signals can be separated into five interfaces as shown. These interfaces and the signals that comprise them are de­scribed below.

6.1 System Interface

The system interface consists of the clock, interrupt, and reset signals for the processor.
RSTB Reset:
causes the processor to enter the reset state. The auc, powerc, sioc, sioc2, phifc, pdx0, tdms, tdms2, timerc, timer0, sbit (upper byte), inc, ins (except OBE, OBE2,
Negative assertion. A high-to-low transition
5-4006 (C)
and PODS status bits set), alf (upper 2 bits, AWAIT and LOWPR), ioc, rb, and re registers are cleared. The mwait register is initialized to all 0s (zero wait-states) unless the EXM pin is high and the INT1 pin is low. In that case, the mwait register is initialized to all 1s (15 wait-states).
Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2. The DAU condition flags are not affected by reset. IOBIT[7:0] are initialized as inputs. If any of the IOBIT pins are switched to outputs (by writing sbit), their initial value will be logic zero (see Table 40, Register Settings After Reset).
Upon negation of the signal, the processor begins exe­cution at location 0x0000 in the active memory map (see Section 4.4, Memory Maps and Wait-States).
Lucent Technologies Inc. 61
Page 62
Data Sheet
DSP1627 Digital Signal Processor March 2000
6 Signal Descriptions
(continued)
CKI Input Clock:
A mask-programmable option selects one of three possible input buffers for the CKI pin (see Sec­tion 7, Mask-Programmable Options, and Table 1, Pin Descriptions). The internal CKI from the output of the selected input buffer can then drive the internal proces­sor clock directly (1X) or drive the on-chip PLL (see Sec­tion 4.13 ). The PLL al lows th e CKI input clock to be at a lower frequency than the internal processor clock.
CKI2 Input Clock 2:
Used with mask-programmable input clock options which require an external crystal or small signal differential across CKI and CKI2 (see Table 1, Pin Descriptions). When the CMOS option is selected, this pin should be tied to V
SSA
.

STOP

A free-running output clock that runs at the CKI rate, in­dependent of the is only available with the crystal and small-signal clock options. When the PLL is selected, the CKO frequency equals the input CKI frequency regardless of how the PLL is programmed.
A logic 0.
A logic 1.
powerc
register setting. This option
INT[1:0] Processor Interrupts 0 and 1:
Positive asserti on. Hardware interrupt inputs to the DSP1627. Each is en­abled via the inc register. When enabled and asserted, each cause the processor to vector to the memory loca­tion described in Table 4. INT1 is used in conjunction with EXM to select the desired reset initialization of the mwait register (see Table 36). When both INT0 and RSTB are asserted, all output and bidirectional pins (ex­cept TDO, which 3-states by JTAG control) are put in a 3-state condition.
Stop Input Clock:
Negative assertion. A high-to-low transition synchronously stops all of the internal proces­sor clocks leaving the processor in a defined state. Re­turning the pin high will synchronously restart the processor clocks to continue program execution from where it left off without any loss of state. This hardware feature has the same effect as setting the NOCK bit in the powerc register (see Table 39).
CKO Clock Out:
Buffered output clock with options program­mable via the ioc register (see Table 38). The selectable CKO options (see Tables 38 and 29) ar e as follow s:
A free-running output clock at the frequency of the in­ternal processor clock; runs at the internal ring oscilla­tor frequency when SLOWCKI is enabled.
A wait-stated clock based on the internal instruction cy­cle; runs at the internal ring oscillator frequency when SLOWCKI is enabled.
A sequenced, wait-stated clock based on the EMI se­quencer cycle; runs at the internal ring oscillator fre­quency when SLOWCKI is enabled.
VEC[3:0] Interrupt Output Vector:
These four pins indicate which interrupt is currently being serviced by the device. Table 4 shows the code associated with each interrupt condition. VEC[3:0] are multiplexed with IOBIT[4:7].
IACK Interrupt Acknowledge:
Positive assertion. IACK signals when an interrupt is being serviced by the DSP1627. IACK remains asserted while in an interrupt service routine, and is cleared when the ireturn instruc­tion is executed.
TRAP Trap Signal:
Positive assertion. When asserted, the processor is put into the trap condition, which normally causes a branch to the location 0x0046. The hardware development system (HDS) can configure the trap pin to cause an HDS trap, which causes a branch to loca­tion 0x0003. Although normally an input, the pin can be configured as an output by the HDS. As an output, the pin can be used to signal an HDS breakpoint in a multi­ple processor environment.
62 Lucent Technologies Inc.
Page 63
Data Sheet March 2000 DSP1627 Digital Signal Processor
6 Signal Descriptions
(continued)

6.2 External Memory Interface

The external memory interface is used to interface the DSP1627 to external memory and I/O devices. It sup­ports read/write operations from/to program and data memory spaces. The interface supports four external memory segments. Each external memory segment can have an independent number of software-program­mable wait-states. One hardware address is decoded, and an enable line is provided, to allow glueless I/O in­terfacing.
AB[15:0] External Memory Address Bus:
This 16-bit bus supplies the address for read or write operations to the external memory or I/O. During exter­nal memory accesses, AB[15:0] retain the value of the last valid external access.
DB[15:0] External Memory Data Bus:
data bus is used for read or write operations to the ex­ternal memory or I/O.
Output only.
This 16-bit bidirectional
EROM External ROM Enable Signal:
When asserted, the signal indicates an access to external program memory (see Table 5, Instruction/Co­efficient Memory Maps). This signal's leading edge can be delayed via the ioc register (see Table 38).
ERAMHI External RAM High Enable Signal:
tion. When asserted, the signal indicates an access to external data memory addresses 0x8000 through 0xFFFF (see Table 6, Data Memory Map). This signal's leading edge can be delayed via the ioc register (see Table 38).
ERAMLO External RAM Low Enable Signal:
tion. When asserted, the signal indicates an access to external data memory addresses 0x4100 through 0x7FFF (see Table 6, Data Memory Map). This signal's leading edge can be delayed via the ioc register (see Table 38).
IO
Negative assertion.
Negative asser-
Negative asser-
RWN Read/Write Not:
the memory access is a read operation. When a logic 0, the memory access is a write operation.
EXM External Memory Select:
latched into the device on the rising edge of RSTB. The value of EXM latched in determines whether the internal ROM is addressable in the instruction/coefficient mem­ory map. If EXM is low, internal ROM is addressable. If EXM is high, only external ROM is addressable in the instruction/coefficient memory map (see Table 5, In­struction/Coefficient Memory Maps). EXM chooses be­tween MAP1 or MAP2 and between MAP3 or MAP4.
When a logic 1, the pin indicates that
Input only. This signal is
External I/O Enable Signal:
asserted, the signal indicates an access to external data memory addresses 0x4000 through 0x40FF (see Table 6, Data Memory Map). This memory segment is intended for memory-mapped I/O. This signal's leading edge can be delayed via the ioc register (see Table 38).
Negative assertion. When
Lucent Technologies Inc. 63
Page 64
Data Sheet
DSP1627 Digital Signal Processor March 2000
6 Signal Descriptions
(continued)

6.3 Serial Interface #1

The serial interface pins implement a full-featured syn­chronous/asynchronous serial I/O channel. In addition, several pins offer a glueless TDM interface for multipro­cessing communication applications (see Figure 5, Mul­tiprocessor Communicat ion s and Conn ections).
DI1 Data Input:
ICK1, either LSB or MSB first, according to the sioc reg­ister MSB field (see Table 22).
ICK1 Input Clock:
mode, ICK1 is an output; in passive mode, ICK1 is an input, according to the sioc register ICK field (see Table 22). Input has typically 0.7 V hysteresis.
ILD1 Input Load:
sdx[in], from the input shift register isr. A falling edge of ILD1 indicates the beginning of a serial input word. In active mode, ILD1 is an output; in passive mode, ILD1 is an input, according to the sioc register ILD field (see Table 22). Input has typically 0.7 V hysteresis.
IBF1 Input Buffer Full:
when the input buffer, sdx[in], is filled. IBF1 is negated by a read of the buffer, as in a0 = sdx. IBF1 is also ne­gated by asserting RSTB.
DO1 Data Output:
shift register (osr), either LSB or MSB first (according to the sioc register MSB field). DO1 changes on the rising edges of OCK1. DO1 is 3-stated when DOEN1 is high.
DOEN1 Data Output Enable:
when not in the multiprocessor mode. DO1 and SADD1 are enabled only if DOEN1 is low. DOEN1 is bidirection­al when in the multiprocessor mode (tdms register MODE field set). In the multiprocessor mode, DOEN1 indicates a valid time slot for a serial output.
Serial data is latched on the rising edge of
The clock for serial input data. In active
The clock for loading the input buffer,
Positive assertion. IBF1 is asserted
The serial data output from the output
Negative assertion. An input
OCK1 Output Clock:
mode, OCK1 is an output; in passive mode, OCK1 is an input, according to the sioc register OCK field (see Ta­ble 22). Input has typically 0.7 V hysteresis.
OLD1 Output Load:
ister, osr, from the output buffer sdx[out]. A falling edge of OLD1 indicates the beginning of a serial output word. In active mode, OLD1 is an output; in passive, OLD1 is an input, according to the sioc register OLD field (see Table 22). Input has typically 0.7 V hysteresis.
OBE1 Output Buffer Empty:
serted when the output buffer, sdx[out], is emptied (moved to the output shift register for transmission). It is cleared with a write to the buffer, as in sdx = a0. OBE1 is also set by asserting RSTB.
SADD1
Serial Address:
stream typically used for addressing during multiproces­sor communication between multiple DSP16xx devices. In multiprocessor mode, SADD1 is an output when the tdms time slot dictates a serial transmission; otherwise, it is an input. Both the source and destination DSP can be identified in the transmission. SADD1 is always an output when not in multiprocessor mode and can be used as a second 16-bit serial output. See the
The clock for se rial output da ta. In active
The clock for loading the output shift reg-
Positive assertion. OBE1 is as-
Negative assertion. A 16-bit serial bit
DSP1611/17/18/27 Digital Signal Processor Informa­tion Manual
ed when DOEN1 is high. When used on a bus, SADD1 should be pulled high through a 5 kΩ resistor.
SYNC1 Multiprocessor Synchronization:
the multiprocessor mode, a falling edge of SYNC1 indi­cates the first word (time slot 0) of a TDM I/O stream and causes the resynchronization of the active ILD1 and OLD1 generators. SYNC1 is an output when the tdms registe r SY NC fi eld is se t (i. e ., se lect s th e ma ste r DSP and uses time slot 0 for transmit). As an input, SYNC1 must be tied low unless part of a TDM interface. When used as an output, SYNC1 = [ILD1/OLD1]/8 or 16, depending on the setting of the SYNCSP field of the tdms register. When configured as described above, SYNC1 can be used to generate a slow clock for SIO operations. Input has typically 0.7 V hysteresis.
for additional information. SADD1 is 3-stat-
Typically used in
64 Lucent Technologies Inc.
Page 65
Data Sheet March 2000 DSP1627 Digital Signal Processor
6 Signal Descriptions
(continued)

6.4 Parallel Host Interface or Serial Interface #2 and Control I/O Interface

This interface pin multiplexes a parallel host interface with a second serial I/O interface and a 4-bit I/O inter­face. The interface selection is made by writing the ESIO2 bit in the ioc register (see Table 38 and Section 4.1). The functions and signals for the second SIO correspo nd exactly wi th those in SIO #1. Therefore, the pin descriptions below discuss only PHIF and BIO pin functionality.
PB[7:0] Parallel I/O Data Bus:
used to input data to, or output data from, the PHIF. Note that PB[3:0] are pin multiplexed with SIO2 func-
tionality, and PB[7:4] are pin multiplexed with BIO unit pins IOBIT[3:0] (see Section 4.1).
PCSN Peripheral Chip Select Not:
PCSN is an input. While PCSN is low, the data strobes PIDS and PODS are enabled. While PCSN is high, the DSP1627 ignores any activity on PIDS and PODS.
PBSEL Peripheral Byte Select:
software. Selects the hig h or low by te of pd x0 avai lable for host accesses.
PSTAT Peripheral Status Select:
logic 0, the PHIF will output the pdx0[out] register on the PB bus. When a logic 1, the PHIF will output the con­tents of the PSTAT register on PB[7:0].
PIDS Parallel Input Data Strobe:
figurable to support both
Intel
In an external device to indicate that data is available on the PB bus. The DSP latches data on the PB bus on the rising edge (low-to-high transition) of PIDS or PCSN, whichever comes first.
In write strobe. The external device sets PIDS(PRWN*) to a logic 0 to indicate that data is available on the PB bus (write operation by the external device). A logic 1 on PIDS(PRWN*) indicates an external read operation by the external device.
mode: Negative assertion. PIDS is pulled low by
Motorola
mode: PIDS(PRWN*) functions as a read /
This 8-bit bidirectional bus is
Negative assertion.
An input pin, configurable in
PSTAT is an input. When a
An input pin, software con-
Intel
and
Motorola
protocols.
PODS Parallel Output Data Strobe:
configurable to support both cols.
In
Intel
mode: Negative assertion. When PODS is pulled low by an external device, the DSP1627 places the con­tents of the parallel output register, pdx0, onto the PB bus.
In
Motorola
level. The external device uses PODS(PDS strobe for both read and write operations.
PIBF Parallel Input Buffer Full:
assertion; configurable in software. This flag is cleared after reset, indicating an empty input buffer pdx0[in].
PIBF is set immediately after the rising edge of PIDS or PCSN, indicating that data has been latched into the pdx0[in] register. When the DSP1627 reads the con­tents of this register, emptying the buffer, the flag is cleared.
Configured in software, PIBF may become the logical OR of the PIBF and POBE flags.
POBE Parallel Output Buffer Empty:
itive assertion; configurable in software. This flag is set after reset, indicating an empty output buffer pdx0[out].
POBE is set immediately after the rising edge of PODS or PCSN, indicating that the data in pdx0[out] has been driven onto the PB bus. When the DSP1627 writes to pdx0[out], filling the buffer, this flag is cleared.
mode: Software-configurable assertion
An input pin, software
Intel
and
Motorola
An output pin with positive
An output pin with pos-
proto-
*
) as its data

6.5 Control I/O Interface

This interface is used for status and control operations provided by the bit I/O unit of the DSP1627. It is pin mul­tiplexed with the PHIF and VEC[3:0] pins (see Section
4.1). Setting the ESIO2 and EBIOH bits in the ioc regis­ter provides a full 8-bit BIO interface at the associated pins.
IOBIT[7:0] I/O Bits [7:0]:
configured as either an input or an output. As outputs, they can be independently set, toggled, or cleared. As inputs, they can be tested independently or in combina­tions for various data patterns.
*
Motorola
Each of these bits can be independently
mode signal name.
Lucent Technologies Inc. 65
Page 66
Data Sheet
DSP1627 Digital Signal Processor March 2000
6 Signal Descriptions
(continued)

6.6 JTAG Test Interface

The JTAG test interface has features that allow pro­grams and data to be downloaded into the DSP via four pins. This provides extensive test and diagnostic capa­bility. In addition, internal circuitry allows the device to be controlled through the JTAG port to provide on-chip in-circuit emulation. Lucent Technologies provides hardware and software tools to interface to the on-chip HDS via the JTAG port.
Note:
The DSP1627 provides all JTAG/ standard test capabilities including boundary scan. See the
DSP1611/17/18/27 Digital Signal
Processor Information Manual
formation on the JTAG test interface.
TDI Test Data Input:
scanned data and instructions are input on this pin. This pin has an internal pull-up resistor.
JTAG serial input signal. All serial-
IEEE
1149.1
for additional in-
TDO Test Data Output:
scanned data and status bits are output on this pin.
TMS Test Mode Select:
when combined with TCK, controls the scan operations. This pin has an internal pull-up resistor.
TCK Test Clock:
all data into the port through TDI, and out of the port through TDO, and controls the port by latching the TMS signal inside the state-machine controller.
JTAG serial output signal. Serial-
JTAG mode control signal that,
JTAG serial shift clock. This signal clocks
66 Lucent Technologies Inc.
Page 67
Data Sheet March 2000 DSP1627 Digital Signal Processor

7 Mask-Programmable Options

The DSP1627 contains a ROM that is mask-programmable. The selection of several programmable features is made when a custom ROM is encoded. These features select the input clock options, the instruction/coefficient memory map option, and the hardware emulation or ROM security option, as summarized in Table 59.
Table 59. DSP1627 ROM Options
Features Options Comments
Input Clock CMOS Level
Memory Map DSP1627x36
ROM Security Nonsecure
* 1627hds.v
and must reside in the first 4 Kwords of ROM.
† crc16.v
of ROM. See the
#
(# indicates the current version number) is the relocatable HDS object code. It uses approximately 140 words
#
is the cyclic redundancy check object code. It uses approximately 75 words and must reside in the first 4 Kwords
DSP1600 Support Tools Manual
Small Signal
Crystal
DSP1627x32
Secure
for detailed information.
2.7 V, 3.0 V, and 5.0 V.
2.7 V, 3.0 V, and 5.0 V.
2.7 V, 3.0 V, and 5.0 V. 36 Kwords IROM, no EROM in MAP1 or MAP3.
32 Kwords IROM, 16 Kwords EROM in MAP1 and MAP3. Specify and l ink Specify and link
1627hds.v
crc16.v
*
#
, allows emulation.
#
, no emulation capability.

7.1 Input Clock Options

For all input options, the input clock CKI can run at some fraction of the internal clock frequency by setting the PLL multiplication factors appropriately (see Section 4.12, Clock Synthesis). When the PLL is bypassed, the input clock CKI frequency is the internal clock frequency.
If the mask option for using an external crystal is chosen, the internal oscillator may be used as a noninverting input buffer by supplying a CMOS level to the CKI pin and leaving the CKI2 pin open.

7.2 Memory Map Options

The DSP1627 offers a DSP1627x36 or a DSP1627x32 where the difference is in the instruction/coefficient memory maps. The DSP1627x36 contains 36 Kwords of internal ROM (IROM), but it doesn’t support the use of IROM and external ROM (EROM) in the same memory map. The DSP1627x32 supports the use of only 32 Kwords of IROM with 16 Kwords of EROM in the same memory map. See Section 4.4 Memory Maps and Wait-States for further de­scription.

7.3 ROM Security Options

The DSP1600 Hardware Development System (HDS) provides on-chip in-circuit emulation and requires that the re­locatable HDS code be linked to the application code. This code's object file is called 1627hds.v unique version identifier. Refer to the DSP1627-ST software tools release for more specific information. If on-chip in-circuit emulation is desired, a nonsecure ROM must be chosen. If ROM security is desired with the DSP1627, the HDS cannot be used. To provide testing of the internal ROM contents on a secure ROM device, a cyclic redundancy check (CRC) program is called by and linked with the user's source code. The CRC code resides in the first 4 Kwords of ROM.
#
, where # is a
See the
DSP1600 Support Tools Manual
for more detailed information.
Lucent Technologies Inc. 67
Page 68
Data Sheet
DSP1627 Digital Signal Processor March 2000

8 Device Characteristics

8.1 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso­lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
External leads can be bonded and soldered safely at temperatures of up to 300 °C. Voltage Range on V
Voltage Range on V
Voltage Range on Any Pin ............................................................................................ .V
Power Dissipation................................................................................................................................................ 1 W
Ambient Temperature Range ......................................................................................................... –40 °C to +85 °C
Storage Temperature Range
with Respect to Ground Using Devices Designed for 5 V Operation.............–0.5 V to +7 V
DD
with Respect to Ground Using Devices Designed for 3 V Operation..........–0.5 V to +4.6 V
DD
– 0.5 V to V
SS
....................................................................................................................–
65 °C to +150 °C
DD
+ 0.5 V

8.2 Handling Precautions

All MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static charge. Although input protection circuitry has been incorporated into the devices to minimize the effect of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mount­ing. Lucent Technologies employs a human-body model for ESD susceptibility testing. Since the failure voltage of electronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is important that standard values be employed to establish a reference by which to compare test data. Values of 100 pF and 1500 Ω are the most common and are the values used in the Lucent Technologies human-body model test circuit. The breakdown voltage for the DSP1627 is greater than 2000 V.

8.3 Recommended Operating Conditions

Table 60. Recommended Operating Conditions
Maximum
Instruction Rate
(MIPS)
50 20 ns CMOS, small-signal,
80 12.5 ns CMOS, small-signal,
100 10 ns CMOS, small-signal,
70 14 ns CMOS, small-signal,
90 11 ns CMOS, small-signal,
Device Speed Input Clock Package Supply Voltage
V
(V)
DD
Min Max Min Max
crystal
crystal
crystal
crystal
crystal
BQFP
or TQFP
BQFP
or TQFP
BQFP
or TQFP
BQFP
or TQFP
BQFP
or TQFP
2.7 3.3 –40 85
2.7 3.3 –40 85
3.0 3.6 –40 85
4.75 5.25 –40 85
4.75 5.25 –40 85
Ambient Temperature
TA (
C)
°°°°
The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL (referred to as 1X operation) and M/(2N) with the PLL selected (see Section 4.12). Device speeds greater than 50 MIPS do not support 1X operation; use the PLL.
68 Lucent Technologies Inc.
Page 69
Data Sheet March 2000 DSP1627 Digital Signal Processor
8 Device Characteristics
(continued)

8.4 Package Thermal Considerations

The recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. The following equations describe the relationship between these parameters. If the applications' maximum power is less than the worst-case value, this relationship determines a higher maximum am­bient temperature or the maximum temperature measured at top dead center of the package.
T
= TJ – P x
A
T
= TJ – P x
TDC
where TA is the still-air ambient temperature and T dead center of the package.
Maximum Junction Temperature (T 100-pin BQFP Maximum Thermal Resistance in Still-Air-Ambient ( 100-pin BQFP Maximum Thermal Resistance, Junction to Top Dead Center ( Maximum Junction Temperature (T 100-pin TQFP Maximum Thermal Resistance in Still-Air-Ambient ( 100-pin TQFP Maximum Thermal Resistance, Junction to Top Dead Center (
WARNING: Due to package thermal constraints, proper precautions in the user's application should be tak-
Θ
JA
Θ
J-TDC
is the temperature measured by a thermocouple at the top
TDC
) in 100-Pin BQFP................................................................................. 125 °C
J
Θ
).....................................................55 °C/W
JA
Θ
) in 100-Pin TQFP ................................................................................. 125 °C
J
Θ
) ..................................................... 30 °C/W
JA
Θ
)...............................12 °C/W
J-TDC
).................................6 °C/W
J-TDC
en to avoid exceeding the maximum junction temperature of 125 °C. Otherwise, the device will be affected adversely.
Lucent Technologies Inc. 69
Page 70
Data Sheet
DSP1627 Digital Signal Processor March 2000

9 Electrical Characteristics and Requirements

The following electrical characteristics are preliminary and are subject to change. Electrical characteristics refer to the behavior of the device under specified conditions. Electrical requirements refer to conditions imposed on the user for proper operation of the device. The parameters below are valid for the conditions described in Section 8.3, Recommended Operating Cond iti ons .
Table 61. Electrical Characteristics and Requirements
Parameter Symbol Min Max Unit
Input Voltage:
Low High
Input Current (except TMS, TDI):
Low (V High (VIH = 5.25 V, VDD = 5.25 V)
Input Current (TMS, TDI):
Low (V High (VIH = 5.25 V, VDD = 5.25 V)
Output Low Voltage:
Low (I Low (IOL = 50 µA)
Output High Voltage:
High (I High (IOH = –50 µA)
Output 3-State Current:
Low (V High (VDD = 5.25 V, VIH = 5.25 V)
Input Capacitance
= 0 V, VDD = 5.25 V)
IL
= 0 V, VDD = 5.25 V)
IL
= 2.0 mA)
OL
= –2.0 mA)
OH
= 5.25 V, VIL = 0 V)
DD
V
V
I
I
I
I
V V
V V
I
OZL
I
OZH
IL
IH
IL IH
IL IH
OL OL
OH OH
–0.3 0.3 * V
0.7 * V
DD
VDD + 0.3 V
DD
–5
—5µA
–100
—5µA
—0.4V —0.2V
VDD – 0.7 V VDD – 0.2 V
–10
—10µA
CI 5 pF
V
µ
A
µ
A
µ
A
Table 62. Electrical Requirements for Mask-Programmable Input Clock Options
Parameter Symbol Min Max Unit
CKI CMOS Level Input Voltage:
Low High
Small-signal Peak-to-pea k Volta ge
(on CKI)
Small-signal Input Duty Cycle Small-signal Input Voltage Range
(pins: CKI, CKI2) Small-signal Buffer Frequency Range Frequency Range of Fundamental Mode or Overtone
Crystal Series Resistance of Fundamental Mode or Overtone
Crystal (pins: CKI, CKI2) Mutual Capacitance of Crystal
(includes board stray capa citance)
* The small-signal buffer must be used in single-ended mode where an ac waveform (sine or square) is applied to CKI and a dc voltage approx-
imately equal to the average value of CKI is appl ied to CKI2, as shown in t he figure below. The maximum allowable ripple on CKI2 is 100 mV.
† Duty cycle for a sine wave is defined as the percentage of time during each clock cycle that the voltage on CKI exceeds the voltage on CKI2.
CKI
CKI2
*
V
IL
V
IH
–0.3 0.3 * V
0.7 * V
DD
VDD + 0.3 V
DD
Vpp 0.6 V
DCyc 45 55 %
Vin 0.2 * V
DD
0.6 * V
DD
fss 35 MHz
fX 5 25 MHz
RS 40
C0 7 pF
V
V
70 Lucent Technologies Inc.
Page 71
Data Sheet March 2000 DSP1627 Digital Signal Processor
9 Electrical Characteristics and Requirements
Additional Electrical Requirements with Crystal Option:
(continued)
See Section 13, Crystal Electrical Characteristics and
Requirements.
Table 63. PLL Electrical Specifications, VCO Frequency Ranges
Parameter Symbol Min Max Unit
VCO frequency range (V VCO frequency range (V VCO frequency range (V
10%)
*
±
= 3 V
DD
= 3.0 V – 3.6 V)* f
DD
= 5 V ± 5%)* f
DD
f
VCO VCO VCO
50 160 MHz 50 200 MHz 70 180 MHz
Input Jitter at CKI 200 ps-rms
* The M and N counter values in the pllc register must be set so that the VCO will operate in the appropriate range (see Table 63). Choose the
lowest value of N and then the appropriate value of M for
INTERNAL CLOCK
f
=
f
CKI
x (M/(2N)) =
f
VCO
/2.
Table 64. PLL Electrical Specifications and pllc Register Settings
MV
DD
pllc13 (ICP) pllc12
(SEL5V)
pllc[11:8]
(LF[3:0])
Typical Lock-in Time (
*
s)
µµµµ
23—24 2.7 V – 3.6 V 1 0 1011 30 21—22 2.7 V – 3.6 V 1 0 1010 30 19—20 2.7 V – 3.6 V 1 0 1001 30 16—18 2.7 V – 3.6 V 1 0 1000 30 12—15 2.7 V – 3.6 V 1 0 0111 30
8—11 2.7 V – 3.6 V 1 0 0110 30
2—7 2.7 V – 3.6 V 1 0 0100 30 19—20 5 V ± 5% 1 1 1110 30 17—18 5 V ± 5% 1 1 1101 30
16 5 V ± 5% 1 1 1100 30 14—15 5 V ± 5% 1 1 1011 30 12—13 5 V ± 5% 1 1 1010 30 10—11 5 V ± 5% 1 1 1001 30
8—9 5 V ± 5% 1 1 1000 30
75 V ± 5% 1 1 0111 30 5—6 5 V ± 5% 1 1 0110 30 2—4 5 V ± 5% 1 1 0101 30
* Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL output clock is un stable. The
DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the PLL is locking. Completion of the lock-in interval is indicated by assertion of the LOCK flag.
Lucent Technologies Inc. 71
Page 72
Data Sheet
DSP1627 Digital Signal Processor March 2000
9 Electrical Characteristics and Requirements
DD
V
VDD – 0.1
(V)
DD
– 0.2
V
OH
V
DD
– 0.3
V
DD
V
– 0.4
01020304051525354550
IOH (mA)
(continued)
DEVICE UNDER
TEST
OH
I
OH
V
5-4007 (F).a
(V)
OL
V
Figure 9. Plot of V
vs. IOH Under Typical Operating Conditions
OH
0.4
0.3
0.2
0.1
0
0 5 10 15 20 25 30 35 40 45 50
OL
(mA)
I
DEVICE
UNDER
TEST
OL
I
5-4008 (F).b
OL
V
Figure 10. Plot of V
vs. IOL Under Typical Operating Conditions
OL
72 Lucent Technologies Inc.
Page 73
Data Sheet March 2000 DSP1627 Digital Signal Processor
9 Electrical Characteristics and Requirements
(continued)

9.1 Power Dissipation

Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power dissipation listed is for a selected application. The following electrical characteristics are preliminary and are subject to change.
Table 65. Power Dissipation and Wake-Up Latency
Operating Mode
(Unused Inputs at VDD or VSS)
Normal Operation ioc = 0x0180
PLL Disabled CKI & CKO = 40 MHz CMOS 220 74 214 72
Crystal Oscillator 241 80 235 78
Small Signal 223 76 217 74 — CKI & CKO = 0 MHz CMOS 0.19 0.067 0.19 0.067
Small Signal 3.0 1.1 3.0 1.1 — Normal Operation ioc = 0x0180
PLL Enabled
pllc = 0xFC0E
CKI = 10 MHz CKO = 40 MHz CMOS 228 77 222 75 — Crystal Oscillator 249 83 243 81
Small Signal 231 78 225 77
Standard Sleep, Ext ernal Interrupt
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
CMOS
Crystal Oscillator
Small Signal
Standard Sleep, Ext ernal Interrupt
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS 33.2 10.9 25.8 7.5 3T*
Crystal Oscillator 54.0 17.1 46.0 14.0 3T*
Small Signal 36.0 12.4 28. 8 9.2 3T*
Sleep with Slow Internal Clock
Crystal/Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
CMOS 1.4 0.4 1.1 0.3 1.5 µs5.0 µs1.5 µs + t
Crystal Oscillator 21.9 6.2 21.8 6.1 1.5 µs5.0 µs1.5 µs + tL5.0 µs + t
Small Signal 3.9 2.1 3.8 2.0 1.5 µs5.0 µs1.5 µs + tL5.0 µs + t
Typical Power Dissipation (mW) Wake-Up Latency
I/O Units ON
powerc[7:4] = 0x0
I/O Units OFF
powerc[7:4] = 0xf
(PLL Not Used
During Wake State)
(PLL Used
During Wake State)
5 V 3 V 5 V 3 V 5 V 3 V 5 V 3 V
Power Management Modes
25.2 8.4 17.8 5.6 3T*
46.2 14.0 38.8 12.0 3T*
28.0 9.8 20.8 7.2 3T*
CKO = 40 MHz
3T* + t 3T* + t 3T* + t
L
L† L† L†
5.0 µs + t
L L L
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
t
L
= PLL lock time (see Table 64).
Lucent Technologies Inc. 73
Page 74
Data Sheet
DSP1627 Digital Signal Processor March 2000
9 Electrical Characteristics and Requirements
Table 65. Power Dissipation and Wake-Up Latency
Operating Mode
(Unused inputs at VDD or VSS)
Typical Power Dissipation (mW) Wake-Up Latency
I/O Units ON
powerc[7:4] = 0x0
(continued)
I/O Units OFF
powerc[7:4] = 0xf
(continued)
During Wake State)
(PLL Not Used
(PLL Used
During Wake State)
5 V 3 V 5 V 3 V 5 V 3 V 5 V 3 V
Sleep with Slow Internal Clock
Crystal/Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS 8.3 3.0 7.5 2.7 1.5 µs5.0 µs
Crystal Oscillator 27.5 9.9 24.5 8.8 1.5 µs5.0 µs
Small Signal 10.0 4.5 10.0 4.0 1.5 µs5.0 µs
Sleep with Slow Internal Clock
Crystal/Small Signal Disabled
powerc[15:14] = 11,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
Crystal Oscillator
Small Signal
0.67 0.24 0.56 0.16 20 ms
0.67 0.24 0.56 0.16 20 µs
20 µs + t 20 µs + t
Software Stop
powerc[15:12] = 0011
PLL Disabled During STOP
CMOS
0.19 0.067 0.19 0.067 3T*
3T* + t
Software Stop
powerc[15:12] = 1111
PLL Disabled During STOP
Crystal Oscillator
Small Signal
0.19 0.067 0.19 0.067 20 ms
0.19 0.067 0.19 0.067 20 µs
20 µs +t
20 µs + t
Hardware Stop (STOP = VSS)
powerc[15:12] = 0000
PLL Disabled During STOP
CMOS 0.19 0.067 0.19 0.067 3T*
Crystal Oscillator 20.0 6.0 20.0 6.0 3T*
Small Signal 3.0 1.1 3.0 1.1 3T*
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Enabled During STOP
CMOS 5.6 2.4 5.6 2.4 3T* 3T*
Crystal Oscillator 25.6 8.4 25.6 8.4 3T* 3T*
Small Signal 8.6 3.5 8.6 3.5 3T* 3T*
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
t
L
= PLL lock time (see Table 64).
L† L†
L†
L†
L†
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the basis
/2
of the application by adding C x V
DD
x f for each output, where C is the additional load capacitance and f is the output
frequency.
74 Lucent Technologies Inc.
Page 75
Data Sheet March 2000 DSP1627 Digital Signal Processor
9 Electrical Characteristics and Requirements
(continued)
Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es­sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh­old of V
/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels
DD
of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec­ommended that unused input and I/O pins be tied to V biguities. Further, if I/O pins are tied high or low, they should be pulled fully to V
or VDD through a 10 kΩ resistor to avoid application am-
SS
or VDD.
SS
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise,
high currents may
flow.

10 Timing Characteristics for 5 V Operation

The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
T
= –40 °C to +85 °C (See Section 8.3.)
A
V
= 5 V ± 5%, VSS = 0 V (See Section 8.3.)
DD
Capacitance load on outputs ( C Output characteristics can be derated as a function of load capacitance (C All outputs: 0.03 ns/pF ≤ dt/dC
) = 50 pF, except for CKO, where CL = 20 pF.
L
).
L
≤ 0.06 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge.
L
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF x 0.06 ns/pF = 1.2 ns
less
than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
Rise and fall times of 4 ns or less
Timing reference levels for delays = VIH, V
IL
Test conditions for outputs (unless noted otherwise):
C
= 50 pF; except for CKO, where C
LOAD
Timing reference levels for delays = VIH, V
3-state delays measured to the high-impedance state of the output driver
LOAD
IL
= 20 pF
For the timing diagrams, see Table 62 for input clock requirements. Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
Lucent Technologies Inc. 75
Page 76
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation

10.1 DSP Clock Generation

t1
t3
1X CKI*
t5
CKO
CKO
* See Table 62 for input clock electrical requirements. † Free-running clock. ‡ Wait-stated clock (see Table 38).
§
W = number of wait-states.
t2
t4
EXTERNAL MEMORY CYCLE
W = 1
§
(continued)
t6, t6a
5-4009 (F).a
Figure 11. I/O Clock Timing Diagram
Table 66. Timing Requirements for Input Clock
Abbreviated Reference Parameter
14 ns and 11 ns
Min Max Unit
t1 Clock In Period (high to high) 20
t2 Clock In Low Time (low to high) 10 ns t3 Clock In High Time (high to low) 10 ns
* Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL. † Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
Table 67. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference Parameter 14 ns 11 ns Unit
Min Max Min Max
t4 Clock Out High Delay 10 8 ns t5 Clock Out Low Delay (high to low) 10 8 ns t6 Clock Out Period (low to low) T* T* ns
t6a Clock Out Period with SLOWCKI Bit
0.74 1.6 0.74 1.6
Set in powerc Register (low to low)
* T = internal clock period, set by CKI or by CKI and the PLL parameters.
*
ns
µ
s
76 Lucent Technologies Inc.
Page 77
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
(continued)

10.2 Reset Circuit

The DSP1627 has a powerup reset circuit that automatically clears the JTAG controller upon powerup. If the supply voltage falls below V being used—by applying six low-to-high clock edges on TCK with TMS held high, followed by the usual RSTB and CKI reset sequence. Figure 12 shows two separate events: an initial powerup and a powerup following a drop in the power supply voltage.
* See Table 60, Recommended Operating Condiitons.
DD
V
RAMP
CKI
TCK
IH
V
TMS
MIN* and a reset is required, the JTAG controller must be reset—even if the JTAG port isn’t
DD
DD
MIN
0.4 V
V
t9
t146
t8
DD
MIN
V
0.4 V t9
t151
t152
t8
t153 t153
IH
V
RSTB
IL
V
t10
OH
V
PINS
OL
V
Notes: See Table 62 for CKI electrical requirements and Table 71 for TCK timing requirements.
When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, DSEL, and RWN outputs remain high, and CKO remains a free-running clock.
TMS and TDI signals have internal pull-up devices.
t11
t10
t11
5-2253 (F).a
Figure 12. Powerup Reset and Chip Reset Timing Diagram
Table 68. Timing Requirements for Powerup Reset and Chip Reset
Abbreviated Reference Parameter Min Max Unit
t8 Reset Pulse (low to high) 6T ns
DD
t9 V
t146 V
t151 TMS Hig h t152 JTAG Reset to CMOS
Ramp 10 ms
DD
MIN to RSTB Low CMOS
Crystal* Small-signal
RSTB Low Crystal*
Small-Signal
20 ms – 6 * T
0 if 6 * T
20 µs – 6 * T
0 if 6 * T
6 * T
TCK
TCK
TCK
2T 20 20
TCK†
2T if 6 * T
≥ 20 ms
if 6 * T
TCK
≥ 20 µs
TCK
< 20 ms
TCK
< 20 µs
— — —
—ns —
— — — —
ms
t153 RSTB Rise (low to high) 95 ns
* With external components as specified in Table 62.
TCK
†T
= t12 = TCK period. See Table 71 for TCK timing requirements.
ns
µ
ns
s
Lucent Technologies Inc. 77
Page 78
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
(continued)
Table 69. Timing Characteristics for Powerup Reset and Chip Reset
Abbreviated Reference Parameter Min Max Unit
t10 RSTB Disable Time (low to 3-state) 100 ns t11 RSTB Enable Time (high to valid) 100 ns
Note:
The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high cur­rents may flow.

10.3 Reset Synchronization

t5 + 2 x t6
IH
V
*
CKI
RSTB
CKO
IL
V
t126
IH
V
IL
V
IH
V
IL
V
CKO
* See Table 62 for input clock electrical requirements. Note: CKO
1
and CKO2 are two possible CKO states before reset. CKO is free-running.
IL
V
IH
V
Figure 13. Reset Synchronization Timing
Table 70. Timing Requirements for Reset Synchronization Timing
Abbreviated Reference Parameter Min Max Unit
t126 Reset Setup (high to high) 1.5 T/2 – 5 ns
5-4011 (F).a
78 Lucent Technologies Inc.
Page 79
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation

10.4 JTAG I/O Specifications

t12
t156
t20
TCK
TMS
TDI
TDO
t155
IH
V
IL
V
t15
IH
V
IL
V
t17
IH
V
IL
V
OH
V
OL
V
t16
t18
Figure 14. JTAG Timing Diagram
(continued)
t14t13
t19
5-4017 (F)
Table 71. Timing Requirements for JTAG Input/Output
Abbreviated Refe rence Parameter Min Max Unit
t12 TCK Period (high to high) 50 ns t13 TCK High Time (high to low) 22.5 ns t14 TCK Low Time (low to high) 22.5 ns t15 TMS Setup Time (valid to high) 7.5 ns t16 TMS Hold Time (high to invalid) 2 ns t17 TDI Setup Time (valid to high) 7.5 ns t18 TDI Hold Time (high to invalid) 2 ns
Table 72. Timing Characteristics for JTAG Input/Output
Abbreviated Reference Parameter Min Max Unit
t19 TDO Delay (low to valid) 19 ns t20 TDO Hold (low to invalid) 0 ns
Lucent Technologies Inc. 79
Page 80
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation

10.5 Interrupt

V
OH
*
CKO
V
OL
t21
V
INT[1:0]
IACK
VEC[3:0]
* CKO is free-running. † IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion.
IH
V
IL
t22
t23
V
OH
V
OL
V
OH
V
OL
t24
(continued)
t25
t26
5-4018 (F)
Figure 15. Interrupt Timing Diagram
Table 73. Timing Requirements for Interrupt
Abbreviated Reference Parameter Min Max Unit
t21 Interrupt Setup (high to low) 15 ns t22 INT Assertion Time (high to low) 2T ns
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Table 74. Timing Characteristics for Interrupt
Abbreviated Reference Parameter Min Max Unit
t23 IACK Assertion Time (low to high) T/2 + 7.5 ns t24 VEC Assertion Time (low to high) 9.5 ns t25 IACK Invalid Time (low to low) 7.5 ns t26 VEC Invalid Time (low to low) 9.5 ns
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
80 Lucent Technologies Inc.
Page 81
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
(continued)

10.6 Bit Input/Output (BIO)

t144
O H
V
CKO
IOBIT
(OUTPUT)
IOBIT
(INPUT)
Table 75. Timing Requirements for BIO Input Read
Abbreviated Reference Parameter Min Max Unit
O L
V
t29
O H
V
O L
V
t27
I H
V
I L
V
DATA INPUT
t28
VALID OUTPUT
Figure 16. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit)
t27 IOBIT Input Setup Time (valid to high) 12 ns t28 IOBIT Input Hold Time (high to invalid) 0 ns
5-4019 (F).a
Table 76. Timing Characteristics for BIO Output
Abbreviated Refe rence Parameter Min Max Unit
t29 IOBIT Output Valid Time (low to valid) 7.5 ns
t144 IOBIT Output Hold Time (low to invalid) 1 ns
t144
OH –
V
CKO
O L–
V
t29
IOBIT
(OUTPUT)
IOBIT
(INPUT)
V V
OH –
O L–
V V
IH –
I L–
t141
TEST INPUT
VALID OUTPUT
t142
Figure 17. Write Outputs and Test Inputs (cbit = Immediate)
Table 77. Timing Requirements for BIO Input Test
Abbreviated Reference Parameter Min Max Unit
t141 IOBIT Input Setup Time (valid to low) 12 ns t142 IOBIT Input Hold Time (low to invalid) 0 ns
5-4019 (F).b
Lucent Technologies Inc. 81
Page 82
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
(continued)

10.7 External Memory Interface

The following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. See the detailed description of the external memory interface including other functional diagrams.
CKO
ENABLE
* W = number of wait-states.
OL
V
OH
V
OL
V
OH
V
Table 78. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO)
Abbreviated Reference Parameter Min Max Unit
t33 CKO to ENABLE Active (low to low) 0 7 ns t34 CKO to ENABLE Inactive (low to high) –1 6 ns
DSP1611/17/18/27 Digital Signal Processor Information Manual
t34t33
*
= 0
W
Figure 18. Enable Transition Timing
for a
5-4020 (F).b
Table 79. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)
Abbreviated Reference Parameter Min Max Unit
t33 CKO to Delayed ENABLE Active (low to low) T/2 – 2 T/2 + 7 ns
82 Lucent Technologies Inc.
Page 83
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
(MWAIT = 0 x 2222)
W* = 2
OH
V
CKO
OL
V
t127
OH
DB
AB
V
OL
V
t129
IH
V
IL
V
t128
OH
V
OL
V
t150
Figure 19. External Memory Data Read Timing Diagram
ENABLE
* W = number of wait-states.
(continued)
t130
READ DATA
READ ADDRESS
5-4021 (F).a
Table 80. Timing Characteristics for External Memory Access
Abbreviated Reference Parameter Min Max Unit
t127 Enable Width (low to high) T(1 + W) – 4 ns t128 Address Valid (enable low to valid) 2 ns
Table 81. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)
Abbreviated
Reference
Parameter 14 ns 11 ns Unit
Min Max Min Max
t129 Read Data Se tup (valid to enable high) 12 11 ns t130 Read Data Hold (enable high to hold) 0 0 ns t150 External Memory Access Time (valid to valid) T(1 + W) – 13 T(1 + W) – 12 ns
Lucent Technologies Inc. 83
Page 84
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
(MWAIT = 0x1002)
W* = 2
OH
V
CKO
ERAMLO
EROM
RWN
DB
AB
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
t133
OH
V
OL
V
t136
OH
V
OL
V
t135
WRITE ADDRESS READ ADDRESS
WRITE DATA READ
t134
(continued)
W* = 1
t131
t132
5-4022 (F).a
* W = number of wait-states.
Figure 20. External Memory Data Write Timing Diagram
Table 82. Timing Characteristics for External Memory Data Write (All Enables)
Abbreviated
Reference
Parameter 14 ns 11 ns Unit
Min Max Min Max
t131 Write Overlap (enable low to 3-state) 0 0 ns t132 RWN Advance (RWN high to enable high) 0 0 ns t133 RWN Delay (enable low to RWN low) 0—0—ns t134 Write Data Setup (data valid to RWN high) T(1 + W)/2 – 3 T(1 + W)/2 – 2 ns t135 RWN Width (low to high) T(1 + W) – 5.5 T(1 + W) – 5.5 ns t136 Write Address Setup (address valid to RWN
0—0—ns
low)
84 Lucent Technologies Inc.
Page 85
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
(MWAIT = 0x1002)
W* = 2
OH
V
CKO
OL
V
OH
ERAMLO
EROM
V
OL
V
OH
V
OL
V
OH
V
DB WRITE READ
OL
V
t138
RWN
AB
OH
V
OL
V
OH
V
OL
V
WRITE ADDRESS READ ADDRESS
(continued)
W* = 1
t131
t137
t139
5-4023 (F).a
* W = number of wait-states.
Figure 21. Write Cycle Followed by Read Cycle
Table 83. Timing Characteristics for Write Cycle Followed by Read Cycle
Abbreviated Reference Parameter Mi n Ma x Unit
t131 Write Overlap (enable low to 3-state) 0 ns t137 Write Data 3-state (RWN high to 3-state) 2 ns t138 Write Data Hold (RWN high to data hold) 0 ns t139 Write Address Hold (RWN high to address hold) 0 ns
Lucent Technologies Inc. 85
Page 86
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
(continued)

10.8 PHIF Specifications

For the PHIF, "READ" means read by the external user (output by the DSP); "WRITE" is similarly defined. The 8-bit reads/ writes are identical to one-half of a 16-bit access.
PCSN
PODS
PIDS
PBSEL
PSTAT
PB[7:0]
16-bit READ
V
IH
V
IL
V
IH
V
IL
t41
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t45
t49
t42
t46
t50
t154
t43
t47
t51
16-bit WRITE
t44
t48
t52
5-4036 (F)
Figure 22. PHIF
Table 84. Timing Requirements for PHIF
Mode Signaling (Read and Write) Timing Diagram
Intel
Mode Signaling
Intel
Abbreviated Reference Param ete r Min Max Unit
t41 PODS to PCSN Setup (low to low) 0 ns t42 PCSN to PODS Hold (high to high) 0 ns t43 PIDS to PCSN Setup (low to low) 0 ns
t44 PCSN to PIDS Hold (high to high) 0 ns t45* PSTAT to PCSN Setup (valid to low) 4.5 ns t46* PCSN to PSTAT Hold (high to invalid) 0 ns t47* PBSEL to PCSN Setup (valid to low) 4.5 ns t48* PCSN to PBSEL Hold (high to invalid) 0 ns t51* PB Write to PCSN Setup (valid to high) 7.5 ns t52* PCSN to PB Write Hold (high to invalid) 4 ns
* This timing diagram for t he PH IF p ort s hows acc ess es usin g t he P CSN sign al t o in iti ate an d compl ete a t ran sactio n. The t rans ac tions can also be initiat ed
and completed with th e PIDS and PO DS signals. An output tran saction (read) is initiate d by PCSN or PODS going low, whic hever comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated by PCSN or PIDS going low, whichever comes last. An input tr ansact ion is co mpleted by PCS N or P IDS goin g hi gh, whic heve r comes f irst . All r equi remen ts re fe renced to PCSN app ly to PI DS or PODS, if PIDS or PODS is the controlling signal.
Table 85. Timing Characteristics for PHIF
Mode Signaling
Intel
Abbreviated Reference Param ete r Min Max Unit
t49* PCSN to PB Read (low to valid) 13 ns t50* PCSN to PB Read Hold (high to invalid) 3 ns
* This timing diagram for t he PH IF p ort s hows acc ess es usin g t he P CSN sign al t o in iti ate an d compl ete a t ran sactio n. The t rans ac tions can also be initiat ed
and completed with th e PIDS and PO DS signals. An output tran saction (read) is initiate d by PCSN or PODS going low, whic hever comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated by PCSN or PIDS going low, whichever comes last. An input tr ansact ion is co mpleted by PCS N or P IDS goin g hi gh, whic heve r comes f irst . All r equi remen ts re fe renced to PCSN app ly to PI DS or PODS, if PIDS or PODS is the controlling signal.
86 Lucent Technologies Inc.
Page 87
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
PCSN
PODS
PIDS
PBSEL
POBE
PIBF
16-bit READ
V
IH
V
IL
t55
V
IH
V
IL
t56
V
IH
V
IL
V
OH
V
OL
t53
V
OH
V
OL
OH
V
OL
V
16-bit WRITE
t55
t56
t55
t56
t54
(continued)
8-bit READ
t53
t56
8-bit WRITE
t55
t56
t54
5-4037 (F).a
Figure 23. PHIF
Table 86. Timing Requirements for PHIF
Mode Signaling (Pulse Period and Flags) Timing Diagram
Intel
Mode Signaling
Intel
Abbreviated Reference Parameter Min Max Unit
t55 PCSN/PODS/PIDS Pulse Width (high to low) 15 ns t56 PCSN/PODS/PIDS Pulse Width (low to high) 15 ns
Table 87. Timing Characteristics for PHIF
Mode Signaling
Intel
Abbreviated Reference Parameter Min Max Unit
t53* t54*
* t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first. t54 should be referenced to the rising edge of PCSN
or PIDS, whichever comes first.
† POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and t54 apply
to the inverted levels as well as those shown.
PCSN/PODS to POBE PCSN/PIDS to PIBF
(high to high)
(high to high)
—15ns —15ns
Lucent Technologies Inc. 87
Page 88
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
16-bit READ 16-bit WRITE
IH
V
PCSN
PRWN
PBSEL
PSTAT
PB[7:0]
PDS
IL
V
IH
V
V
IL
IH
V
IL
V
IH
V
IL
V
V
IH
V
IL
Figure 24. PHIF
t41
t43
t45
t49
Motorola
t42
t44
t46
t50
t154
Mode Signaling (Read and Write) Timing Diagram
(continued)
t43 t44
t47
t51
t48
t52
5-4038 (F).a
Table 88. Timing Requirements for PHIF
Motorola
Mode Signaling
Abbreviated Reference Parameter Min Max Unit
t41
t42
to PCSN Setup (valid to low)
PDS PCSN to PDS† Hold (high to invalid)
0—ns 0—ns
t43 PRWN to PCSN Setup (valid to low) 4.5 ns
t44 PCSN to PRWN Hold (high to invalid) 0 ns t45* PSTAT to PCSN Setup (valid to low) 4.5 ns t46* PCSN to PSTAT Hold (high to invalid) 0 ns t47* PBSEL to PCSN Setup (valid to low) 4.5 ns t48* PCSN to PBSEL Hold (high to invalid) 0 ns t51* PB Write to PCSN Setup (valid to high) 8 ns t52* PCSN to PB Write Hold (high to invalid) 4 ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The tr ansac tions can also
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes las t. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 89. Timing Characteristics for PHIF
Motorola
Mode Signaling
Abbreviated Reference Parameter Min Max Unit
t49* PCSN to PB Read (low to valid) 13 ns t50* PCSN to PB Read (high to invalid) 3 ns
* This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The tr ansac tions can also
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes las t. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
88 Lucent Technologies Inc.
Page 89
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
16-bit WRITE
t55
t56
t55
t56
t54
PCSN
PDS
PRWN
PBSEL
POBE
PIBF
V
VIL–
V
V
V
V
V
V
V
V
V
V
OH
OH
OH
16-bit READ
IH
t55
IH
IL
t56
IH
IL
– –
OL
t53
– –
OL
– –
OL
(continued)
8-bit READ
t53
t56
8-bit WRITE
t55
t56
t54
5-4039 (F).a
Figure 25. PHIF
Motorola
Table 90. Timing Characteristics for PHIF
Mode Signaling (Pulse Period and Flags) Timing Diagram
Motorola
Mode Signaling
Abbreviated Reference Parameter Min Max Unit
t53* t54*
* An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced to
PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
† PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
PCSN/PDS PCSN/PDS
Table 91. Timing Requirements for PHIF
to POBE† (high to high)
to PIBF† (high to high)
Motorola
Mode Signaling
—15ns —15ns
Abbreviated Reference Parameter Min Max Unit
t55 PCSN/PDS/PRWN Pulse Width (high to low) 15 ns t56 PCSN/PDS/PRWN Pulse Width (low to high) 15 ns
Lucent Technologies Inc. 89
Page 90
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
V
PCSN
PODS (PDS*)
PIDS (PRWN*)
PBSEL
PSTAT
PB[7:0]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t47
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t45
t49
(continued)
t50
t48
t46
t154
5-4040 (F).a
*
Motorola
Table 92. Timing Requirements for
mode signal name.
Figure 26. PHIF
Intel
or
Motorola
Mode Signaling (Status Register Read) Timing Diagram
Intel
and
Motorola
Mode Signaling (Status Register Read)
Abbreviated Reference Parameter Min Max Unit
t45
t46
t47
t48
† t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.
Table 93. Timing Characteristics for
PSTAT to PCSN Setup (valid to low) PCSN to PSTAT Hold (high to invalid) PBSEL to PCSN Setup (valid to low) PCSN to PBSEL Hold (high to invalid)
Intel
and
Motorola
Mode Signaling (Status Register Read)
4.5 ns 0—ns
4.5 ns 0—ns
Abbreviated Reference Parameter Min Max Unit
t49
t50
† t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.
PCSN to PB Read (low to valid) PCSN to PB Read Hold (high to invalid)
—13 ns
3—ns
90 Lucent Technologies Inc.
Page 91
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
IH
V
V
V
V
V
VIL–
OH
OL
OH
OL
t57
– –
– –
RSTB
POBE
PIBF
(continued)
t58
5-4775 (F)
Figure 27. PHIF, PIBF, and POBE Reset Timing Diagram
Table 94. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset
Abbreviated Reference Parameter Min Max
Unit
t57 RSTB Disable to POBE/PIBF* (high to valid) 19 ns t58 RSTB Enable to POBE/PIBF* (low to invalid) 3 19 ns
* After reset, POBE and PIBF always go to the levels shown, indicating output buffer empty and input buffer empty. The DSP progr am, however,
may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply.
IH
V
CKO
POBE
PIBF
† POBE and PIBF can be programmed to be active-high or active-low. They are shown active-high. The timing characteristic for active-low is
the same as for active-high
IL
V
t59
VOH–
OL
V
VOH–
OL
V
.
t59
5-4776 (F)
Figure 28. PHIF, PIBF, and POBE Disable Timing Diagram
Table 95. PHIF Timing Characteristics for POBE and PIBF Disable
Abbreviated Reference Parameter Min Max Unit
t59 CKO to POBE/PIBF Disable (high/low to disable) 15 ns
Lucent Technologies Inc. 91
Page 92
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation

10.9 Serial I/O Specifications

t70
V
ICK
V
ILD
V
DI
V
IBF
V
* N = 16 or 8 bits.
V
V
V
OH
OL
IH
IL
IH
IL
IH
IL
– –
t72 t71
t74t75
t73
t75
t77 t78
B0 B1
Figure 29. SIO Passive Mode Input Timing Diagram
(continued)
BN – 1* B0
t79
5-4777 (F)
Table 96. Timing Requirements for Serial Inputs
Abbreviated Reference Parameter Min Max Unit
t70
Clock Period (high to high)
40
—† t71 Clock Low Time (low to high) 18 ns t72 Clock High Time (high to low) 18 ns t73 Load High Setup (high to high) 6 ns t74 Load Low Setup (low to high) 6 ns t75 Load High Hold (high to invalid) 0 ns t77 Data Setup (valid to high) 5 ns t78 Data Hold (high to invalid) 0 ns
† Device is fully static; t70 is tested at 200 ns. ‡ For Multiprocessor mode, see note in Section 10.10.
Table 97. Timing Characteristics for Serial Outputs
Abbreviated Reference Parameter Min Max Unit
t79 IBF Delay (high to high) 22 ns
ns
92 Lucent Technologies Inc.
Page 93
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
OH
V
ICK
ILD
DI
IBF
* ILD goes high during bit 6 (of 0:15), N = 8 or 16.
Table 98. Timing Requirements for Serial Inputs
OL
V
t101
t76a
OH
V
OL
V
t77 t78
IH
V
IL
V
OH
V
OL
V
B0 B1
Figure 30. SIO Active Mode Input Timing Diagram
(continued)
*
BN – 1 B0
t79
5-4778 (F)
Abbreviated Reference Parameter Min Max Unit
t77 Data Setup (valid to high) 5 ns t78 Data Hold (high to invalid) 0 ns
Table 99. Timing Characteristics for Serial Outputs
Abbreviated Reference Parameter Min Max Unit
t76a ILD Delay (high to low) 22 ns t101 ILD Hold (high to invalid) 4 ns
t79 IBF Delay (high to high) 22 ns
Lucent Technologies Inc. 93
Page 94
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
t80
t81t82
IH
V
OCK
OLD
DO*
SADD
DOEN
OBE
IL
V
t85
t83
IH
V
IL
V
t88
OH
V
OL
V
t94
OH
V
OL
V
IH
V
IL
V
OH
V
OL
V
t84
t85
B0 B1 B7 BN – 1
AD0
(continued)
AD1
t96
AD7
t90t90t87
t93t93t92
AS7
t89
t95
5-4796 (F)
* See sioc register, MSB field to determine if B0 is the MSB or LSB. See sioc register, ILEN field to determine if the DO word length is 8 bits or
16 bits.
Figure 31. SIO Passive Mode Output Timing Diagram
Table 100. Timing Requirements for Serial Inputs
Abbreviated Reference P ara met er Min Max Unit
t80
Clock Period (high to high)
40
—†
ns t81 Clock Low Time (low to high) 18 ns t82 Clock High Time (high to low) 18 ns t83 Load High Setup (high to high) 6 ns t84 Load Low Setup (low to high) 6 ns t85 Load Hold (high to invalid) 0 ns
† Device is fully static; t80 is tested at 200 ns. ‡ For multiprocessor mode, see note in Section 10.10.
Table 101. Timing Characteristics for Serial Outputs
Abbreviated Reference Parameter Min Max Unit
t87 Data Delay (high to valid) 22 ns t88 Enable Data Delay (low to active) 22 ns t89 Disable Data Delay (high to 3-state) 22 ns t90 Data Hold (high to invalid) 4 ns t92 Address Delay (high to valid) 22 ns t93 Address Hold (high to invalid) 4 ns t94 Enable Delay (low to active) 22 ns t95 Disable Delay (high to 3-state) 22 ns t96 OBE Delay (high to high) 22 ns
94 Lucent Technologies Inc.
Page 95
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation
OH
V
OCK
OLD
SADD
DOEN
OBE
* OLD goes high at the end of bit 6 of 0:15.
DO
OL
V
t102 t86a
OH
V
OL
V
t88
OH
V
OL
V
t94
OH
V
OL
V
IH
V
IL
V
OH
V
OL
V
B0 B1 B7 BN – 1
AD0
(continued)
AD1
t96
*
t90t90t87
t89
t95
5-4797 (F)
AD7
t93t93t92
AS7
Figure 32. SIO Active Mode Output Timing Diagram
Table 102. Timing Characteristics for Serial Outputs
Abbreviated Reference Parameter Min Max Unit
t86a OLD Delay (high to low) 22 ns t102 OLD Hold (high to invalid) 4 ns
t87 Data Delay (high to valid) 22 ns t88 Enable Data Delay (low to active) 22 ns t89 Disable Data Delay (high to 3-state) 22 ns t90 Data Hold (high to invalid) 4 ns t92 Address Delay (high to valid) 22 ns t93 Address Hold (high to invalid) 4 ns t94 Enable Delay (low to active) 22 ns t95 Disable Delay (high to 3-state) 22 ns t96 OBE Delay (high to high) 22 ns
Lucent Technologies Inc. 95
Page 96
Data Sheet
DSP1627 Digital Signal Processor March 2000
10 Timing Characteristics for 5 V Operation
OH
V
CKO
ICK
OCK
ICK/OCK*
ILD
OLD
SYNC
OL
V
t97
OH
V
OL
V
t99
OH
V
OL
V
OH
V
t76a
t101
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
t86a
t102
t103
t105
t98
t100
(continued)
t76b
t101
t86b
t102
t104
t105
5-4798 (F)
* See sioc register, LD field.
Figure 33. Serial I/O Active Mode Clock Timing
Table 103. Timing Characteristics for Signal Generation
Abbreviated Reference Parameter Min Max Unit
t97 ICK Delay (high to high) 15 ns t98 ICK Delay (high to low) 15 ns
t99 OCK Delay (high to high) 15 ns t100 OCK Delay (high to low) 15 ns t76a ILD Delay (high to low) 22 ns t76b ILD Delay (high to high) 22 ns t101 ILD Hold (high to invalid) 4 ns t86a OLD Delay (high to low) 22 ns t86b OLD Delay (high to high) 22 ns t102 OLD Hold (high to invalid) 4 ns t103 SYNC Delay (high to low) 22 ns t104 SYNC Delay (high to high) 22 ns t105 SYNC Hold (high to invalid) 4 ns
96 Lucent Technologies Inc.
Page 97
Data Sheet March 2000 DSP1627 Digital Signal Processor
10 Timing Characteristics for 5 V Operation

10.10 Multiprocessor Communication

OCK/ICK
t113 t112
SYNC
DO/D1
SADD
DOEN
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
t112
*
t113
t116
t121
t120
(continued)
TIME SLOT 1 TIME SLOT 2
t117
B0B15B8B7B1B0B15
t114
t122
AD0AS7AS0AD7AD1AD0
t120
t115
5-4799 (F)
* Negative edge initiates time slot 0.
Figure 34. SIO Multiprocessor Timing Diagram
Note:
All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.
Table 104. Timing Requirements for SIO Multiprocessor Communication
Abbreviated Reference Parameter Min Max Unit
t112 Sync Setup (high/low to high) 22 ns t113 Sync Hold (high to high/low) 0 ns t114 Address Setup (valid to high) 9 ns t115 Address Hold (high to invalid) 0 ns
Table 105. Timing Characteristics for SIO Multiprocessor Communication
Abbreviated Reference* Parameter Min Max Unit
t116 Data Delay (bit 0 only) (low to valid) 22 ns t117 Data Disable Delay (high to 3-state) 20 ns t120 DOEN Valid Delay (high to valid) 16 ns t121 Address Delay (bit 0 only) (low to valid) 22 ns t122 Address Disable Delay (high to 3-state) 20 ns
* With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.
Lucent Technologies Inc. 97
Page 98
Data Sheet
DSP1627 Digital Signal Processor March 2000

11 Timing Characteristics for 3.0 V Operation

The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
T
= –40 °C to +85 °C (See Section 8.3.)
A
V
= 3.0 V to 3.6 V, VSS = 0 V (See Section 8.3.)
DD
Capacitance load on outputs ( C Output characteristics can be derated as a function of load capacitance (C All outputs: 0.03 ns/pF ≤ dt/dC
) = 50 pF, except for CKO, where CL = 20 pF.
L
).
L
≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge.
L
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF x 0.06 ns/pF = 1.2 ns
less
than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
Rise and fall times of 4 ns or less
Timing reference levels for delays = VIH, V
IL
Test conditions for outputs (unless noted otherwise):
C
= 50 pF; except for CKO, where C
LOAD
Timing reference levels for delays = VIH, V
3-state delays measured to the high-impedance state of the output driver
LOAD
IL
= 20 pF
For the timing diagrams, see Table 62 for input clock requirements. Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
98 Lucent Technologies Inc.
Page 99
Data Sheet March 2000 DSP1627 Digital Signal Processor
11 Timing Characteristics for 3.0 V Operation

11.1 DSP Clock Generation

t1
t3
1X CKI*
t5
CKO
CKO
* See Table 62 for input clock electrical requirements. † Free-running clock. ‡ Wait-stated clock (see Table 38).
§ W = number of wait-states.
t2
t4
EXTERNAL MEMORY CYCLE
W = 1
§
(continued)
t6, t6a
5-4009 (F).a
Figure 35. I/O Clock Timing Diagram
Table 106. Timing Requirements for Input Clock
Abbreviated Reference Parameter 10 ns
*
Min Max Unit
t1 Clock In Period (high to high) 20
t2 Clock In Low Time (low to high) 10 ns t3 Clock In High Time (high to low) 10 ns
* Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL. † Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
Table 107. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference Parameter 10 ns Unit
Min Max
t4 Clock Out High Delay 10 ns t5 Clock Out Low Delay (high to low) 10 ns t6 Clock Out Period (low to low) T* ns
t6a Clock Out Period with SLOWCKI Bit Set
0.74 3.8
in powerc Register (low to low)
* T = internal clock period, set by CKI or by CKI and the PLL parameters.
ns
µ
s
Lucent Technologies Inc. 99
Page 100
Data Sheet
DSP1627 Digital Signal Processor March 2000
11 Timing Characteristics for 3.0 V Operation
(continued)

11.2 Reset Circuit

The DSP1627 has a powerup reset circuit that automatically clears the JTAG controller upon powerup. If the supply voltage falls below V being used—by applying six low-to-high clock edges on TCK with TMS held high, followed by the usual RSTB and CKI reset sequence. Figure 60 shows two separate events: an initial powerup and a powerup following a drop in the power supply voltage.
* See Table 60, Recommended Operating Condiitons.
DD
V
RAMP
CKI
TCK
IH
V
TMS
MIN* and a reset is required, the JTAG controller must be reset—even if the JTAG port isn’t
DD
DD
MIN
0.4 V
V
t9
t146
t8
DD
MIN
V
0.4 V t9
t151
t152
t8
t153 t153
IH
V
RSTB
IL
V
t10
OH
V
PINS
OL
V
Notes: See Table 62 for CKI electrical requirements and Table 151 for TCK timing requirements. When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state
condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, DSEL, and RWN outputs remain high, and CKO remains a free-running clock.
TMS and TDI signals have internal pull-up devices.
t11
t10
t11
5-2253 (F).a
Figure 36. Powerup Reset and Chip Reset Timing Diagram
Table 108. Timing Requirements for Powerup Reset and Chip Reset
Abbreviated Reference Parameter Min Max Unit
t8 Reset Pulse (low to high) 6T ns t9 V
t146 V
t151 TMS High t152 JTAG Reset to CMOS
DD
Ramp 10 ms
DD
MIN to RSTB Low CMOS
Crystal* Small-Signal
RSTB Low Crystal*
Small-Signal
20 ms – 6 * T
0 if 6 * T
20 µs – 6 * T
0 if 6 * T
6 * T
TCK
TCK
TCK
2T
20 20
TCK†
2T
if 6 * T
≥ 20 ms
if 6 * T
TCK
≥ 20 µs
TCK
< 20 ms
TCK
< 20 µs
— — —
—ns —
— — — —
ns
ms
µ
ns
s
t153 RSTB (low to high) 54 ns
* With external components as specified in Table 62.
TCK
= t12 = TCK period. See Table 151 for TCK timing requirements.
†T
100 Lucent Technologies Inc.
Loading...