Datasheet DS90LV047ATMX, DS90LV047ATMTCX, DS90LV047ATMTC, DS90LV047ATM Datasheet (NSC)

Page 1

DS90LV047A 3V LVDS Quad CMOS Differential Line Driver

General Description

The DS90LV047Ais a quad CMOS flow-through differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV047A accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition, the driver supports a TRI-STATE

function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The DS90LV047Ahasaflow-through pinout for easy PCB layout.

The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV047A and companion line receiver (DS90LV048A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.

Features

400 Mbps (200 MHz) switching rates

n Flow-through pinout simplifies PCB layout n 300 ps typical differential skew n 400 ps maximum differential skew n 1.7 ns maximum propagation delay n 3.3V power supply design

350 mV differential signaling

n Low power dissipation (13mW at 3.3V static) n Interoperable with existing 5V LVDS receivers n High impedance on LVDS outputs on power down n Conforms to TIA/EIA-644 LVDS Standard n Industrial operating temperature range (−40˚C to +85˚C) n Available in surface mount (SOIC) and low profile

TSSOP package

Connection Diagram Functional Diagram

Truth Table

ENABLES INPUT OUTPUTS

EN EN

OUT+

OUT−

H L or Open L L H

HHL

All other combinations of ENABLE inputs X Z Z

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Dual-In-Line

DS100887-1

Order Number DS90LV047ATM, DS90LV047ATMTC

See NS Package Number M16A, MTC16

DS100887-2

July 1999

DS90LV047A 3V LVDS Quad CMOS Differential Line Driver

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

) −0.3V to +4V

Input Voltage (D

) −0.3V to (VCC+ 0.3V)

Enable Input Voltage (EN, EN

) −0.3V to (VCC+ 0.3V)

Output Voltage (D

OUT+,DOUT−

) −0.3V to +3.9V

Short Circuit Duration

OUT+,DOUT−

) Continuous

Maximum Package Power Dissipation

+25˚C M Package 1088 mW MTC Package 866 mW Derate M Package 8.5 mW/˚C above +25˚C Derate MTC Package 6.9 mW/˚C above +25˚C

Storage Temperature Range −65˚C to +150˚C Lead Temperature Range

Soldering (4 sec.) +260˚C Maximum Junction Temperature +150˚C ESD Rating (Note 10)

(HBM, 1.5 kΩ, 100 pF) ≥ 10 kV

(EIAJ, 0 Ω, 200 pF) ≥ 1200 V

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (V

) +3.0 +3.3 +3.6 V Operating Free Air Temperature (T

) −40 +25 +85 ˚C

Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3, 4)

Symbol Parameter Conditions Pin Min Typ Max Units

OD1

Differential Output Voltage R

100Ω (

Figure 1

OUT−

OUT+

250 310 450 mV

∆V

OD1

Change in Magnitude of V

OD1

for Complementary Output States

1 35 |mV|

Offset Voltage 1.125 1.17 1.375 V

∆V

Change in Magnitude of VOSfor Complementary Output States

1 25 |mV|

Output High Voltage 1.33 1.6 V

Output Low Voltage 0.90 1.02 V

Input High Voltage DIN,

EN, EN*

2.0 V

Input Low Voltage GND 0.8 V

Input High Current V

or 2.5V −10 2 +10 µA

Input Low Current V

GND or 0.4V −10 −2 +10 µA

Input Clamp Voltage I

−18 mA −1.5 −0.8 V

Output Short Circuit Current (Note 11)

ENABLED, D

IN=VCC,DOUT+

=0Vor

= GND, D

OUT−

=0V

OUT−

OUT+

−4.2 −9.0 mA

OSD

Differential Output Short Circuit Current (Note 11)

ENABLED, VOD= 0V −4.2 −9.0 mA

OFF

Power-off Leakage V

OUT

0V or 3.6V, V

or Open

−20

1 +20 µA

Output TRI-STATE Current EN = 0.8V and EN* = 2.0V

OUT

0V or V

−10

1 +10 µA

No Load Supply current Drivers Enabled

DIN=VCCor GND V

4.0 8.0 mA

CCL

Loaded Supply Current Drivers Enabled

RL= 100Ω All Channels, DIN= V

or GND (all inputs)

20 30 mA

CCZ

No Load Supply Current Drivers Disabled

DIN=VCCor GND, EN = GND, EN* = V

2.2 6.0 mA

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Switching Characteristics

+3.3V

10%,T

−40˚C to +85˚C (Notes 3, 9, 12)

Symbol Parameter Conditions Min Typ Max Units

PHLD

Differential Propagation Delay High to Low R

100Ω,C

15 pF

(

Figure 2

and

Figure 3

)

0.5 0.9 1.7 ns

PLHD

Differential Propagation Delay Low to High 0.5 1.2 1.7 ns

SKD1

Differential Pulse Skew |t

PHLD−tPLHD

(Note 5)

0 0.3 0.4 ns

SKD2

Channel-to-Channel Skew (Note 6) 0 0.4 0.5 ns

SKD3

Differential Part to Part Skew (Note 7) 0 1.0 ns

SKD4

Differential Part to Part Skew (Note 8) 0 1.2 ns

TLH

Rise Time 0.5 1.5 ns

THL

Fall Time 0.5 1.5 ns

PHZ

Disable Time High to Z R

100Ω,C

15 pF

(

Figure 4

and

Figure 5

)

25ns

PLZ

Disable Time Low to Z 2 5 ns

PZH

Enable Time Z to High 3 7 ns

PZL

Enable Time Z to Low 3 7 ns

MAX

Maximum Operating Frequency (Note 14) 200 250 MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V

OD1

and

∆V

OD1

Note 3: All typicals are given for: V

+3.3V, T

+25˚C.

Note 4: The DS90LV047Aisa current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90Ω to 110Ω).

Note 5: t

SKD1|tPHLD−tPLHD

| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the

same channel. Note 6: t

SKD2

is the Differential Channel-to-Channel Skew of any event on the same device.

Note 7: t

SKD3

, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This speci-

fication applies to devices at the same V

and within 5˚C of each other within the operating temperature range.

Note 8: t

SKD4

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended

operating temperature and voltage ranges, and across process distribution. t

SKD4

is defined as |Max − Min| differential propagation delay.

Note 9: Generator waveform for all tests unless otherwise specified: f=1 MHz, Z

50Ω,t

≤1 ns, and tf≤ 1 ns.

Note 10: ESD Ratings:

HBM (1.5 kΩ, 100 pF) ≥ 10 kV EIAJ (0 Ω, 200 pF) ≥ 1200 V

Note 11: Output short circuit current (I

) is specified as magnitude only, minus sign indicates direction only.

Note 12: C

includes probe and jig capacitance.

Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. Note 14: f

MAX

generator input conditions: t

1ns(0%to 100%), 50%duty cycle, 0V to 3V.OutputCriteria:dutycycle=45%/55%, VOD>250mV,allchannels

switching.

Parameter Measurement Information

DS100887-3

FIGURE 1. Driver VODand VOSTest Circuit

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Parameter Measurement Information (Continued)

DS100887-4

FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit

DS100887-5

FIGURE 3. Driver Propagation Delay and Transition Time Waveforms

DS100887-6

FIGURE 4. Driver TRI-STATE Delay Test Circuit

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Parameter Measurement Information (Continued)

Typical Application

Applications Information

General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN808, AN977, AN971, AN916, AN805, AN903.

LVDSdriversand receivers are intendedto be primarily used in an uncomplicated point-to-point configuration as is shown in

Figure 6

. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100Ω. A termination resistor of 100Ω (selected to match the media), and is located as close to the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90LV047A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the

other logic state. The output current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in

Figure 6

.AC or unterminated configurations are not allowed. The 3.1 mA loop current will develop a differential voltage of 310mV across the 100Ω termination resistor which the receiver detects with a 250mV minimum differential noise margin, (driven signal minus receiver threshold (250mV – 100mV=150mV)). The signal is centered around +1.2V (Driver Offset, V

) with respect to

ground as shown in

Figure 7

. Note that the steady-state volt-

age (V

) peak-to-peak swing is twice the differentialvoltage

) and is typically 620mV.

The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency.Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I

requirements of the ECL/PECL designs. LVDS requires

80%less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers.

DS100887-7

FIGURE 5. Driver TRI-STATE Delay Waveform

DS100887-8

FIGURE 6. Point-to-Point Application

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Applications Information (Continued)

The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required.

The DS90LV047A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

Power Decoupling Recommendations:

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1µF and 0.001µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground.

PC Board considerations:

Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

Differential Traces:

Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be

10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver.

Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line.

Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels.

Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable.

Termination:

Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice.

Surface mount 1%to 2%resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be

10mm

(12mm MAX).

Probing LVDS Transmission Lines:

Always use high impedance (

100kΩ), low capacitance

(

2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing will give deceiving results.

Cables and Connectors, General Comments:

When choosing cable and connectors for LVDS it is important to remember:

Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities.

Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver.

For cable distances

0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive.

Fail-Safe Feature:

The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver,care should be taken to prevent noise from appearing as a valid signal.

The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.

1. Open Input Pins. The DS90LV048A is a quad receiver

device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs.

2. Terminated Input. If the driver is disconnected (cable

unplugged), or if the driver is in a TRI-STATE or poweroff condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable.

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Applications Information (Continued)

3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to

2.4V). It is only supported with inputs shorted and no external common-mode voltage applied.

External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.

Pin Descriptions

Pin No. Name Description

2, 3, 6, 7 D

Driver input pin, TTL/CMOS compatible

10, 11, 14,15D

OUT+

Non-inverting driver output pin, LVDS levels

9, 12, 13,16D

OUT−

Inverting driver output pin, LVDS levels

1 EN Driver enable pin: When EN is

low, the driver is disabled. When EN is high and EN

is low or open, the driver is enabled. If both EN and EN

are open circuit, then the driver is disabled.

Pin No. Name Description

8EN

Driver enable pin: When EN*is high, the driver is disabled. When EN

is low or open and EN is high, the driver is enabled. If both EN and EN

are open circuit, then the driver is disabled.

Power supply pin, +3.3V±0.3V

5 GND Ground pin

Ordering Information

Operating Package Type/ Order Number

Temperature Number

−40˚C to +85˚C SOP/M16A DS90LV047ATM

−40˚C to +85˚C TSSOP/MTC16 DS90LV047ATMTC

DS100887-9

FIGURE 7. Driver Output Levels

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Typical Performance Curves

Output High Voltage vs Power Supply Voltage

DS100887-14

Output Low Voltage vs Power Supply Voltage

DS100887-15

Output Short Circuit Current vs Power Supply Voltage

DS100887-16

Output TRI-STATE Current vs Power Supply Voltage

DS100887-17

Differential Output Voltage vs Power Supply Voltage

DS100887-18

Differential Output Voltage vs Load Resistor

DS100887-19

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Typical Performance Curves (Continued)

Offset Voltage vs Power Suppy Voltage

DS100887-20

Power Supply Current vs Frequency

DS100887-21

Power Supply Current vs Power Supply Voltage

DS100887-22

Power Supply Current vs Ambient Temperature

DS100887-23

Differential Propagation Delay vs Power Supply Voltage

DS100887-24

Differential Propagation Delay vs Ambient Temperature

DS100887-25

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Typical Performance Curves (Continued)

Differential Skew vs Power Supply Voltage

DS100887-26

Differential Skew vs Ambient Temperature

DS100887-27

Transition Time vs Power Supply Voltage

DS100887-28

Transition Time vs Ambient Temperature

DS100887-29

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Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC

Order Number DS90LV047ATM

NS Package Number M16A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90LV047ATMTC

NS Package Number MTC16

DS90LV047A 3V LVDS Quad CMOS Differential Line Driver

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

Datasheet DS90LV047ATMX, DS90LV047ATMTCX, DS90LV047ATMTC, DS90LV047ATM Datasheet (NSC)

Specifications and Main Features

Frequently Asked Questions

User Manual