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DS90CR218A/DS90CR217
+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel
Link - 85 MHz
General Description
The DS90CR217 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams.Aphase-locked transmit clockis transmitted in
parallel with thedata streams over a fourth LVDS link.Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR218A receiver converts the
three LVDS data streams back into 21 bits of CMOS/TTL
data.At a transmit clockfrequency of 85 MHz, 21 bits ofTTL
data are transmitted at a rate of 595 Mbps per LVDS data
channel. Usinga 85 MHz clock,the data throughputis 1.785
Gbit/s (223 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 85 MHz shift clock support
n 50%duty cycle on receiver output clock
n Best–in–Class Set & Hold Times on TxINPUTs
n Low power consumption
n
±
1V common mode range (around +1.2V)
n Narrow bus reduces cable size and cost
n Up to 1.785 Gbps throughput
n Up to 223 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
Block Diagrams
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS90CR217
DS101080-1
Order Number DS90CR217MTD
See NS Package Number MTD48
DS90CR218A
DS101080-27
Order Number DS90CR218AMTD
See NS Package Number MTD48
November 1999
DS90CR218A/DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-85 MHz
© 1999 National Semiconductor Corporation DS101080 www.national.com
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Pin Diagrams
Typical Application
DS101080-21
DS90CR217
DS101080-22
DS90CR218A
DS101080-23
DS90CR218A/DS90CR217
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Page 3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contactthe National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
CMOS/TTL Input Voltage −0.5V to (V
CC
+ 0.3V)
CMOS/TTL Output Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Driver Output Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Output Short
Circuit Duration Continuous
Junction Temperature +150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) +260˚C
Maximum Package Power Dissipation
@
+25˚C
MTD48 (TSSOP) Package:
DS90CR217 1.98 W
DS90CR218A 1.89 W
Package Derating
DS90CR217 16 mW/˚C above +25˚C
DS90CR218A 15 mW/˚C above +25˚C
ESD Rating
(HBM, 1.5kΩ, 100pF)
>
7kV
(EIAJ, 0Ω, 200pF)
>
700V
Latch Up Tolerance
@
25˚C
>
±
300mA
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (V
CC
) 3.0 3.3 3.6 V
Operating Free Air
Temperature (T
A
) −10 +25 +70 ˚C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
CC
) 100 mV
PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
High Level Input Voltage 2.0 V
CC
V
V
IL
Low Level Input Voltage GND 0.8 V
V
OH
High Level Output Voltage IOH= −0.4 mA 2.7 3.3 V
V
OL
Low Level Output Voltage IOL= 2 mA 0.06 0.3 V
V
CL
Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V
I
IN
Input Current VIN= 0.4V, 2.5V or V
CC
+1.8 +15 µA
V
IN
= GND −10 0 µA
I
OS
Output Short Circuit Current V
OUT
= 0V −60 −120 mA
LVDS DRIVER DC SPECIFICATIONS
V
OD
Differential Output Voltage RL= 100Ω 250 290 450 mV
∆V
OD
Change in VODbetween
Complimentary Output States
35 mV
V
OS
Offset Voltage (Note 4) 1.125 1.25 1.375 V
∆V
OS
Change in VOSbetween
Complimentary Output States
35 mV
I
OS
Output Short Circuit Current V
OUT
= 0V, −3.5 −5 mA
R
L
= 100Ω
I
OZ
Output TRI-STATE®Current PWR DWN = 0V,
±
1
±
10 µA
V
OUT
=0VorV
CC
LVDS RECEIVER DC SPECIFICATIONS
V
TH
Differential Input High Threshold VCM= +1.2V +100 mV
V
TL
Differential Input Low Threshold −100 mV
I
IN
Input Current VIN= +2.4V, VCC= 3.6V
±
10 µA
V
IN
= 0V, VCC= 3.6V
±
10 µA
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current
Worst Case (with Loads)
RL= 100Ω,
C
L
= 5 pF,
Worst Case
Pattern
(
Figures 1, 2
)
f = 33 MHz 28 42 mA
f = 40 MHz 29 47 mA
f = 66 MHz 34 52 mA
f = 85 MHz 39 57 mA
DS90CR218A/DS90CR217
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Page 4
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
I
CCTZ
Transmitter Supply Current
Power Down
PWR DWN = Low
Driver Outputs in TRI-STATE
under Powerdown Mode
10 55 µA
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current Worst
Case
CL= 8 pF,
Worst Case
Pattern
(
Figures 1, 3
)
f = 33 MHz 49 60 mA
f = 40 MHz 53 65 mA
f = 66 MHz 78 100 mA
f = 85 MHz 90 115 mA
I
CCRZ
Receiver Supply Current Power
Down
PWR DWN = Low
Receiver Outputs Stay Low during
Powerdown Mode
140 400 µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
CC
= 3.3V and TA= +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages arereferenced toground unlessotherwise specified (except V
OD
and ∆VOD).
Note 4: V
OS
previously referred as VCM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (
Figure 2
) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (
Figure 2
) 0.75 1.5 ns
TCIT TxCLK IN Transition Time (
Figure 4
) 1.0 6.0 ns
TPPos0 Transmitter Output Pulse Position for Bit0 (
Figure 15
) f = 85 MHz −0.20 0 0.20 ns
TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns
TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns
TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns
TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns
TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns
TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns
TCIP TxCLK IN Period (
Figure 6
) 11.76 T 50 ns
TCIH TxCLK IN High Time (
Figure 6
) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (
Figure 6
) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (
Figure 6
) f = 85 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN (
Figure 6
)0ns
TCCD TxCLK IN to TxCLK OUT Delay
@
25˚C,VCC=3.3V (
Figure 8
) 3.8 6.3 ns
TPLLS Transmitter Phase Lock Loop Set (
Figure 10
)10ms
TPDD Transmitter Powerdown Delay (
Figure 13
) 100 ns
TJIT TxCLK IN Cycle-to-Cycle Jitter 2ns
DS90CR218A/DS90CR217
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (
Figure 3
) 2.0 3.5 ns
CHLT CMOS/TTL High-to-Low Transition Time (
Figure 3
) 1.8 3.5 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (
Figure 16
) f = 85 MHz 0.49 0.84 1.19 ns
RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns
RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns
RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns
RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns
RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns
RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns
RSKM RxIN Skew Margin (Note 5) (
Figure 17
) f = 85 MHz 290 ps
RCOP RxCLK OUT Period (
Figure 7
) 11.76 T 50 ns
RCOH RxCLK OUT High Time (
Figure 7
) f = 85 MHz 4 5 6.5 ns
RCOL RxCLK OUT Low Time (
Figure 7
) 3.5 5 6 ns
RSRC RxOUT Setup to RxCLK OUT (
Figure 7
) 3.5 ns
RHRC RxOUT Hold to RxCLK OUT (
Figure 7
) 3.5 ns
RCCD RxCLK IN to RxCLK OUT Delay
@
25˚C, VCC= 3.3V (Note 6)(
Figure 9
) 5.5 7 9.5 ns
RPLLS Receiver Phase Lock Loop Set (
Figure 11
)10ms
RPDD Receiver Powerdown Delay (
Figure 14
)1µs
Note 5: Receiver Skew Marginis definedas the validdata sampling region at thereceiver inputs. Thismargin takes into account thetransmitter pulse positions(min
and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both
dependent on type/length of cable), and source clock jitter less than 250 ps.
Note 6: Totallatency for thechannel link chipset is afunction of clock period andgate delays throughthe transmitter(TCCD) and receiver(RCCD). The total latency
for the 217/287 transmitter and 218A/288A receiver is: (T + TCCD) + (2
*
T + RCCD), where T=Clock period.
AC Timing Diagrams
DS101080-2
FIGURE 1. “Worst Case” Test Pattern
DS101080-3
DS101080-4
FIGURE 2. DS90CR217 (Transmitter) LVDS Output Load and Transition Times
DS90CR218A/DS90CR217
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AC Timing Diagrams (Continued)
DS101080-5
DS101080-6
FIGURE 3. DS90CR218A (Receiver) CMOS/TTL Output Load and Transition Times
DS101080-7
FIGURE 4. D590CR217 (Transmitter) Input Clock Transition Time
DS101080-8
Note 7: Measurements at V
DIFF
=0V
Note 8: TCCS measured between earliest and latest LVDS edges
Note 9: TxCLK Differential Low→High Edge
FIGURE 5. DS90CR217 (Transmitter) Channel-to-Channel Skew
DS101080-9
FIGURE 6. DS90CR217 (Transmitter) Setup/Hold and High/Low Times
DS90CR218A/DS90CR217
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AC Timing Diagrams (Continued)
DS101080-10
FIGURE 7. DS90CR218A (Receiver) Setup/Hold and High/Low Times
DS101080-11
FIGURE 8. DS90CR217 (Transmitter) Clock In to Clock Out Delay
DS101080-12
FIGURE 9. DS90CR218A (Receiver) Clock In to Clock Out Delay
DS101080-13
FIGURE 10. DS90CR217 (Transmitter) Phase Lock Loop Set Time
DS90CR218A/DS90CR217
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AC Timing Diagrams (Continued)
DS101080-14
FIGURE 11. DS9OCR218A (Receiver) Phase Lock Loop Set Time
DS101080-16
FIGURE 12. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR217)
DS101080-17
FIGURE 13. Transmitter Powerdown Delay
DS90CR218A/DS90CR217
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AC Timing Diagrams (Continued)
DS101080-18
FIGURE 14. Receiver Powerdown Delay
DS101080-19
FIGURE 15. Transmitter LVDS Output Pulse Position Measurement
DS90CR218A/DS90CR217
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AC Timing Diagrams (Continued)
DS101080-28
FIGURE 16. Receiver LVDS Input Strobe Position
DS90CR218A/DS90CR217
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AC Timing Diagrams (Continued)
Applications Information
The DS90CR217 and DS90CR218A are backward compatible with the existing 5V Channel Link transmitter/receiver
pair (DS90CR213, DS90CR214). To upgrade from a 5V to a
3.3V system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V
CC
, LVDS VCCand PLL VCC.
2. Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
3. The receiver powerdown feature when enabled wilI lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain theoutputs in the previous statewhen
powerdown occurred.
DS90CR217 Pin Description—Channel Link Transmitter
Pin Name I/O No. Description
TxIN I 21 TTL level input.
TxOUT+ O 3 Positive LVDS differential data output.
TxOUT− O 3 Negative LVDS differential data output.
TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DWN
I 1 TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at
power down.
V
CC
I 4 Power supply pins for TTL inputs.
GND I 5 Ground pins for TTL inputs.
PLL V
CC
I 1 Power supply pins for PLL.
PLL GND I 2 Ground pins for PLL.
LVDS V
CC
I 1 Power supply pin for LVDS outputs.
LVDS GND I 3 Ground pins for LVDS outputs.
DS90CR218A Pin Description—Channel Link Receiver
Pin Name I/O No. Description
RxIN+ I 3 Positive LVDS differential data inputs.
RxIN− I 3 Negative LVDS differential data inputs.
RxOUT O 21 TTL level data outputs.
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
DS101080-20
C— Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos— Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew—typicaIIy 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 85MHz
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 17. Receiver LVDS Input Skew Margin
DS90CR218A/DS90CR217
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Page 12
Applications Information (Continued)
DS90CR218A Pin Description—Channel Link Receiver (Continued)
Pin Name I/O No. Description
PWR DWN
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V
CC
I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V
CC
I 1 Power supply for PLL.
PLL GND 1 2 Ground pin for PLL.
LVDS V
CC
I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable
lengths (
<
2m), themedia electricalperformance is lesscritical. For higher speed/longdistance applications the media’s
performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between theconductors andpairs). Twin-coax forexample, has
been demonstrated at distances as great as 5 meters and
with the maximum data transfer of 1.785 Gbit/s. Additional
applications information can be found in the following National Interface Application Notes:
AN = #### Topic
AN-1041 Introduction to Channel Link
AN-1108 Channel_link PCB and Interconnect
Design-In Guidelines
AN-1109 Multi-Drop Channel-Link Operation
AN-806 Transmission Line Theory
AN-905 Transmission Line Calculations and
Differential Impedance
AN-916 Cable Information
CABLES: A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21bit CHANNEL LINK chipset (DS90CR217/218A) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR287/288A) requires five pairs of signal
wires. The ideal cable/connectorinterface would havea constant 100Ω differential impedance throughout the path. It is
also recommended that cable skew remain below 90ps ( 85
MHz clock rate) to maintain a sufficient data sampling window at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground provides acommon modereturn path forthe twodevices. Some
of themore commonlyused cabletypes for point-to-pointapplications include flat ribbon, flex, twisted pair and TwinCoax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally
perform well in short point-to-point applications while TwinCoax isgood forshort andlong applications. When using ribbon cable,it isrecommended to placea groundline between
each differential pair to act as a barrierto noise coupling between adjacent pairs. ForTwin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All extended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes providethe subsystem communications designer with many useful guidelines. It is recommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
RECEIVER FAILSAFE FEATURE:These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these
conditions receiver inputs will be in a HIGH state. If a clock
signal ispresent, dataoutputs will all be HIGH;if theclock input isalso floating/terminated, dataoutputs will remainin the
last valid state.A floating/terminated clock input will result in
a HIGH clock output.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise canceling of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the impedance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces).Any discontinuities which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure thatthe differential trace impedance match the differential impedanceof the selected physical media (this impedance should also match the value of the termination resistor
that is connectedacross the differential pairat the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter may be tied to ground or left no connect. All
unused outputs at the RxOUT outputs of the receiver must
then be left floating.
DS90CR218A/DS90CR217
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Page 13
Applications Information (Continued)
TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of thereceiver input. The actualvalue of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18
shows an example. No additional pull-up or pulldown resistors are necessary as with some other differential
technologies such as PECL. Surface mount resistors are
recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decouplingcapacitors (Multi-Layered Ceramic type in surface mount form factor) between each V
CC
and the ground plane(s) are recommended. The three capacitor values are 0.1 µF, 0.01µF and 0.001 µF.An example
is shown in
Figure 19
. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If boardspace is limiting the
number of bypass capacitors, the PLL V
CC
should receive
the most filtering/bypassing. Next would be the LVDS V
CC
pins and finally the logic VCCpins.
CLOCK JITTER: The CHANNEL LINK devices employ a
PLLto generate and recover theclock transmittedacross the
LVDS interface. The width of each bit in the serialized LVDS
data stream isone-seventh the clock period. Forexample, a
85 MHzclock hasa period of 11.76ns whichresults in a data
bit width of 1.68 ns. Differential skew (∆t within one differen-
tial pair), interconnect skew (∆t of one differential pair to another) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noisesignal. Individual bypassing of each V
CC
to ground
will minimizethe noise passed on to the PLL, thus creating a
low jitter LVDS clock. These measures provide more margin
for channel-to-channelskew andinterconnect skew as a part
of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MARGIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold thereforeproviding approximately200 mVof differential noisemargin. Common modeprotection is ofmore importance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V. This allows for a
±
1.0V shifting of the center point due to ground potential differences and common
mode noise.
POWER SEQUENCING AND POWERDOWN MODE: Outputs ofthe CNANNELLINK transmitterremain in TRI-STATE
until the power supply reaches 2V. Clock and data outputs
will begin to toggle 10 ms after V
CC
has reached 3V and the
Powerdown pin is above 1.5V. Either device may be placed
into a powerdownmode at any time byasserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 µW (typical).
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver
clocks (inputand output) stop. The dataoutputs (RxOUT)retain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V
CC
through an internal diode. Current is limited
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.
DS101080-24
FIGURE 18. LVDS Serialized Link Termination
DS101080-25
FIGURE 19. CHANNEL LINK
Decoupling Configuration
DS90CR218A/DS90CR217
www.national.com13
Page 14
Applications Information (Continued)
DS101080-26
FIGURE 20. Single-Ended and Differential Waveforms
DS90CR218A/DS90CR217
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Page 15
Physical Dimensions inches (millimeters) unless otherwise noted
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
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www.national.com
Order Number DS90CR217MTD or DS90CR218AMTD
Dimensions in millimeters only
NS Package Number MTD48
DS90CR218A/DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link-85 MHz
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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