Datasheet DS90CR211, DS90CR212 Datasheet (National Semiconductor)

查询DS90CR211供应商

DS90CR211/DS90CR212
21-Bit Channel Link

General Description

The DS90CR211 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams.Aphase-locked transmit clockis transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR212 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 21 bits of TTLdata are
transmitted at a rate of 280 Mbps per LVDS data channel.
Using a 40 MHz clock, the data throughput is 840
Mbit/s(105 Mbyte/s).

The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 21-bit wide
data bus and one clock, up to 44 conductors are required.
With the Channel Link chipset as few as 9 conductors (3
data pairs, 1 clock pair and a minimum of one ground) are

July 1997

needed. This provides a 80%reduction in required cable
width, providing a system cost savings, reduces connector
physical size, and reduces shielding requirements due to the
cables smaller form factor.

The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, 5 4-bit nibbles plus 1 control, or
2 9-bit (byte + parity) and 3 control.

Features

n Narrow bus reduces cable size and cost

±

n

1V Common mode range (ground shifting)

n 290 mV swing LVDS data transmission
n 840 Mbit/s data throughput
n Low swing differential current mode drivers reduce EMI
n Rising edge data strobe
n Power down mode
n Offered in low profile 48-lead TSSOP package

DS90CR211/DS90CR212 21-Bit Channel Link

Block Diagrams

DS90CR211

Order Number DS90CR211MTD

See NS Package Number MTD48

DS012637-27

DS90CR212

DS012637-1

Order Number DS90CR212MTD

See NS Package Number MTD48

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 1998 National Semiconductor Corporation DS012637 www.national.com

Connection Diagrams

DS90CR211

Typical Application

DS012637-2

DS90CR212

DS012637-3

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DS012637-19

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to (V
CMOS/TTL Ouput Voltage −0.3V to (V
LVDS Receiver Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output

Short Circuit Duration continuous
Junction Temperature +150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature

(Soldering, 4 sec.) +260˚C

Maximum Power Dissipation

) −0.3V to +6V

CC

@

+25˚C

CC
CC
CC
CC

+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)

MTD48 (TSSOP) Package:
DS90CR211 1.98W
DS90CR212 1.89W

Package Derating:

DS90CR211 16 mW/˚C above +25˚C
DS90CR212 15 mW/˚C above +25˚C

This device does not meet 2000V ESD rating (Note 4) .

Recommended Operating
Conditions

Supply Voltage (V

) 4.5 5.5 V

CC

Operating Free Air Temperature (T
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V

) 100 mV

CC

Min Max Units

) −10 +70 ˚C

A

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

V

IL

V

OH

V

OL

V

CL

I

IN

I

OS

LVDS DRIVER DC SPEClFlCATIONS

V

OD

∆V

V

CM

∆V

I

OS

I

OZ

LVDS RECEIVER DC SPECIFlCATIONS

V

TH

V

TL

I

IN

TRANSMITTER SUPPLY CURRENT

I

CCTW

I

CCTZ

RECEIVER SUPPLY CURRENT

I

CCRW

High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
High Level Output Voltage I
Low Level Output Voltage I
Input Clamp Voltage I
Input Current V
Output Short Circuit Current V

Differential Output Voltage R
Change in VODbetween 35 mV

OD

=

−0.4 mA 3.8 4.9 V

OH

=

2 mA 0.1 0.3 V

OL

=

−18 mA −0.79 −1.5 V

CL

=

, GND, 2.5V or 0.4V

V

IN

CC

=

0V −120 mA

OUT

=

100Ω 250 290 450 mV

L

±

5.1

Complementary Output States
Common Mode Voltage 1.1 1.25 1.375 V
Change in VCMbetween 35 mV

CM

Complementary Output States
Output Short Circuit Current V

OUT

=

Output TRI-STATE®Current Power Down=0V, V

Differential Input High Threshold V

=

CM

=

0V, R

100Ω −2.9 −5 mA

L

OUT

=

0V or V

±

CC

1

+1.2V +100 mV
Differential Input Low Threshold −100 mV
Input Current V

Transmitter Supply Current,
Worst Case

Transmitter Supply Current,
Power Down

Receiver Supply Current,
Worst Case

=

+2.4V V

IN

=

V

0V

IN

=

R

100Ω,C

L

Worst Case Pattern

Figure 1,Figure 2

(

=

L

Power Down=Low

=

C

8 pF,

L

Worst Case Pattern

Figure 1,Figure 3

(

5 pF,

)

)

=

5.5V

CC

<

±

1

<

±

1

f=32.5 MHz 34 51 mA

f=37.5 MHz 36 53 mA

125µA

f=32.5 MHz 55 75 mA
f=37.5 MHz 60 80 mA

CC

±

10 µA

±

10 µA

±

10 µA

±

10 µA

PP

V

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

RECEIVER SUPPLY CURRENT

I

CCRZ

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-

fied (except V
Note 4: ESD Rating:

Receiver Supply Current,
Power Down

and ∆VOD).

OD

HBM (1.5 kΩ, 100 pF)
PLL V

≥ 1000V

CC

All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V

CC

=

5.0V and T

Power Down=Low

=

+25˚C.

A

110µA

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

Figure 2

LLHT LVDS Low-to-High Transition Time (
LHLT LVDS High-to-Low Transition Time (
TCIT TxCLK IN Transition Time (

Figure 4

TCCS TxOUT Channel-to-Channel Skew (Note 5) (
TPPos0 Transmitter Output Pulse Position for Bit0 (
TPPos1 Transmitter Output Pulse Position for Bit1 6.3 7.2 7.5 ns
TPPos2 Transmitter Output Pulse Position for Bit2 12.8 13.6 14.6 ns
TPPos3 Transmitter Output Pulse Position for Bit3 20 20.8 21.5 ns
TPPos4 Transmitter Output Pulse Position for Bit4 27.2 28 28.5 ns
TPPos5 Transmitter Output Pulse Position for Bit5 34.5 35.2 35.6 ns
TPPos6 Transmitter Output Pulse Position for Bit6 42.2 42.6 42.9 ns
TPPos0 Transmitter Output Pulse Position for Bit0 (
TPPos1 Transmitter Output Pulse Position for Bit1 2.9 3.3 3.9 ns
TPPos2 Transmitter Output Pulse Position for Bit2 6.1 6.6 7.1 ns
TPPos3 Transmitter Output Pulse Position for Bit3 9.7 10.2 10.7 ns
TPPos4 Transmitter Output Pulse Position for Bit4 13 13.5 14.1 ns
TPPos5 Transmitter Output Pulse Position for Bit5 17 17.4 17.8 ns
TPPos6 Transmitter Output Pulse Position for Bit6 20.3 20.8 21.4 ns
TCIP TxCLK IN Period (
TCIH TxCLK IN High Time (
TCIL TxCLK IN Low Time (
TSTC TxIN Setup to TxCLK IN (

THTC TxIN Hold to TxCLK IN (
TCCD TxCLK IN to TxCLK OUT Delay

Figure 6

) 25 T 50 ns

Figure 6

) 0.35T 0.5T 0.65T ns

Figure 6

) 0.35T 0.5T 0.65T ns

Figure 6

) f = 20 MHz 14 ns

Figure 6

) 2.5 2 ns

@

TPLLS Transmitter Phase Lock Loop Set (
TPDD Transmitter Powerdown Delay (

Note 5: This limit based on bench characterization.

Figure 14

) 0.75 1.5 ns

Figure 2

) 0.75 1.5 ns

)8ns

Figure 5

) 350 ps

Figure 16

Figure 16

)f

)f

=

20 MHz −200 150 350 ps

=

40 MHz −100 100 300 ps

f=40MHz 8 ns

25˚C, V

Figure 10

=

Figure 8

5.0V (

CC

) 5 9.7 ns

)10ms

) 100 ns

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Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

Figure 3

CLHT CMOS/TTL Low-to-High Transition Time (
CHLT CMOS/TTL High-to-Low Transition Time (
RCOP RxCLK OUT Period (

Figure 7

) 25 T 50 ns

) 3.5 6.5 ns

Figure 3

) 2.7 6.5 ns

RSKM Receiver Skew Margin (Note 6) f=20 MHz 1.1 ns

=

V

CC

5V, T

=

25˚C (

A

RCOH RxCLK OUT High Time (

Figure 17

)f

Figure 7

)f

=

40 MHz 700 ps

=

20 MHz 19 ns

f=40 MHz 6 ns

RCOL RxCLK OUT Low Time (

Figure 7

)f

=

20 MHz 21.5 ns

f=40 MHz 10.5 ns

RSRC RxCLK Setup to RxCLK OUT (

Figure 7

)f

=

20 MHz 14 ns

f=40 MHz 4.5 ns

RHRC RxCLK Hold to RxCLK OUT (

Figure 7

)f

=

20 MHz 16 ns

f=40 MHz 6.5 ns
RCCD RxCLK IN to RxCLK OUT Delay
RPLLS Receiver Phase Lock Loop Set (
RPDD Receiver Powerdown Delay (

Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew(TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock(TxCLK IN) jitter.

RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).

@

25˚C, V

Figure 11

Figure 15

=

Figure 9

5.0V (

CC

) 7.6 11.9 ns

)10ms

)1µs

AC Timing Diagrams

FIGURE 1. “WORST CASE” Test Pattern

DS012637-5

FIGURE 2. DS90CR211 (Transmitter) LVDS Output Load and Transition Timing

DS012637-7

FIGURE 3. DS90CR212 (Receiver) CMOS/TTL Output Load and Transition Timing

DS012637-4

DS012637-6

DS012637-8

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AC Timing Diagrams (Continued)

FIGURE 4. DS90CR211 (Transmitter) Input Clock Transition Time

DS012637-9

Measurements at Vdiff=0V
TCCS measured between earliest and latest initial LVDS edges.
TxCLK OUT Differential Low→High Edge

FIGURE 5. DS90CR211 (Transmitter) Channel-to-Channel Skew and Pulse Width

FIGURE 6. DS90CR211 Setup/Hold and High/Low Times

FIGURE 7. DS90CR212 Setup/Hold and High/Low Times

DS012637-10

DS012637-11

DS012637-12

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AC Timing Diagrams (Continued)

FIGURE 8. DS90CR211 (Transmitter) Clock In to Clock Out Delay

FIGURE 9. DS90CR212 (Receiver) Clock In to Clock Out Delay

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FIGURE 10. DS90CR211 (Transmitter) Phase Lock Loop Set Time

DS012637-16

FIGURE 11. DS90CR212 (Receiver) Phase Lock Loop Set Time

DS012637-15

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AC Timing Diagrams (Continued)

FIGURE 12. Seven Bits of LVDS in One Clock Cycle

FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR211)

DS012637-17

DS012637-18

FIGURE 14. Transmitter Powerdown Delay

FIGURE 15. Receiver Powerdown Delay

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DS012637-23

DS012637-24

AC Timing Diagrams (Continued)

FIGURE 16. Transmitter LVDS Output Pulse Position Measurement

DS012637-25

SW— Setup and Hold Time (Internal data sampling window)
TCCS— Transmitter Output Skew
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)
Cable Skew — Typically 10 ps–40 ps per foot

DS012637-26

FIGURE 17. Receiver LVDS Input Skew Margin

DS90CR211 Pin Description—Channel Link Transmitter (Tx)

Pin Name I/O No. Description

TxIN I 21 TTL Level inputs
TxOUT+ O 3 Positive LVDS differential data output
TxOUT− O 3 Negative LVDS differential data output
TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe
TxCLK OUT+ O 1 Positive LVDS differential clock output
TxCLK OUT− O 1 Negative LVDS differential clock output
PWR DOWN
V

CC

GND I 5 Ground pins for TTL inputs

I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down
I 4 Power supply pins for TTL inputs

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DS90CR211 Pin Description—Channel Link Transmitter (Tx) (Continued)

Pin Name I/O No. Description

PLL V

CC

I 1 Power supply pin for PLL
PLL GND I 2 Ground pins for PLL
LVDS V

CC

I 1 Power supply pin for LVDS outputs
LVDS GND I 3 Ground pins for LVDS outputs

DS90CR212 Pin Description—Channel Link Receiver (Rx)

Pin Name I/O No. Description

RxIN+ I 3 Positive LVDS differential data inputs
RxIN− I 3 Negative LVDS differential data inputs
RxOUT O 21 TTL level outputs
RxCLK IN+ I 1 Positive LVDS differential clock input
RxCLK IN− I 1 Negative LVDS differential clock input
RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe
PWR DOWN
V

CC

GND I 5 Ground pins for TTL outputs
PLL V

CC

PLL GND I 2 Ground pin for PLL
LVDS V

CC

LVDS GND I 3 Ground pins for LVDS inputs

I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state

I 4 Power supply pins for TTL outputs

I 1 Power supply for PLL

I 1 Power supply pin for LVDS inputs

Applications Information

The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex­ample, for lower data rate (clock rate) and shorter cable

<

lengths (
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc­tions provide tighter skew (matched electrical length be­tween the conductors and pairs). Twin-coaxfor example, has
been demonstrated at distances as great as 10 meters and
with the maximum data transfer of 1.12 Gbit/s. Additional ap­plications information can be found in the following National
Interface Application Notes:

AN-1035 PCB Design Guidelines for LVDS and

AN-806 Transmission Line Theory
AN-905 Transmission Line Calculations and

AN-916 Cable Information

CABLES: A cable interface between the transmitter and re­ceiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR211/212) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR281/282) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 350 ps (
MHz clock rate) to maintain a sufficient data sampling win­dow at the receiver.

2m), the media electrical performance is less criti-

=

####

AN

Topic

Link Devices

Differential Impedance

@

40

In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro­vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap­plications include flat ribbon, flex, twisted pair and
Twin-Coax.All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally per­form well in short point-to-point applications while Twin-Coax
is good for short and long applications. When using ribbon
cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be­tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex­tended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmis­sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.

The high-speed transport of LVDS signals has been demon­strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com­munications designer with many useful guidelines. It is rec­ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.

BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid

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Applications Information (Continued)

to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can­celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped­ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui­ties which do occur on one signal line should be mirrored in

FIGURE 18. LVDS Serialized Link Termination

UNUSED INPUTS: All unused inputs at the TxW inputs of

the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.

TERMINATION: Use of current mode drivers requires a ter­minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be­tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.

Figure 18

pull-down resistors are necessary as with some other differ­ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that ac­companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re­duce stubs and effectively terminate the differential lines.

DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce­ramic type in surface mount form factor) between each V
and the ground plane(s) are recommended. The three ca­pacitor values are 0.1 µF, 0.01µF and 0.001 µF.An example
is shown in
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL V
the most filtering/bypassing. Next would be the LVDS V
pins and finally the logic VCCpins.

shows an example. No additional pull-up or

CC

Figure 19

. The designer should employ wide

should receive

CC

CC

the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ­ential impedance of the selected physical media (this imped­ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider­ations will limit reflections and crosstalk which adversely ef­fect high frequency performance and EMI.

DS012637-20

DS012637-21

FIGURE 19. CHANNEL LINK

Decoupling Configuration

CLOCK JITTER: The CHANNEL LINK devices employ a

PLLto generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
40 MHz clock has a period of 25 ns which results in a data bit
width of 3.57 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to an­other) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noise signal. Individual bypassing of each V
will minimize the noise passed on to the PLL, thus creating a

to ground

CC

low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.

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Applications Information (Continued)

FIGURE 20. Single-Ended and Differential Waveforms

COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR­GIN: The typical signal swing for LVDS is 300 mV centered

at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differ­ential noise margin. Common mode protection is of more im­portance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V.This allows for a
ter point due to ground potential differences and common
mode noise.

POWER SEQUENCING AND POWERDOWN MODE: Out­puts of the CHANNEL LINK transmitter remain in
TRI-STATE

®

until the power supply reaches 3V. Clock and

data outputs will begin to toggle 10 ms after V

4.5V and the Powerdown pin is above 2V. Either device may
be placed into a powerdown mode at any time by asserting
the Powerdown pin (active low). Total power dissipation for
each device will decrease to 5 µW (typical).

The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or re­ceiver. If power to the transmit board is lost, the receiver
clocks (input and output) stop. The data outputs (RxOUT) re­tain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V
(5 mA per input) by the fixed current mode drivers, thus

through an internal diode. Current is limited

CC

avoiding the potential for latchup when powering the device.

±

1.0V shifting of the cen-

has reached

CC

DS012637-22

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13

Physical Dimensions inches (millimeters) unless otherwise noted

DS90CR211/DS90CR212 21-Bit Channel Link

48-Lead Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90CR211MTD or DS90CR212MTD

NS Package Number MTD48

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2. A critical component in any component of a life support
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.

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