Datasheet DS90CF366MTDX, DS90CF366MTD Datasheet (NSC)

DS90CF386/DS90CF366
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD)
Link—85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link—85 MHz

General Description

The DS90CF386 receiver converts the four LVDS data
streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/
sec bandwidth) back into parallel 28 bits of CMOS/TTL data
(24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL).
Also available is the DS90CF366 that converts the three
LVDS data streams (Up to 1.78 Gbps throughput or 223
Megabytes/sec bandwidth) back into parallel 21 bits of
CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync
and DE). Both Receivers’ outputs are Falling edge strobe. A
Rising edge or Falling edge strobe transmitter (DS90C385/
DS90C365) will interoperate with a Falling edge strobe Re­ceiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.

Features

n 20 to 85 MHz shift clock support
n Rx power consumption

<

142 mW (typ)@85MHz

Grayscale

n Rx Power-down mode

<

1.44 mW (max)

n ESD rating

>

7 kV (HBM),>700V (EIAJ)

n Supports VGA, SVGA, XGA and Single Pixel SXGA.
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package

Block Diagrams

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

DS90CF386

DS101085-27

Order Number DS90CF386MTD

See NS Package Number MTD56

DS90CF366

DS101085-28

Order Number DS90CF366MTD

See NS Package Number MTD48

November 1999

DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit-Color Flat Panel Display (FPD)

Link— 85 MHz, +3.3V LVDS Receiver 18-Bit-Color Flat Panel Display (FPD) Link—85 MHz

© 1999 National Semiconductor Corporation DS101085 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact theNational Semiconductor SalesOffice/
Distributors for availability and specifications.

Supply Voltage (V

CC

) −0.3V to +4V

CMOS/TTL Output Voltage −0.3V to (V

CC

+ 0.3V)

LVDS Receiver Input Voltage −0.3V to (V

CC

+ 0.3V)
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature

(Soldering, 4 sec) +260˚C

Maximum Package Power
Dissipation Capacity

@

25˚C

MTD56 (TSSOP) Package:

DS90CF386 1.61 W

MTD48 (TSSOP) Package:

DS90CF366 1.89 W

Package Derating:

DS90CF386 12.4 mW/˚C above +25˚C
DS90CF366 15 mW/˚C above +25˚C

ESD Rating

(HBM, 1.5 kΩ, 100 pF)

>

7kV

(EIAJ, 0Ω, 200 pF)

>

700V

Recommended Operating
Conditions

Min Nom Max Units

Supply Voltage (V

CC

) 3.0 3.3 3.6 V

Operating Free Air

Temperature (T

A

) −10 +25 +70 ˚C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V

CC

) 100 mV

PP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

High Level Input Voltage 2.0 VCC V

V

IL

Low Level Input Voltage GND 0.8 V

V

OH

High Level Output Voltage IOH= - 0.4 mA 2.7 3.3 V

V

OL

Low Level Output Voltage IOL= 2 mA 0.06 0.3 V

V

CL

Input Clamp Voltage ICL= −18 mA -0.79 -1.5 V

I

IN

Input Current VIN= 0.4V, 2.5V or

V

CC

+1.8 +15 uA

V

IN

= GND -10 0 uA

I

OS

Output Short Circuit Current V

OUT

= 0V -60 -120 mA

LVDS RECEIVER DC SPECIFICATIONS

V

TH

Differential Input High Threshold VCM= +1.2V +100 mV

V

TL

Differential Input Low Threshold −100 mV

I

IN

Input Current VIN= +2.4V, VCC= 3.6V

±

10 µA

V

IN

= 0V, VCC= 3.6V

±

10 µA

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current C

L

= 8 pF, f = 32.5 MHz 49 70 mA

Worst Case Worst Case Pattern, f = 37.5 MHz 53 75 mA

DS90CF386

(Figures

1,4)

f = 65 MHz 81 114 mA

f = 85 MHz 96 135 mA

ICCRW Receiver Supply Current C

L

= 8 pF, f = 32.5 MHz 49 60 mA

Worst Case Worst Case Pattern, f = 37.5 MHz 53 65 mA

DS90CF366

(Figures

1,4)

f = 65 MHz 78 100 mA

f = 85 MHz 90 115 mA

ICCRG Receiver Supply Current, C

L

= 8 pF, f = 32.5 MHz 28 45 mA

16 Grayscale 16 Grayscale Pattern, f = 37.5 MHz 30 47 mA

(Figures 2, 3, 4 )

f = 65 MHz 43 60 mA
f = 85 MHz 43 70 mA

ICCRZ Receiver Supply Current Power Down = Low

140 400 µA

Power Down Receiver Outputs Stay Low during

Power Down Mode

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Electrical Characteristics (Continued)

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V

CC

= 3.3V and TA= +25C.

Note 3: Current into device pins isdefined as positive. Currentout of device pins isdefined as negative. Voltages are referencedto ground unless otherwise speci­fied (except V

OD

and ∆VOD).

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

CLHT CMOS/TTL Low-to-High Transition Time

(Figure 4 )

2.0 3.5 ns

CHLT CMOS/TTL High-to-Low Transition Time

(Figure 4 )

1.8 3.5 ns

RSPos0 Receiver Input Strobe Position for Bit 0

(Figure 11

,

Figure 12 )

f = 85 MHz 0.49 0.84 1.19 ns

RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns
RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns
RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns
RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns
RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns
RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns
RSKM RxIN Skew Margin (Note 4)

(Figure 13 )

f = 85 MHz 290 ps

RCOP RxCLK OUT Period

(Figure 5)

11.76 T 50 ns

RCOH RxCLK OUT High Time

(Figure 5 )

f = 85 MHz 4.5 5 7 ns

RCOL RxCLK OUT Low Time

(Figure 5)

4.0 5 6.5 ns

RSRC RxOUT Setup to RxCLK OUT

(Figure 5 )

3.5 ns

RHRC RxOUT Hold to RxCLK OUT

(Figure 5 )

3.5 ns

RCCD RxCLK IN to RxCLK OUT Delay 25˚C, V

CC

= 3.3V

(Figure 6 )

5.5 7.0 9.5 ns

RPLLS Receiver Phase Lock Loop Set

(Figure 7 )

10 ms

RPDD Receiver Power Down Delay

(Figure 10 )

1µs

Note 4: ReceiverSkew Margin is defined as the validdatasamplingregion at the receiver inputs. This margintakesintoaccount the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter­ference (both dependent on type/length of cable), and clock jitter (less than 150 ps).

AC Timing Diagrams

DS101085-2

FIGURE 1. “Worst Case” Test Pattern

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AC Timing Diagrams (Continued)

DS101085-12

FIGURE 2. “16 Grayscale” Test Pattern (DS90CF386)(Notes 5, 6, 7, 8)

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AC Timing Diagrams (Continued)

Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed

to produce groups of 16 vertical stripes across the display.

Note 7:

Figures 1, 3

show a falling edge data strobe (TxCLK IN/RxCLK OUT).

Note 8: Recommended pin to signal mapping. Customer may choose to define differently.

DS101085-3

FIGURE 3. “16 Grayscale” Test Pattern (DS90CF366)(Notes 5, 6, 7, 8)

DS101085-4

FIGURE 4. DS90CF386/DS90CF366 (Receiver) CMOS/TTL Output Load and Transition Times

DS101085-5

FIGURE 5. DS90CF386/DS90CF366 (Receiver) Setup/Hold and High/Low Times

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AC Timing Diagrams (Continued)

DS101085-6

FIGURE 6. DS90CF386/DS90CF366 (Receiver) Clock In to Clock Out Delay

DS101085-7

FIGURE 7. DS90CF386/DS90CF366 (Receiver) Phase Lock Loop Set Time

DS101085-9

FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF386

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AC Timing Diagrams (Continued)

DS101085-10

FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF366

DS101085-8

FIGURE 10. DS90CF386/DS90CF366 (Receiver) Power Down Delay

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AC Timing Diagrams (Continued)

DS101085-25

FIGURE 11. DS90CF386 (Receiver) LVDS Input Strobe Position

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AC Timing Diagrams (Continued)

DS101085-26

FIGURE 12. DS90CF366 (Receiver) LVDS Input Strobe Position

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AC Timing Diagrams (Continued)

DS101085-11

C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 9) + ISI (Inter-symbol interference) (Note 10)
Cable Skew — typically 10 ps–40 ps per foot, media dependent

Note 9: Cycle-to-cycle jitter is less than 250 ps at 85 MHz.
Note 10: ISI is dependent on interconnect length; may be zero.

FIGURE 13. Receiver LVDS Input Skew Margin

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DS90CF386 Pin Description—24-Bit FPD Link Receiver

Pin Name I/O No. Description

RxIN+ I 4 Positive LVDS differentiaI data inputs.
RxIN− I 4 Negative LVDS differential data inputs.
RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control

lines—FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data

Enable).
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN

I 1 TTL level input. When asserted (low input) the receiver outputs are low.

V

CC

I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V

CC

I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS V

CC

I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.

DS90CF366 Pin Description—18-Bit FPD Link Receiver

Pin Name I/O No. Description

RxIN+ I 3 Positive LVDS differentiaI data inputs.
RxIN− I 3 Negative LVDS differential data inputs.
RxOUT O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,

FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN

I 1 TTL level input. When asserted (low input) the receiver outputs are low.

V

CC

I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V

CC

I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS V

CC

I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.

RECEIVER FAILSAFE FEATURE:

These receivers have input failsafe bias circuitry to guaran­tee a stable receiver output for floating or terminated re­ceiver inputs. Under these conditions receiver inputs will be
in a HIGH state.If a clock signal is present, data outputs will
all be HIGH;if the clock inputis also floating/terminated,data
outputs will remain in the last valid state. A
floating/terminated clock input will result in a LOWclock out­put.

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Pin Diagram

DS90CF386

DS101085-23

DS90CF366

DS101085-13

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Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90CF386MTD
Dimensions in millimeters only

NS Package Number MTD56

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.

2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

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www.national.com

48-Lead Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90CF366MTD
Dimensions in millimeters only

NS Package Number MTD48

DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit-Color Flat Panel Display (FPD)

Link— 85 MHz, +3.3V LVDS Receiver 18-Bit-Color Flat Panel Display (FPD) Link—85 MHz

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.