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查询DS90C387A供应商
DS90C387A/DS90CF388A
Dual Pixel LVDS Display Interface / FPD-Link
General Description
The DS90C387A/DS90CF388A transmitter/receiver pair is
designed to support dual pixel data transmission between
Host and Flat Panel Display up to QXGA resolutions. The
transmitter converts 48 bits (Dual Pixel 24-bit color) of
CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage
Differential Signalling) data streams. At a maximum dual
pixel rate of 112MHz, LVDS data line speed is 784Mbps,
providing a total throughput of 5.7Gbps (714 Megabytes per
second).
The LDI chipset is improved over prior generations of
FPD-Link devices and offers higher bandwidth support and
longer cable drive. To increase bandwidth, the maximum
pixel clock rate is increased to 112 MHz and 8 serialized
LVDS outputs are provided. Cable drive is enhanced with a
user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable
loading effects.
The DS90C387A transmitter provides a second LVDS output
clock. Both LVDS clocks are identical. This feature supports
backward compatibility with the previous generation of
FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a ’dual pixel’ configuration of
two 24-bit or 18-bit FPD-Link receivers.
This chipset is an ideal means to solve EMI and cable size
problems for high-resolution flat panel applications. It pro-
vides a reliable interface based on LVDS technology that
delivers the bandwidth needed for high-resolution panels
while maximizing bit times, and keeping clock rates low to
reduce EMI and shielding requirements. For more details,
please refer to the “Applications Information” section of this
datasheet.
Features
n Supports SVGA through QXGA panel resolutions
n 32.5 to 112/170MHz clock support
n Drives long, low cost cables
n Up to 5.7 Gbps bandwidth
n Pre-emphasis reduces cable loading effects
n Dual pixel architecture supports interface to GUI and
timing controller; optional single pixel transmitter inputs
support single pixel GUI interface
n Transmitter rejects cycle-to-cycle jitter
n 5V tolerant on data and control input pins
n Programmable transmitter data and control strobe select
(rising or falling edge strobe)
n Backward compatible with FPD-Link
n Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link
October 2002
Generalized Transmitter Block Diagram
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
10132002
© 2002 National Semiconductor Corporation DS101320 www.national.com
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Generalized Receiver Block Diagram
DS90C387A/DS90CF388A
Generalized Block Diagrams
10132003
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10132001
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DS90C387A/DS90CF388A
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to +5.5V
CMOS/TTL Output
Voltage −0.3V to (V
LVDS Receiver Input
Voltage −0.3V to +3.6V
LVDS Driver Output
Voltage −0.3V to +3.6V
LVDS Output Short
Circuit Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) +260˚C
Maximum Package Power Dissipation Capacity
100 TQFP Package:
DS90C387A 2.8W
DS90CF388A 2.8W
) −0.3V to +4V
CC
+ 0.3V)
CC
@
25˚C
Package Derating:
DS90C387 A 18.2mW/˚C above +25˚C
DS90CF388 A 18.2mW/˚C above +25˚C
ESD Rating:
DS90C387A
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
>
>
300 V
DS90CF388A
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
>
>
200 V
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (V
Operating Free Air
Temperature (T
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
) 3.0 3.3 3.6 V
CC
A)
−10 +25 +70 ˚C
) 100 mV
CC
6kV
2kV
p-p
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS (Tx inputs, Rx outputs, control inputs and outputs)
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
LVDS DRIVER DC SPECIFICATIONS
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OZ
LVDS RECEIVER DC SPECIFICATIONS
V
TH
V
TL
I
IN
High Level Input Voltage 2.0 V
CC
Low Level Input Voltage GND 0.8 V
High Level Output Voltage IOH= −0.4 mA 2.7 2.9 V
I
= −2 mA 2.7 2.85 V
OH
Low Level Output Voltage IOL= 2 mA 0.1 0.3 V
Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V
Input Current VIN= 0.4V, 2.5V or V
V
= GND −15 0 µA
IN
Output Short Circuit Current V
= 0V −120 mA
OUT
CC
+1.8 +15 µA
Differential Output Voltage RL= 100Ω 250 345 450 mV
Change in VODbetween
35 mV
Complimentary Output States
Offset Voltage 1.125 1.25 1.375 V
Change in VOSbetween
35 mV
Complimentary Output States
Output Short Circuit Current V
Output TRI-STATE®Current PD = 0V, V
= 0V, RL= 100Ω −3.5 −10 mA
OUT
OUT
=0VorV
±
CC
1
±
10 µA
Differential Input High Threshold VCM= +1.2V +100 mV
Differential Input Low Threshold −100 mV
Input Current VIN= +2.4V, VCC= 3.6V
V
= 0V, VCC= 3.6V
IN
±
10 µA
±
10 µA
V
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current
Worst Case
DS90C387A/DS90CF388A
Transmitter Supply Current
16 Grayscale
ICCTZ Transmitter Supply Current
Power Down
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current
Worst Case
ICCRG Receiver Support Current
16 Grayscale
ICCRZ Receiver Supply Current
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
and ∆VOD).
OD
= 3.3V and TA= +25˚C.
CC
R
= 100Ω,CL=5
L
f = 32.5 MHz 115 160 mA
pF,
Worst Case
Pattern
(Figures 1, 3),
DUAL=High
f = 65 MHz 145 200 mA
f = 85 MHz 165 230 mA
f = 112 MHz 210 260 mA
(48-bit RGB)
100Ω,C
= 5 pF,
L
16 Grayscale
Pattern
(Figures 2, 3),
DUAL=High
(48-bit RGB)
f = 32.5 MHz 92 140 mA
f = 65 MHz 100 150 mA
f = 85 MHz 110 170 mA
f = 112 MHz 130 190 mA
PD = Low
Driver Outputs in TRI-STATE under
Powerdown Mode
C
= 8 pF,
L
Worst Case
Pattern
(Figures 1, 4),
DUAL = High
(48-bit RGB)
= 8 pF,
C
L
16 Grayscale
Pattern
(Figures 2, 4),
DUAL = High
(48-bit RGB)
f = 32.5 MHz 100 140 mA
f = 65 MHz 150 200 mA
f = 85 MHz 170 220 mA
f = 112 MHz 185 240 mA
f = 32.5 MHz 45 80 mA
f = 65 MHz 60 110 mA
f = 85 MHz 85 130 mA
f = 112 MHz 110 160 mA
PD = Low
Receiver Outputs stay low
during Powerdown mode.
4.8 50 µA
255 300 µA
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DS90C387A/DS90CF388A
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
TCIT TxCLK IN Transition Time (Figure 5) DUAL=Gnd or Vcc 1.0 2.0 3.0 ns
DUAL=1/2Vcc 1.0 1.5 1.7 ns
TCIP TxCLK IN Period (Figure 6) DUAL=Gnd or Vcc 8.928 T 30.77 ns
DUAL=1/2Vcc 5.88 15.38 ns
TCIH TxCLK in High Time (Figure 6) 0.35T 0.5T 0.65T ns
TCIL TxCLK in Low Time (Figure 6) 0.35T 0.5T 0.65T ns
TXIT TxIN Transition Time 1.5 6.0 ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 3), PRE = 0.75V
(disabled)
LVDS Low-to-High Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.6 ns
LHLT LVDS High-to-Low Transition Time (Figure 3), PRE = 0.75V
(disabled)
LVDS High-to-Low Transition Time (Figure 3), PRE = Vcc (max) 0.11 0.7 ns
TBIT Transmitter Output Bit Width DUAL=Gnd or Vcc 1/7 TCIP ns
DUAL=1/2Vcc 2/7 TCIP ns
TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70 MHz −250 0 +250 ps
f = 70 to 112 MHz −200 0 +200 ps
TCCS TxOUT Channel to Channel Skew 100 ps
TSTC TxIN Setup to TxCLK IN (Figure 6) 2.7 ns
THTC TxIN Hold to TxCLK IN (Figure 6)0ns
TJCC Transmitter Jitter Cycle-to-cycle (Figures
13, 14) (Note 5), DUAL=Vcc
TPLLS Transmitter Phase Lock Loop Set (Figure 8)10ms
TPDD Transmitter Powerdown Delay (Figure 10) 100 ns
f = 112 MHz 85 100 ps
f = 85 MHz 60 75 ps
f = 65 MHz 70 80 ps
f = 56 MHz 100 120 ps
f = 32.5 MHz 75 110 ps
0.14 0.7 ns
0.16 0.8 ns
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (Figure 4), Rx data out 1.52 2.0 ns
CMOS/TTL Low-to-High Transition Time (Figure 4), Rx clock out 0.5 1.0 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 4), Rx data out 1.7 2.0 ns
CMOS/TTL High-to-Low Transition Time (Figure 4), Rx clock out 0.5 1.0 ns
RCOP RxCLK OUT Period (Figure 7) 8.928 T 30.77 ns
DS90C387A/DS90CF388A
RCOH RxCLK OUT High Time (Figure 7)(Note 4) f = 112 MHz 3.5 ns
f = 85 MHz 4.5 ns
RCOL RxCLK OUT Low Time (Figure 7)(Note 4) f = 112 MHz 3.5 ns
f = 85 MHz 4.5 ns
RSRC RxOUT Setup to RxCLK OUT (Figure 7)(Note 4) f = 112 MHz 2.4 ns
f = 85 MHz 3.0 ns
RHRC RxOUT Hold to RxCLK OUT (Figure 7)(Note 4) f = 112 MHz 3.4 ns
f = 85 MHz 4.75 ns
RPLLS Receiver Phase Lock Loop Set (Figure 9)10ms
RPDD Receiver Powerdown Delay (Figure 11)1µs
RSKM Receiver Skew Margin (Figure 12) (Notes 4, 6), f = 112 MHz 170 ps
f = 100 MHz 170 240 ps
f = 85MHz 300 350 ps
f = 66MHz 300 350 ps
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested at 112MHz to verify
functional performance.
Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of
in the clock edge from most graphics VGA chips currently available. This parameter is used when calculating system margin as described in AN-1059.
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
±
3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16).A jitter event of 3ns, represents worse case jump
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AC Timing Diagrams
DS90C387A/DS90CF388A
10132010
FIGURE 1. “Worst Case” Test Pattern
10132011
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
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AC Timing Diagrams (Continued)
DS90C387A/DS90CF388A
FIGURE 3. DS90C387A (Transmitter) LVDS Output Load and Transition Times
FIGURE 4. DS90CF388A (Receiver) CMOS/TTL Output Load and Transition Times
10132012
10132013
10132014
FIGURE 5. DS90C387A (Transmitter) Input Clock Transition Time
FIGURE 6. DS90C387A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
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AC Timing Diagrams (Continued)
FIGURE 7. DS90CF388A (Receiver) Setup/Hold and High/Low Times
DS90C387A/DS90CF388A
10132016
FIGURE 8. DS90C387A (Transmitter) Phase Lock Loop Set Time
FIGURE 9. DS90CF388A (Receiver) Phase Lock Loop Set Time
10132019
10132020
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AC Timing Diagrams (Continued)
DS90C387A/DS90CF388A
10132021
FIGURE 10. Transmitter Power Down Delay
FIGURE 11. Receiver Power Down Delay
C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
j
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
j
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
j
ISI is dependent on interconnect length; may be zero
See Applications Informations section for more details.
FIGURE 12. Receiver Skew Margin
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10132025
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AC Timing Diagrams (Continued)
FIGURE 13. TJCC Test Setup - DS90C387A
DS90C387A/DS90CF388A
10132027
FIGURE 14. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter
10132028
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DS90C387A Pin Description — FPD Link Transmitter
Pin Name I/O No. Description
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
AnP O 8 Positive LVDS differential data output.
AnM O 8 Negative LVDS differential data output.
CLKIN I 1 TTL level clock input.
DS90C387A/DS90CF388A
R_FB I 1 Programmable data strobe select. Rising data strobe edge selected when
R_FDE I 1 Programmable control (DE) strobe select. Tied high for data active when DE
CLK1P O 1 Positive LVDS differential clock output.
CLK1M O 1 Negative LVDS differential clock output.
PD
PLLSEL I 1 PLL range select. This pin must be tied to V
PRE I 1 Pre-emphasis level select. Pre-emphasis is active when input is tied to V
DUAL I 1 Three-mode select for dual pixel, single pixel, or single pixel input to dual
V
CC
GND I 6 Ground pins for TTL inputs and digital circuitry.
PLLV
CC
PLLGND I 3 Ground pins for PLL circuitry.
LVDSV
CC
LVDSGND I 4 Ground pins for LVDS outputs.
CLK2P/NC O 1 Additional positive LVDS differential clock output. Identical to CLK1P. No
CLK2M/NC O 1 Additional negative LVDS differential clock output. Identical to CLK1M. No
Note 10: Inputs default to “low” when left open due to internal pull-down resistor.
Note 11: The PLL range shift point is in the 55 - 68 MHz range, typically the shift will occur during the lock time.
I 51 TTL level input. This includes: 16 Red, 16 Green, 16 Blue, and 3 control
lines HSYNC, VSYNC, DE (Data Enable).(Note 10)
input is high. (Note 10)
is high. (Note 10)
I 1 TTL level input. Assertion (low input) tri-states the outputs, ensuring low
current at power down. (Note 10)
for auto-range. NC or tied to
CC
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 10, 11)
through external pull-up resistor. Resistor value determines pre-emphasis
level (see table in application section). For normal LVDS drive level (No
pre-emphasis) leave this pin open (do not tie to ground).(Note 10)
pixel output operation. Single pixel mode when input is low (only LVDS
channels A0 thru A3 and CLK1 are active) for power savings. Dual mode is
active when input is high. Single in - dual out when input is at 1/2 Vcc. (Note
10)
I 4 Power supply pins for TTL inputs and digital circuitry.
I 2 Power supply pin for PLL circuitry.
I 3 Power supply pin for LVDS outputs.
connect if not used.
connect if not used.
CC
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DS90CF388A Pin Description — FPD Link Receiver
Pin Name I/O No. Description
AnP I 8 Positive LVDS differential data inputs.
AnM I 8 Negative LVDS differential data inputs.
Rn, Gn, Bn,
DE, HSYNC,
VSYNC
RxCLK INP I 1 Positive LVDS differential clock input.
RxCLK INM I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL level clock output. The falling edge acts as data strobe.
R_FDE I 1 Programmable control (DE) strobe select. Tied high for data active when DE
PLLSEL I 1 PLL range select. This pin must be tied to V
PD
STOPCLK O 1 Indicates receiver clock input signal is not present with a logic high. With a
V
CC
GND I 10 Ground pins for TTL outputs and digital circuitry
PLLV
CC
PLLGND I 2 Ground pin for PLL circuitry.
LVDSV
CC
LVDSGND I 3 Ground pins for LVDS inputs.
CNTLE,
CNTLF
Note 12: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions
receiver inputs will be in a HIGH state. If the clock input is floating/terminated, outputs will remain in the last valid state.
O 51 TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3
control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable).
is high. (Note 10)
for auto-range. NC or tied to
CC
Ground is reserved for future use. Typical shift point is between 55 and 68
MHz. (Notes 10, 11)
I 1 TTL level input. When asserted (low input) the receiver data outputs are low
and clock output is high. (Note 10)
clock input present, a low logic is indicated.
I 6 Power supply pins for TTL outputs and digital circuitry.
I 1 Power supply for PLL circuitry.
I 2 Power supply pin for LVDS inputs.
2 No Connect. Make NO Connection to these pins - leave these pins open, do
not tie to ground or V
.
CC
DS90C387A/DS90CF388A
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LVDS Interface / TFT Data (Color) Mapping
Different color mapping options exist. See National Application Notes 1127 and 1163 for details.
The LVDS Clock waveshape is shown in Figure 15. Note that
the rising edge of the LVDS clock occurs two LVDS sub
symbols before the current cycle of data. The clock is compose of a 4 LVDS sub symbol HIGH time anda3LVDSsub
symbol LOW time. The respective pin (transmitter and receiver) names are show in Figure 15. As stated above these
names are not the color mapping information (MSB/LSB) but
DS90C387A/DS90CF388A
pin names only.
Inputs B17 and B27 are double wide bits. If using the
DS90CF388A, this bits are sampled in the back half of the bit
only. Also, the DE signal is mapped to two LVDS sub symbols. The DS90CF388A only samples the DE bit on channel
A2. Two FPD-Link receivers may also be used in place of the
DS90CF388A, since the DS90C387A provides two LVDS
clocks. If this is the case, the FPD-Link receiver datasheet
needs to be consulted for recovery mapping information. In
this application, it is possible to recover two signals of: DE,
B17 and B27 from the transmitter.
There are two reserved bits (RES). The DS90CF388A ignores these bits. If using separate FPD-Link receivers, the
corresponding receiver outputs for these two bits should be
left open (NC).
FIGURE 15. TTL Data Inputs Mapped to LVDS Outputs 387A/388A
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Applications Information
How to configure the DS90C387A and DS90CF388A for
most common application:
1. To configure for single input pixel-to-dual pixel output
application, the DS90C387 “DUAL” pin must be set to 1/2
Vcc=1.65V. This may be implemented using pull-up and
pull-down resistors of 10kΩ. In this configuration, the input
signals (single pixel) are split into odd and even pixel (dual
pixels) starting with the odd (first) pixel outputs A0-to-A3 the
next even (second) pixel outputs to A4-to-A7. The splitting of
the data signal also starts with DE (data enable) transitioning
from logic low to high indicating active data. The ’R_FDE’ pin
must be set high in this case. The number of clock cycles
during blanking must be an EVEN number. This configuration will allow the user to interface to an LDI receiver
(DS90CF388A) or to two FPD-Link ’notebook’ receivers
(DS90CF384A or DS90CF386).
2. To configure for single pixel or dual pixel application using
the DS90C387A/DS90CF388A, the “DUAL” pin must be set
to Vcc (dual) or Gnd (single). In dual mode, the
transmitter-DS90C387A has two LVDS clock outputs enabling an interface to two FPD-Link ’notebook’ receivers
(DS90CF384A or DS90CF386). In single mode, outputs
A4-to-A7 and CLK2 are disabled which reduces power dissipation.
The DS90CF388A is able to support single or dual pixel
interface up to 112MHz operating frequency. This receiver
may also be used to interface to a VGA controller with an
integrated LVDS transmitter.
TABLE 1. Pre-emphasis DC voltage level with (Rpre)
Rpre Resulting PRE Voltage Effects
1MΩ or NC 0.75V Standard LVDS
50kΩ 1.0V
9kΩ 1.5V 50% pre-emphasis
3kΩ 2.0V
1kΩ 2.6V
100Ω Vcc 100% pre-emphasis
DS90C387A/DS90CF388A
Transmitter Features:
The transmitter is designed to reject cycle-to-cycle jitter
which may be seen at the transmitter input clock. Very low
cycle-to-cycle jitter is passed on to the transmitter outputs.
This significantly reduces the impact of jitter provided by the
input clock source, and improves the accuracy of data sampling.
The transmitter is offered with programmable edge data
strobes for convenient interface with a variety of graphics
controllers. The transmitter can be programmed for rising
edge strobe or falling edge strobe through a dedicated pin. A
rising edge transmitter will inter-operate with a falling edge
receiver without any translation logic.
Pre-Emphasis:
Pre-Emphasis adds extra current during LVDS logic transition to reduce the cable loading effects. Pre-emphasis
strength is set via a DC voltage level applied from min to max
(0.75V to Vcc) at the “PRE” pin.A higher input voltage on the
”PRE” pin increases the magnitude of dynamic current during data transition. The “PRE” pin requires one pull-up resistor (Rpre) to Vcc in order to set the DC level. There is an
internal resistor network, which cause a voltage drop. Please
refer to the tables below to set the voltage level.
TABLE 2. Pre-emphasis needed per cable length
Frequency PRE Voltage Typical cable length
112MHz 1.0V 2 meters
112MHz 1.5V 5 meters
80MHz 1.0V 2 meters
80MHz 1.2V 7 meters
65MHz 1.5V 10 meters
56MHz 1.0V 10 meters
Note 13: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating
frequency.
RSKM - Receiver Skew Margin
RSKM is a chipset parameter and is explained in AN-1059 in
detail. It is the difference between the transmitter’s pulse
position and the receiver’s strobe window. RSKM must be
greater than the summation of: Interconnect skew, LVDS
Source Clock Jitter (TJCC), and ISI (if any). See Figure 12.
Interconnect skew includes PCB traces differences, connector skew and cable skew for a cable application. PCB trace
and connector skew can be compensated for in the design of
the system. Cable skew is media type and length dependant.
Power Down:
Both transmitter and receiver provide a power down feature.
When asserted current draw through the supply pins is
minimized and the PLLs are shut down. The transmitter
outputs are in TRI-STATE when in power down mode. The
receiver outputs are forced to a active LOW state when in
the power down mode. (See Pin Description Tables). The PD
pin should be driven HIGH to enable the device once VCCis
stable.
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Applications Information (Continued)
DS90C387/DS90CF388:
The DS90C387A/CF388A chipset is electrically similar to the
DS90C387/CF388. The DS90C387/CF388 is intended for
improved support of longer cable drive. Cable drive is enhanced with a user selectable pre-emphasis feature that
provides additional output current during transitions to counteract cable loading effects. Optional DC balancing on a
Configuration Table
DS90C387A/DS90CF388A
TABLE 3. Transmitter / Receiver configuration table
Pin Condition Configuration
R_FB (Tx only) R_FB = V
R_FB = GND Falling Edge Data Strobe
R_FDE (both Tx and Rx) R_FDE = V
R_FDE = GND Active data DE = Low
DUAL (Tx only) DUAL=V
DUAL=1/2V
DUAL=Gnd 24-bit color (single pixel) support
CC
cycle-to-cycle basis, is also provided to reduce ISI
(Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been
added to deskew long cables of pair-to-pair skew of up to
+/−1 LVDS data bit time (up to 80 MHz Clock Rate). These
three enhancements allow cables 5+ meters in length to be
driven depending upon media and clock rate.
CC
CC
Rising Edge Data Strobe
Active data DE = High
48-bit color (dual pixel) support
CC
Single-to-dual support
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Pin Diagram
DS90C387A/DS90CF388A
Transmitter-DS90C387A
10132006
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Pin Diagram
DS90C387A/DS90CF388A
Receiver-DS90CF388A
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Physical Dimensions inches (millimeters)
unless otherwise noted
DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link
Dimensions show in millimeters
Order Number DS90C387AVJD and DS90CF388AVJD
NS Package Number VJD100A
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can be reasonably expected to cause the failure of
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