Datasheet DS90C032 Datasheet (National Semiconductor)

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DS90C032
LVDS Quad CMOS Differential Line Receiver

DS90C032 LVDS Quad CMOS Differential Line Receiver

September 2003

General Description

TheDS90C032 is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa­tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.

TheDS90C032 accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE
that may be used to multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100Ω) input Fail­safe with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.

TheDS90C032 and companion line driver (DS90C031) pro­vide a new alternative to high power psuedo-ECL devices for
high speed point-to-point interface applications.

®

function

Connection Diagrams

Dual-In-Line

Features

n>155.5 Mbps (77.7 MHz) switching rates
n Accepts small swing (350 mV) differential signal levels
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
n Industrial operating temperature range
n Military operating temperature range option
n Available in surface mount packaging (SOIC) and (LCC)
n Pin compatible with DS26C32A, MB570 (PECL) and

41LF (PECL)

n Supports OPEN, short and terminated input fail-safe
n Compatible with IEEE 1596.3 SCI LVDS standard
n Conforms to ANSI/TIA/EIA-644 LVDS standard
n Available to Standard Microcircuit Drawing (SMD)

5962-95834

LCC Package

Order Number

DS90C032TM

See NS Package Number M16A

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 2003 National Semiconductor Corporation DS011945 www.national.com

01194501

01194520

Order Number

DS90C032E-QML

See NS Package Number E20A

For complete Military Specifications,

refer to appropriate SMD or MDS.

Functional Diagram and Truth Tables

DS90C032

Receiver

ENABLES INPUTS OUTPUT

EN EN* R

LH X Z

All other combinations V

of ENABLE inputs V

01194502

IN+−RIN−

≥ 0.1V H

ID

≤ −0.1V L

ID

R

Full Fail-safe OPEN/SHORT H

or Terminated

OUT

www.national.com 2

DS90C032

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

Input Voltage (R

Enable Input Voltage

(EN, EN*) −0.3V to (V

Output Voltage (R

Maximum Package Power Dissipation

M Package 1025 mW

E Package 1830 mW

Derate M Package 8.2 mW/˚C above +25˚C

Derate E Package 12.2 mW/˚C above +25˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature Range

Soldering (4 sec.) +260˚C

) −0.3V to +6V

CC

IN+,RIN−

) −0.3V to (VCC+0.3V)

) −0.3V to (VCC+0.3V)

OUT

@

+25˚C

CC

+0.3V)

Maximum Junction

Temperature (DS90C032T) +150˚C

Maximum Junction

Temperature (DS90C032E) +175˚C

ESD Rating (Note 7)

(HBM, 1.5 kΩ, 100 pF) ≥ 3,500V

(EIAJ, 0 Ω, 200 pF) ≥ 250V

Recommended Operating
Conditions

Min Typ Max Units

Supply Voltage (V

Receiver Input Voltage GND 2.4 V

Operating Free Air Temperature (T

DS90C032T −40 +25 +85 ˚C

DS90C032E −55 +25 +125 ˚C

) +4.5 +5.0 +5.5 V

CC

)

A

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Note 2)

Symbol Parameter Conditions Pin Min Typ Max Units

V

V

I

V

V

I

I

V

V

I

V

I

I

TH

TL

IN

OH

OL

OS

OZ

IH

IL

I

CL

CC

CCZ

Differential Input High Threshold VCM= +1.2V R

Differential Input Low Threshold −100 mV

Input Current VIN= +2.4V VCC= 5.5V −10

V

= 0V −10

IN

Output High Voltage IOH= −0.4 mA, VID= +200 mV R

I

= −0.4 mA, DS90C032T 3.8 4.9 V

OH

,

IN+

R

IN−

3.8 4.9 V

OUT

+100 mV

±

1 +10 µA

±

1 +10 µA

Input terminated

Output Low Voltage IOL= 2 mA, VID= −200 mV 0.07 0.3 V

Output Short Circuit Current Enabled, V

Output TRI-STATE Current Disabled, V

Input High Voltage EN,

Input Low Voltage 0.8 V

Input Current −10

= 0V (Note 8) −15 −60 −100 mA

OUT

OUT

=0VorV

CC

−10

±

1 +10 µA

2.0 V

EN*

±

1 +10 µA

Input Clamp Voltage ICL= −18 mA −1.5 −0.8 V

No Load Supply Current EN, EN* = VCCor GND, DS90C032T V

CC

3.5 10 mA

Receivers Enabled Inputs Open DS90C032E 3.5 11 mA

EN, EN* = 2.4 or 0.5, Inputs Open 3.7 11 mA

No Load Supply Current EN = GND, EN* = V

CC

DS90C032T 3.5 10 mA

Receivers Disabled Inputs Open DS90C032E 3.5 11 mA

www.national.com3

Switching Characteristics

VCC= +5.0V, TA= +25˚C DS90C032T (Notes 3, 4, 5, 9)

Symbol Parameter Conditions Min Typ Max Units

DS90C032

t

PHLD

t

PLHD

t

SKD

t

SK1

t

TLH

t

THL

t

PHZ

t

PLZ

t

PZH

t

PZL

Differential Propagation Delay High to Low CL= 5 pF 1.5 3.40 5.0 ns

Differential Propagation Delay Low to High VID= 200 mV 1.5 3.48 5.0 ns

Differential Skew |t

PHLD−tPLHD

|(Figure 1 and Figure 2) 0 80 600 ps

Channel-to-Channel Skew (Note 5) 0 0.6 1.0 ns

Rise Time 0.5 2.0 ns

Fall Time 0.5 2.0 ns

Disable Time High to Z RL=2kΩ 10 15 ns

Disable Time Low to Z CL=10pF 10 15 ns

Enable Time Z to High (Figure 3 and Figure 4) 4 10 ns

Enable Time Z to Low 410ns

Switching Characteristics

VCC= +5.0V±10%, TA= −40˚C to +85˚C DS90C032T (Notes 3, 4, 5, 6, 9)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

t

PLHD

t

SKD

t

SK1

t

SK2

t

TLH

t

THL

t

PHZ

t

PLZ

t

PZH

t

PZL

Differential Propagation Delay High to Low CL= 5 pF 1.0 3.40 6.0 ns

Differential Propagation Delay Low to High VID= 200 mV 1.0 3.48 6.0 ns

Differential Skew |t

PHLD−tPLHD

|(Figure 1 and Figure 2) 0 0.08 1.2 ns

Channel-to-Channel Skew (Note 5) 0 0.6 1.5 ns

Chip to Chip Skew (Note 6) 5.0 ns

Rise Time 0.5 2.5 ns

Fall Time 0.5 2.5 ns

Disable Time High to Z RL=2kΩ 10 20 ns

Disable Time Low to Z CL=10pF 10 20 ns

Enable Time Z to High (Figure 3 and Figure 4) 4 15 ns

Enable Time Z to Low 415ns

Switching Characteristics

VCC= +5.0V±10%, TA= −55˚C to +125˚C DS90C032E (Notes 3, 4, 5, 6, 9, 10)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

t

PLHD

t

SKD

t

SK1

t

SK2

t

PHZ

t

PLZ

t

PZH

t

PZL

Differential Propagation Delay High to Low CL= 20 pF 1.0 3.40 8.0 ns

Differential Propagation Delay Low to High VID= 200 mV 1.0 3.48 8.0 ns

Differential Skew |t

PHLD−tPLHD

|(Figure 1 and Figure 2) 0 0.08 3.0 ns

Channel-to-Channel Skew (Note 5) 0 0.6 3.0 ns

Chip to Chip Skew (Note 6) 7.0 ns

Disable Time High to Z RL=2kΩ 10 20 ns

Disable Time Low to Z CL=10pF 10 20 ns

Enable Time Z to High (Figure 3 and Figure 4) 4 20 ns

Enable Time Z to Low 420ns

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Parameter Measurement Information

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

DS90C032

01194503

01194504

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

CLincludes load and test jig capacitance.

for t

and t

S

1=VCC

= GND for t

S

1

PZL

PZH

PLZ

and t

measurements.

measurements.

PHZ

01194505

FIGURE 3. Receiver TRI-STATE Delay Test Circuit

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Parameter Measurement Information (Continued)

DS90C032

FIGURE 4. Receiver TRI-STATE Delay Waveforms

Typical Application

01194506

FIGURE 5. Point-to-Point Application

Applications Information

LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 5. This configuration provides a clean signaling
environment for the quick edge rates of the drivers. The
receiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. A termina­tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu­ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.

TheDS90C032 differential line receiver is capable of detect­ing signals as low as 100 mV, over a
range centered around +1.2V. This is related to the driver
offset voltage which is typically +1.2V. The driven signal is
centered around this voltage and may shift
center point. The
potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef-

±

1V shifting may be the result of a ground

±

1V common-mode

±

1V around this

01194507

fects of coupled noise, or a combination of the two. Both
receiver input pins should honor their specified operating
input voltage range of 0V to +2.4V (measured from each pin
to ground), exceeding these limits may turn on the ESD
protection circuitry which will clamp the bus voltages.

Receiver Fail-Safe:

The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re­ceiver, care should be taken to prevent noise from appearing
as a valid signal.

The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.

1. Open Input Pins. TheDS90C032 is a quad receiver
device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.

www.national.com 6

Applications Information (Continued)

2. Terminated Input. TheDS90C032 requires external fail­safe biasing for terminated input failsafe.

Terminated input failsafe is the case of a receiver that
has a 100Ω termination across its inputs and the driver
is in the following situations. Unplugged from the bus, or
the driver output is in TRI-STATE or in power-off condi­tion. The use of external biasing resistors provide a
small bias to set the differential input voltage while the
line is un-driven, and therefore the receiver output will be
in HIGH state. If the driver is removed from the bus but
the cable is still present and floating, the unplugged
cable can become a floating antenna that can pick up
noise. The LVDS receiver is designed to detect very
small amplitude and width signals and recover them to
standard logic levels. Thus, if the cable picks up more
than 10mV of differential noise, the receiver may re­spond. To insure that any noise is seen as common­mode and not differential, a balanced interconnect and
twisted pair cables is recommended, as they help to
ensure that noise is coupled common to both lines and
rejected by the receivers.

3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ­ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (1.2V

±

1V). It is only supported with inputs shorted and no

external common-mode voltage applied.

4. Operation in environment with greater than 10mV

differential noise.

National recommends external failsafe biasing on its
LVDS receivers for a number of system level and signal
quality reasons. First, only an application that requires
failsafe biasing needs to employ it. Second, the amount
of failsafe biasing is now an application design param­eter and can be custom tailored for the specific applica­tion. In applications in low noise environments, they may
choose to use a very small bias if any. For applications
with less balanced interconnects and/or in high noise
environments they may choose to boost failsafe further.
Nationals "LVDS Owner’s Manual provides detailed cal­culations for selecting the proper failsafe biasing resis­tors. Third, the common-mode voltage is biased by the
resistors during the un-driven state. This is selected to
be close to the nominal driver offset voltage (V
when switching between driven and un-driven states,
the common-mode modulation on the bus is held to a
minimum.

For additional Failsafe Biasing information, please refer
to Application Note AN-1194 for more detail.

The footprint of theDS90C032 is the same as the industry
standard 26LS32 Quad Differential (RS-422) Receiver.

OS

). Thus

DS90C032

www.national.com7

Pin Descriptions

Pin No.

DS90C032

(SOIC)

10, 14

1, 7, 9,15R

11, 13

Name Description

2, 6,

3, 5,

Non-inverting receiver input pin

R

IN+

Inverting receiver input pin

IN−

R

Receiver output pin

OUT

4 EN Active high enable pin, OR-ed with

EN*

12 EN* Active low enable pin, OR-ed with EN

16 V

Power supply pin, +5V±10%

CC

8 GND Ground pin

Ordering Information

Operating Package Type/ Order Number

Temperature Number

−40˚C to +85˚C SOP/M16A DS90C032TM

−55˚C to +125˚C LCC/E20A DS90C032E-QML

DS90C032E-QML (NSID)

5962-95834 (SMD)

Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical
Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device
pins is defined as negative. All voltages are referenced to ground unless
otherwise specified.

Note 3: All typicals are given for: V

Note 4: Generator waveform for all tests unless otherwise specified:f=1

MHz, Z

=50Ω,trand tf(0%–100%) ≤ 1 ns for RINand trand tf≤ 6 ns for EN

O

or EN*.

Note 5: Channel-to-Channel Skew is defined as the difference between the
propagation delay of one channel and that of the others on the same chip with
an event on the inputs.

Note 6: Chip to Chip Skew is defined as the difference between the mini­mum and maximum specified differential propagation delays.

Note 7: ESD Rating:

HBM (1.5 kΩ, 100 pF) ≥ 3,500V

EIAJ (0Ω, 200 pF) ≥ 250V

Note 8: Output short circuit current (I
minus sign indicates direction only. Only one output should be shorted at a
time, do not exceed maximum junction temperature specification.

Note 9: C

Note 10: For DS90C032E propagation delay measurements are from 0V on

the input waveform to the 50% point on the output (R

includes probe and jig capacitance.

L

= +5.0V, TA= +25˚C.

CC

) is specified as magnitude only,

OS

).

OUT

Typical Performance Characteristics

Output High Voltage vs

Power Supply Voltage

01194508 01194509

Output High Voltage vs

Ambient Temperature

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Typical Performance Characteristics (Continued)

DS90C032

Output Low Voltage vs

Power Supply Voltage

Output Short Circuit Current

vs Power Supply Voltage

Output Low Voltage vs

Ambient Temperature

01194510 01194511

Output Short Circuit Current

vs Ambient Temperature

Differential Propagation Delay

vs Power Supply Voltage

01194512 01194513

Differential Propagation Delay

vs Ambient Temperature

01194514 01194515

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Typical Performance Characteristics (Continued)

DS90C032

Differential Skew vs

Power Supply Voltage

Transition Time vs

Power Supply Voltage

01194516

Differential Skew vs

Ambient Temperature

01194517

Transition Time vs

Ambient Temperature

01194518 01194519

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Physical Dimensions inches (millimeters)

unless otherwise noted

DS90C032

20-Lead Ceramic Leadless Chip Carrier, Type C

Order Number DS90C032E-QML

NS Package Number E20A

16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC

Order Number DS90C032TM

NS Package Number M16A

www.national.com11

Notes

DS90C032 LVDS Quad CMOS Differential Line Receiver

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