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DS89C387
Twelve Channel CMOS Differential Line Driver
General Description
The DS89C387 is a high speed twelve channel CMOS differential driver that meets the requirements of TIA/EIA-422-B.
The DS89C387 features a low I
maximum, which makes it ideal for battery powered and
power conscious applications. The device replaces three
DS34C87s and offers a PC board space savings up to 30%.
The twelve channel driver is available in a SSOP package.
The device is ideal for wide parallel bus applications.
Each TRI-STATE
be active or in a HI-impedance offstate.Eachenableiscommon to only two drivers for flexibility and control. The drivers
may be disabled to turn off load current and to save power
when data is not being transmitted.
®
enable (EN) allows the driver outputs to
specification of 1.5 mA
CC
Connection Diagram Functional Diagram
48L SSOP
DS89C387
The driver’s input (DI) is compatible with both TTL and
CMOS signal levels.
Features
n Low power ICC: 1.5 mA maximum
n Meets TIA/EIA-422-B (RS-422)
n Guaranteed AC parameters:
— Maximum driver skew −3 ns
— Maximum transition time −10 ns
n Available in SSOP packaging:
— Requires 30%less PCB space than 3 DS34C87TMs
DS89C387 Twelve Channel CMOS Differential Line Driver
May 1995
1/6 of package
DS012086-2
Truth Table
Enable Input Outputs
EN DI DO DO
LXZZ
HHHL
HLLH
DS012086-1
Order Number DS89C387TMEA
See NS Package Number MS48A
TRI-STATE®is a registered trademarkof National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012086 www.national.com
*
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Lead Temperature (T
)
L
(Soldering 4 sec.) 260˚C
This device does not meet 2000V ESD rating. (Note 11)
Distributors for availability and specifications.
Supply Voltage (V
DC Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
) −0.5 to 7.0V
CC
) −1.5 to VCC+1.5V
IN
) −0.5 to 7V
OUT
IK,IOK
DC Output Current, per pin (I
or GND Current (ICC)
DC V
CC
Storage Temperature Range (T
Maximum Power Dissipation (P
)
)
OUT
) −65˚C to +150˚C
STG
)@25˚C (Note 3)
D
±
20 mA
±
150 mA
±
500 mA
Operating Conditions
Supply Voltage (V
DC Input or Output Voltage (V
Operating Temperature Range (T
) 4.50 5.50 V
CC
IN,VOUT
A
DS89C387T −40 +85 ˚C
Input Rise or Fall Times (t
) 500 ns
r,tf
Min Max Units
)0VCCV
)
SSOP Package 1359 mW
DC Electrical Characteristics (Notes 2, 4)
=
V
V
IH
V
IL
V
OH
V
OL
V
T
|V
T
V
OS
|V
OS–VOS
I
IN
I
CC
I
OZ
I
SC
I
OFF
Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive; all currents out of device pins are negative.
Note 3: Ratings apply to ambient temperature at 25˚C. Above this temperature derate SSOP (MEA) Package 10.9 mW/˚C.
Note 4: Unless otherwise specified, min/max limits apply across the −40˚C to 85˚C temperature range. All typicals are given for V
Note 5: See TIA/EIA-422-B for exact test conditions.
Note 6: Measured per input. All other inputs at V
Note 7: This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted.
±
10%(unless otherwise specified)
5V
CC
Symbol Parameter Conditions Min Typ Max Units
High Level Input 2.0 V
CC
Voltage
Low Level Input GND 0.8 V
Voltage
High Level Output V
Voltage I
Low Level Output V
Voltage I
Differential Output R
=
or VIL, 2.5 3.4 V
V
IN
IH
=
−20 mA
OUT
=
or VIL, 0.3 0.5 V
V
IN
IH
=
48 mA
OUT
=
100Ω 2.0 3.1 V
L
Voltage (Note 5)
|–|VT| Difference In R
=
100Ω 0.4 V
L
Differential Output (Note 5)
Common Mode R
=
100Ω 2.0 3.0 V
L
Output Voltage (Note 5)
| Difference In R
=
100Ω 0.4 V
L
Common Mode Output (Note 5)
Input Current V
Quiescent Supply I
Current V
TRI-STATE Output V
=
V
IN
CC
=
0 µA, 600 1500 µA
OUT
=
V
IN
CC
=
V
2.4V or 0.5V (Note 6) 0.8 2.0 mA
IN
=
V
OUT
Leakage Current Control=V
Output Short V
=
V
IN
CC
, GND, VIH,orV
IL
or GND
CC
IL
or GND
±
0.5
or GND −30 −115 −150 mA
±
1.0 µA
±
5.0 µA
Circuit Current (Notes 5, 7)
Power Off Output V
CC
=
0V V
Leakage Current (Note 5) V
or GND.
CC
=
6V 100 µA
OUT
=
−0.25V −100 µA
OUT
=
5V and T
CC
=
25˚C.
A
V
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Switching Characteristics (Note 4)
=
V
±
10%,tr,tf≤6ns(
5V
CC
Figures 1, 2, 3, 4
)
Symbol Parameter Conditions Min Typ Max Units
t
PLH,tPHL
Propagation Delay S1 Open 2 6 11 ns
Input to Output
Skew (Note 8) S1 Open 0 0.5 3 ns
t
TLH,tTHL
Differential Output Rise S1 Open 6 10 ns
And Fall Times
t
PZH
t
PZL
t
PHZ
t
PLZ
C
PD
Output Enable Time S1 Closed 12 25 ns
Output Enable Time S1 Closed 13 26 ns
Output Disable Time (Note 9) S1 Closed 4 8 ns
Output Disable Time (Note 9) S1 Closed 6 12 ns
Power Dissipation 100 pF
Capacitance (Note 10)
C
IN
Note 8: Skew is defined as the difference in propagation delays between complementary outputs at the crossing point.
Note 9: Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are less than indicated
due to the delay added by the RC time constant of the load.
Note 10: C
PD
.
I
CC
Note 11: ESD Rating: HBM (1.5 kΩ, 100 pF)
Inputs ≥ 1500V
Outputs ≥ 1000V
EIAJ (0Ω, 200 pF)
All Pins ≥ 350V
Input Capacitance 6 pF
determines the no load dynamic power consumption, P
=
V2CCf+ICCVCC, and the no load dynamic current consumption, I
C
D
PD
=
C
S
PDVCC
Logic Diagram
f+
DS012086-3
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Parameter Measurement Information
C1=C2=C3=40 pF (including Probe and Jig Capacitance), R1=R2=50Ω,R3=500Ω
FIGURE 1. AC Test Circuit
FIGURE 2. Propagation Delays
DS012086-4
DS012086-5
FIGURE 3. Enable and Disable Times
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DS012086-6
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Parameter Measurement Information (Continued)
Input pulse; f=1 MHz, 50%,tr≤6 ns, tf≤ 6ns
FIGURE 4. Differential Rise and Fall Times
Typical Application
*RTis optional although highly recommended to reduce reflection.
FIGURE 5. Two-Wire Balanced System, RS-422
Application Information
SKEW
Skew may be thought of in a lot of different ways, the next
few paragraphs should clarify what is represented by “Skew”
in the datasheet and how it is determined. Skew, as used in
this databook, is the absolute value of a mathematical difference between two propagation delays. This is commonly accepted throughout the semiconductor industry. However,
there is no standardized method of measuring propagation
delay, from which skew is calculated, of differential line drivers. Elucidating, the voltage level, at which propagation delays are measured, on both input and output waveforms are
(Circuit 1)
DS012086-7
DS012086-8
not always consistant. Therefore, skew calculated in this
datasheet, may not be calculated the same as skew defined
in another. This is important to remember whenever making
a skew comparison.
Skew may be calculated for the DS89C387, from many different propagation delay measurements. They may be classified into three categories, single-ended, differential, and
complementry. Single-ended skew is calculated from t
and t
measurements (see
PLH
is calculated from t
ures 8, 9
). Complementry skew is calculated from t
t
measurements (see
PLH
PHLD
Figures 6, 7
and t
measurements (see
PLHD
Figures 10, 11
). Differential skew
).
PHL
PHL
Fig-
and
(Circuit 2)
DS012086-9
FIGURE 6. Circuits for Measuring Single-Ended Propagation Delays (See
DS012086-10
Figure 7
)
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Application Information (Continued)
Waveforms for Circuit 1
DS012086-11
FIGURE 7. Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See
Figure 2
In
, VX, where X is a number, is the waveform voltage level at which the propagation delay measurement either starts or stops. Furthermore, V1 and V2 are normally
identical. The same is true for V3 and V4. However,as mentioned before, these levels are not standardized and may
vary, even with similar devices from other companies. Also
note, NC (no connection) in
Figure 1
means the pin is not
used in propagation delay measurement for the corresponding circuit.
The single-ended skew provides information about the pulse
width distortion of the output waveform. The lower the skew,
the less the output waveform will be distorted. For best case,
skew would be zero, and the output duty cycle would be
50%, assuming the input has a 50%duty cycle.
(Circuit 3)
DS012086-13
FIGURE 8. Circuit for Measuring Differential
Propagation Delays (See
Figure 9
)
Waveforms for Circuit 2
DS012086-12
Figure 6
)
However, if V3 and V4 are specified voltages, then V3 and
V4 are less likely to be equal to the crossing point voltage.
Thus, the differential propagation delays will not be measured to zero volts on the differential waveform.
The differential skew also provides information about the
pulse width distortion of the differential output waveform relative to the input waveform. The higher the skew, the greater
the distortion of the differential output waveform. Assuming
the input has a 50%duty cycle, the differential output will
have a 50%duty cycle if skew equals zero and less than a
50%duty cycle if skew is greater than zero.
(Circuit 4)
DS012086-15
FIGURE 10. Circuit for Measuring Complementary
Skew (See
Figure 11
)
Waveforms for Circuit 4
Waveforms for Circuit 3
DS012086-14
FIGURE 9. Propagation Delay Waveforms
for Circuit 3 (See
Figure 8
)
For differential propagation delays, V1 should equal V2. Fur-
*
thermore, the crossing point of DO and DO
corresponds to
zero volts on the differential waveform (see bottom waveform in
Figure 9
). This is true whether V3 equals V4 or not.
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DS012086-16
FIGURE 11. Waveforms for Circuit 4 (See
Figure 10
)
Complementary skew is calculated from single-ended propagation delay measurements on complementary output signals, DO and DO
ues, they are identical on DO and DO
*
. Note, when V3 and V4 are absolute val-
*
; but vary whenever
they are relative values.
The complementary skew reveals information about the con-
tour of the rising and falling edge of the differential output
Page 7
Application Information (Continued)
signal of the driver.This is important information because the
receiver will interpret the differential output signal. If the differential transitions do not continuously ascend or decend
through the receivers threshold region, errors may occur.Errors may also occur if the transitions are too slow.
In addition, complementary skew provides information about
the common mode modulation of the driver. The common
mode voltage is represented by (DO–DO
*
)/2. This informa-
low propagation delay. The minimum channel to channel
skew is 0 ns since it is possible for all 12 drivers to have
identical propagation delays. Note, this is best and worst
case calculations used whenever Skew (channel) is not independently characterized and specified in the datasheet.
The device to device skew may be calculated in the same
way and the results are the same. Therefore, the device to
device skew is 9 ns and 0 ns maximum and minimum respectively.
tion may be used as a means for determining EMI affects.
Only “Skew” is specified in this datasheet for the DS89C387.
It refers to the complementary skew of the driver. Complementary skew is measured at both V3 and V4 (see
Figure 11
).
More information can be calculated from the propagation delays. The channel to channel and device to device skew may
be calculated in addition to the types of skew mentioned previously.These parameters provide timing performance information beneficial when designing. The channel to channel
skew is calculated from the variation in propagation delay
from receiver to receiver within one package. The device to
device skew is calculated from the variation in propagation
delay from one DS89C387 to another DS89C387.
For the DS89C387, the maximum channel to channel skew
is9ns(t
max–tpmin) where tpis the low to high or high to
p
Skew (comp.) 0 0.5 3 ns
Skew (channel) 0 9 ns
Skew (device) 0 9 ns
Note Skew (comp.) in
datasheet. Also Skew (channel) and Skew (device) are calculations, but are guaranteed by the propagation delay tests.
Both Skew (channel) and Skew (device) would normally be
tighter whenever specified from characterization data.
The information in this section of the datasheet is to help
clarity how skew is defined in this datasheet. This should
help when designing the DS89C387 into most applications.
DS89C387 Equivalent Input/Output Circuits
TABLE 1. DS89C387 Skew Table
Parameter Min Typ Max Units
Table 1
is the same as “Skew” in the
DS012086-17
FIGURE 12. Driver Output Equivalent Circuit
DS012086-18
FIGURE 13. Driver Input or
Driver Enable Equivalent Circuit
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Pin Descriptions
TABLE 2. Device Pin Names and Descriptions
#
Pin
7, 8, 15, 16, 22, 23, DI TTL/CMOS Compatible Driver Input
31, 32, 39, 40, 46, 47
2, 6, 9, 13, 17, 21, DO Non-Inverting Driver Output Pin
26, 30, 33, 37, 41, 45
3, 5, 10, 12, 18, 20, DO
27, 29, 34, 36, 44, 44
4, 11, 19, 28, 35, 43 EN Active High Dual Driver Enabling Pin
38 V
14, 24 GND Device Ground Pin
1, 25, 48 NC Unused Pin (NOT CONNECTED)
Pin
Name
CC
*
Inverting Driver Output Pin
Positive Power Supply Pin +5±10
Pin Description
%
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead (0.300" Wide) Molded Shrink Small Outline Package, JEDEC
Order Number DS89C387TMEA
NS Package Number MS48A
DS89C387 Twelve Channel CMOS Differential Line Driver
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