Page 1
Rev 1; 2/08
PART TEMP RANGE PIN-PACKAGE
DS8113-RNG+ -40°C to +85°C 28 SO
PGND
28
27
26
25
24
23
22
AUX2IN
AUX1IN
I/OIN
XTAL2
TOP VIEW
DS8113
XTAL1
OFF
GND
21 VDD
20 RSTIN
19 CMDVCC
18 1_8V
17 VCC
16 RST
15 CLK
5V/3V
CLKDIV2
CLKDIV1
CP1
VDDA
VUP
PRES
PRES
I/O
AUX2
AUX1
4
1
2
3
5
6
7
8
9
10
11
12
13
14CGND
CP2
SO
Smart Card Interface
General Description
The DS8113 smart card interface is a low-cost, analog
front-end for a smart card reader, designed for all ISO
7816, EMV™, and GSM11-11 applications. The DS8113
supports 5V, 3V, and 1.8V smart cards. The DS8113
provides options for low active- and stop-mode power
consumption, with as little as 10nA stop-mode current.
The DS8113 is designed to interface between a system
microcontroller and the smart card interface, providing
all power supply, ESD protection, and level shifting
required for IC card applications.
An EMV Level 1 certified library (written for the MAXQ2000
microcontroller) and hardware reference design is
available. Contact Maxim technical support at
micro.support@maxim-ic.com regarding requirements for
other microcontroller platforms. An evaluation kit,
DS8113-KIT, is available to aid in prototyping and
evaluation.
Applications
Consumer Set-Top Boxes
Access Control
Banking Applications
POS Terminals
Debit/Credit Payment Terminals
PIN Pads
Automated Teller Machines
Telecommunications
Pay/Premium Television
Features
♦ Analog Interface and Level Shifting for IC Card
Communication
♦ 8kV (min) ESD (IEC) Protection on Card Interface
♦ Ultra-Low Stop-Mode Current, Less Than 10nA
Typical
♦ Internal IC Card Supply-Voltage Generation:
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)
1.8V ±10%, 30mA (max)
♦ Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
♦ I/O Lines from Host Directly Level Shifted for
Smart Card Communication
♦ Flexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8
♦ High-Current, Short-Circuit and High-Temperature
Protection
♦ Low Active-Mode Current
Pin Configuration
DS8113
Ordering Information
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead-free package.
Selector Guide appears at end of data sheet.
EMV is a trademark owned by EMVCo LLC.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to:
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
________________________________________________________________ Maxim Integrated Products 1
www.maxim-ic.com/errata.
Page 2
Smart Card Interface
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUP PLY
Digital Supply Voltage V
DD
2.7 6.0 V
Card Voltage-Generator Supply Volt age V
DDA
V
DDA
> V
DD
5.0 6.0 V
V
TH2
Thresho ld volt age (falling) 2.35 2.45 2.55 V
Reset Voltage Thresholds
V
HYS2
Hysteresi s 50.0 100 150 mV
CURRENT CONSUMPTION
Acti ve VDDCurrent 5V Cards
(Including 80mA Draw from 5V Card)
I
DD_50V
ICC= 80mA, f
XTAL
= 20MHz,
f
CLK
= 10MHz, V
DDA
= 5.0V
80.75 85.00 mA
Acti ve VDDCurrent 5V Cards
(Current Con sumed by DS8113 Only)
I
DD_IC
ICC= 80mA, f
XTAL
= 20MHz,
f
CLK
= 10MHz, V
DDA
= 5.0V (Note 2)
0.75 5.00 mA
Acti ve VDDCurrent 3V Cards
(Including 65mA Draw from 3V Card)
I
DD_30V
ICC= 65mA, f
XTAL
= 20MHz,
f
CLK
= 10MHz, V
DDA
= 5.0V
65.75 70.00 mA
Acti ve VDDCurrent 3V Cards
(Current Con sumed by DS8113 Only)
I
DD_IC
ICC= 65mA, f
XTAL
= 20MHz,
f
CLK
= 10MHz, V
DDA
= 5.0V (Note 2)
0.75 5.00 mA
Acti ve VDDCurrent 1.8V Cards
(Including 30mA Draw from 1.8V Card)
I
DD_18V
ICC= 30mA, f
XTAL
= 20MHz,
f
CLK
= 10MHz, V
DDA
= 5.0V
30.75 35.00 mA
Acti ve VDDCurrent 1.8V Cards
(Current Con sumed by DS8113 Only)
I
DD_IC
ICC= 30mA, f
XTAL
= 20MHz,
f
CLK
= 10MHz, V
DDA
= 5.0V (Note 2)
0.75 5.00 mA
Inacti ve-Mode Current I
DD
Card inact ive, act ive-high PRES,
DS8113 not in stop mode
50.0 200 µA
Stop-Mode Current I
DD_STOP
DS8113 in ultra-low-power stop
mode (CMDVCC, 5V/3V, and 1 _8V
set to l og ic 1) (Note 3)
0.01 2.00 µA
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD Relative to GND...............-0.5V to +6.5V
oltage Range on VDDA Relative to PGND ..........-0.5V to +6.5V
V
Voltage Range on CP1, CP2, and VUP
Relative to PGND...............................................-0.5V to +7.5V
oltage Range on All Other Pins
V
Relative to GND......................................-0.5V to (V
DS8113
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DD
+ 0.5V)
RECOMMENDED DC OPERATING CONDITIONS
(VDD= +3.3V, V
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
DDA
Maximum Junction Temperature .....................................+125°C
aximum Power Dissipation (T
M
Storage Temperature Range .............................-55°C to +150°C
-25°C to +85°C) .......700mW
=
A
Soldering Temperature.........Refer to the IPC/JEDEC J-STD-020
pecification.
S
2 _______________________________________________________________________________________
Page 3
Smart Card Interface
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK SOURCE
Crysta l Frequency f
XTAL
External crystal 0 20 MHz
f
XTAL1
0 20 MHz
V
IL_XTAL1
Low-level input on XTAL1 -0.3
0.3 x
V
D
D
XTAL1 Operating Condit ions
V
IH_XTAL1
High-level input on XTAL1
0.7 x
V
DD
VDD+
0.3
V
External Capacitance for Cryst al
C
XTAL1
,
C
XTAL2
15 pF
Internal Osc illator f
INT
2.2 2.7 3.2 MHz
SHUTDOWN TEMPERATURE
Shutdown Temperature T
SD
+150 °C
RST PIN
Output Low Volt age V
OL_RST1IOL_RST
= 1mA 0 0.3 V
Card-Inactive Mode
Output Current I
OL_RST1VO_LRST
= 0V 0 -1 mA
Output Low Volt age V
OL_RST2IOL_RST
= 200µA 0 0.3 V
Output H igh
Voltage
V
OH_RST2IOH_RST
= -200µA
V
CC
-
0.5
V
CC
V
Rise Tim e t
R_RST
CL= 30pF 0.1 µ s
Fall Time t
F_RST
CL= 30pF 0.1 µ s
Shutdown Current
Thresho ld
I
RST(SD)
-20 mA
Current Lim itation I
RST(LIMIT)
-20 +20 mA
Card-Active Mode
RSTIN to RST Delay t
D(RSTIN-RST)
2 µs
CLK PIN
Output Low Volt age V
OL_CLK1IOLCLK
= 1mA 0 0.3 V
Card-Inactive Mode
Output Current I
OL_CLK1VOLCLK
= 0V 0 -1 mA
Output Low Volt age V
OL_CLK2IOLCLK
= 200µA 0 0.3 V
Output H igh
Voltage
V
OH_CLK2IOHCLK
= -200µA
V
CC
-
0.5
V
CC
V
Rise Tim e t
R_CLK
CL= 30pF (Note 4) 8 ns
Fall Time t
F_CLK
CL= 30pF (Note 4) 8 ns
Current Lim itation I
CLK(LIMIT)
-70 +70 mA
Clock Freq uenc y f
CLK
Operational 0 10 MHz
Duty Fact or CL= 30pF 45 55 %
Card-Active Mode
Slew Rate SR C
L
= 30pF 0.2 V/ns
VCC PIN
Output Low Volt age V
CC1
ICC= 1mA 0 0.3 V
Card-Inactive Mode
Output Current I
CC1
VCC= 0V 0 -1 mA
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
DDA
_______________________________________________________________________________________ 3
DS8113
Page 4
Smart Card Interface
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
65mA < I
CC(5V)
< 80mA 4. 55 5.00 5.25
I
CC(5V)
< 65mA 4.75 5.00 5.25
I
CC(3V)
< 65mA 2.78 3.00 3.22
I
CC(1.8V)
< 30mA 1.65 1.80 1.95
5V card; current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20 MHz
4.6 5.4
3V card; current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20 MHz
2.75 3.25
Output Low Volt age V
CC2
1.8V card; current pul ses of 12nC
with I < 200mA, t < 400ns,
f < 20 MHz
1.62 1.98
V
V
CC(5V)
= 0 to 5V -80
V
CC(3V)
= 0 to 3V -65
Output Current I
CC2
V
CC(1.8V)
= 0 to 1.8V -30
mA
Shutdown Current
Thresho ld
I
CC(SD)
120 mA
Card-Active Mode
Slew Rate V
CCSR
Up/down; C < 300nF (Note 5) 0.05 0.16 0.22 V/µs
DATA LINES (I/O A ND I/OIN)
I/O I/OIN Fall ing Edge Dela y t
D(IO-IOIN)
200 ns
Pullup Pul se Active T ime t
PU
100 ns
Maximum Frequency f
IOMAX
1 MHz
Input Capacitance C
I
10 pF
I/O, AUX1, AUX2 PIN S
Output Low Volt age V
OL_IO1IOL_IO
= 1mA 0 0.3 V
Output Current I
OL_IO1
V
OL_IO
= 0V 0 -1 mA
Card-Inactive Mode
Internal Pul lup
Res istor
R
PU_IO
To V
CC
9 11 19 k
Output Low Volt age V
OL_IO2IOL_IO
= 1mA 0 0.3 V
I
OH_IO
= < -20µA 0.8 x V
CC
V
CCOutput H igh
Voltage
V
OH_IO2
I
OH_IO
= < -40µA (3V/5V) 0.75 x V
CC
V
CC
V
Output Ri se/Fall
Time
t
OT
CL= 30pF 0.1 µ s
Input Low Voltage V
IL_IO
-0.3 +0.8
Input High Voltage V
IH_IO
1.5 V
CC
V
Input Low Current I
IL_IO
V
IL_IO
= 0V 600 µA
Input High Current I
IH_IO
V
IH_IO
= V
CC
20 µA
Input Ri se/Fa ll Time t
IT
1.2 µ s
Current Lim itation I
IO(LIMIT)CL
= 30pF -15 +15 mA
Card-Active Mode
Current When
Pullup Act ive
I
PU
CL= 80pF, VOH= 0.9 x V
DD
-1 mA
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
DDA
DS8113
4 _______________________________________________________________________________________
Page 5
Smart Card Interface
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/OIN, AUX1IN, AUX2IN PIN S
Output Low Volt age V
O
L
I
O
L
= 1mA 0 0.3 V
No Load
0.9 x
V
DD
VDD+
0.1
Output H igh Voltage V
OH
IOH< -40µA
0.75 x
V
DD
VDD+
0.1
V
Output Ri se/Fall T ime t
OT
CL= 30pF, 10% to 90% 0.1 µ s
Input Low Voltage V
I
L
-0.3
0.3 x
V
DD
V
Input High Vo ltage V
IH
0.7 x
V
DD
VDD+
0.3
V
Input Low Current I
IL_IO
VIL= 0V 600 µA
Input High Current I
IH_IO
VIH= V
DD
10 µA
Input R ise/Fal l T ime t
IT
VILto V
IH
1.2 µ s
Integrated Pullup Resistor R
PU
Pullup to V
DD
9 11 13 k
Current When Pullup Act ive I
PU
CL= 30pF, VOH= 0.9 x V
DD
-1 mA
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V, 1_8V)
Input Low Voltage V
IL
-0.3
0.3 x
V
DD
V
Input High Vo ltage V
IH
0.7 x
V
DD
VDD+
0.3
V
Input Low Current I
IL_IO
0 < VIL< V
DD
5 µ A
Input High Current I
IH_IO
0 < VIH< V
DD
5 µ A
INTERRUPT OUTPUT PIN (OFF)
Output Low Volt age V
OL
IOL= 2mA 0 0.3 V
Output H igh Voltage V
OH
IOH= -15µA
0.75 x
V
DD
V
Integrated Pullup Resistor R
PU
Pullup to V
DD
16 20 24 k
PRES, PRES PINS
Input Low Voltage V
IL_PRES
0.3 x
V
DD
V
Input High Vo ltage V
IH_PRES
0.7 x
V
DD
V
Input Low Current I
IL_PRESVIL_PRES
= 0V 40 µA
Input High Current I
IH_PRESVIH_PRES
= V
DD
40 µA
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
DDA
_______________________________________________________________________________________ 5
DS8113
Page 6
Smart Card Interface
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING
A
ctivation T ime t
ACT
5
0 220 µs
Deactivation Time t
D
EACT
50 80 100 µs
Window Start t
3
50 130
CLK to Card Start
Time
Window End t
5
140 220
µs
PRES/PRES Debounce Tim e t
DEBOUNCE
5 8 11 ms
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD= +3.3V, V
= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
DDA
DS8113
Note 1: Operation guaranteed at -40°C and +85°C but not tested.
Note 2: IDD_IC measures the amount of current used by the DS8113 to provide the smart card current minus the load.
Note 3: Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to a logic-high.
Note 4: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum
rise and fall time is 10ns.
Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
6 _______________________________________________________________________________________
Page 7
Smart Card Interface
PIN NAME FUNCTION
1, 2
CLKDIV1,
CLKDIV2
Clock D ivid er. Determines the di vided-down input clock frequency (presented at XTAL1 or from a
crystal at X T AL1 and XTAL2) on the CLK output pin. Di viders of 1, 2, 4, and 8 are ava ilable.
3 5V/3V
5V/3V Selection Pin . A llows select ion of 5V or 3V for commu nication wit h an IC card. Log ic-high
select s 5V operation; logic-low se lect s 3V operatio n. The 1_8V pin overrides the setting on thi s pin if
active. See T able 3 for a complete descr iption of choo sing card voltages.
4 PGND Analog Ground
5, 7 CP2, CP1 Step-Up Converter Contact. Unused for the DS8113.
6 VDDA Charge Pump Supply. Must be equal to or higher than VDD. For the DS8113 thi s must be at least 5.0V.
8 VUP Charge Pump Output. Unused for the DS8113.
9 PRES
Card Presen ce Ind icator. Act ive-low card presence inputs from the DS8113 to the microcontroller.
When the presence indicator become s acti ve, a debounce tim e out begins. Aft er 8ms (typ) the OFF
signal becomes active.
10 PRES
Card Presen ce Ind icator. Act ive-high card presence inputs from the DS8113 to the microcontroller.
When the presence indicator become s acti ve, a debounce tim e out begins. Aft er 8ms (typ) the OFF
signal becomes active.
11 I/O Smart Card Data-L ine Output. Card data communication lin e, contact C7.
12, 13
AUX2,
AUX1
Smart Card Auxil iary Line (C4, C8) Output. Data line co nnected to card reader contact s C4 (AUX1)
and C8 (AUX2).
14 CGND Smart Card Ground
15 CLK Smart Card Clock. Card clock, contact C3.
16 RST Smart Card Reset . Card reset output from contact C2.
17 VCC
Smart Card Supply Voltage. Decouple to CGND (card ground) w ith 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m).
18 1 _8V
1.8V Operation Select ion. Active-high se lection for 1.8V smart card communication. An active-h igh
signal on thi s p in o verrides an y sett ing on the 5V/3V pin.
19 CMDVCC Acti vat ion Sequence Initiate. Active-low input from host.
20 RSTIN Card Reset Input. Reset input from the host.
21 VDD Supply Volt age
22 GND Digital Ground
23 OFF S tatus Output. Act ive-low interrupt output to the host. U se a 20k integrated pullup res istor to VDD.
24, 25
XTAL1,
XTAL2
Crysta l/Clock Input. Conne ct an input from an e xternal c lock to XTAL1 or conne ct a cr y stal acros s
XTAL1 and XTAL2. F or the low idle-mode current variant, an ext ernal clock must be driven o n
XTAL1.
26 I/OIN I/O Input. Host-to-interface chip data I/O line.
27, 28
AUX1IN,
AUX2IN
C4/C8 Input. Host-to-interface I/O line for aux iliary con nections to C4 and C8.
Pin Description
_______________________________________________________________________________________ 7
DS8113
Page 8
Smart Card Interface
TEMPERATURE
MONITOR
CARD VOLTAGE
GENERATOR
CLOCK
GENERATION
CONTROL
SEQUENCER
POWER-SUPPLY
SUPERVISOR
I/O TRANSCEIVER
VDD
GND
VDDA
PGND
CP1
CP2
VUP
VCC
XTAL1
XTAL2
CLKDIV1
CLKDIV2
1_8V
5V/3V
CMDVCC
RSTIN
CGND
RST
CLK
I/O
AUX1
AUX2
PRES
PRES
OFF
I/OIN
AUX1IN
AUX2IN
DS8113
VDD
ALARM
(INTERNAL SIGNAL)
POWER ON
t
W
t
W
POWER OFF
V
TH2
+ V
HYS2
V
TH2
SUPPLY DROPOUT
Detailed Description
The DS8113 is an analog front-end for communicating
with 1.8V, 3V, and 5V smart cards. It is a dual inputvoltage device, requiring one supply to match that of a
host microcontroller and a separate +5V supply for
generating correct smart card supply voltages. The
DS8113 translates all communication lines to the cor-
DS8113
rect voltage level and provides power for smart card
operation. It is a low-power device, consuming very little current in active-mode operation (during a smart
card communication session), and is suitable for use in
battery-powered devices such as laptops and PDAs,
consuming only 10nA in stop mode. See Figure 1 for a
functional diagram.
Power Supply
The DS8113 is a dual-supply device. The supply pins
for the device are VDD, GND, VDDA, and PGND. V
D
should be in the range of 2.7V to 6.0V, and is the supply for signals that interface with the host controller. It
should, therefore, be the same supply as used by the
host controller. All smart card contacts remain inactive
during power-on or power-off. The internal circuits are
kept in the reset state until VDDreaches V
TH2
+ V
HYS2
and for the duration of the internal power-on reset
pulse, tW. A deactivation sequence is executed when
VDDfalls below V
TH2
.
An internal regulator generates the 1.8V, 3V, or 5V card
supply voltage (VCC). The regulator should be supplied
separately by VDDA and PGND. VDDA should be connected to a minimum 5.0V supply in order to provide
the correct supply voltage for 5V smart cards.
Voltage Supervisor
The voltage supervisor monitors the VDDsupply. A
220µs reset pulse (tW) is used internally to keep the
device inactive during power-on or power-off of the
VDDsupply. See Figure 2.
The DS8113 card interface remains inactive no matter
the levels on the command lines until duration tWafter
VDDhas reached a level higher than V
When VDDfalls below V
, the DS8113 executes a
TH2
card deactivation sequence if its card interface is
active.
TH2
+ V
HYS2
D
.
Figure 1. Functional Diagram
Figure 2. Voltage Supervisor Behavior
8 _______________________________________________________________________________________
Page 9
Smart Card Interface
CLKDIV1 CLKDIV2 f
CLK
0 0 f
XTAL
/8
0 1 f
XTAL
/4
1 1 f
XTAL
/2
1 0 f
XTAL
OFF CMDVCC STATUS
High High Card present.
Low High Card not present.
Clock Circuitry
The card clock signal (CLK) is derived from a clock signal input to XTAL1 or from a crystal operating at up to
20MHz connected between XTAL1 and XTAL2. The
output clock frequency of CLK is selectable through
inputs CLKDIV1 and CLKDIV2. The CLK signal fre-
, f
quency can be f
Table 1 for the frequency generated on the CLK signal
X
TAL
TAL/2
X
, f
X
TAL/4
, or f
TAL/8
X
. See
given the inputs to CLKDIV1 and CLKDIV2.
Note that CLKDIV1 and CLKDIV2 must not be changed
simultaneously; a delay of 10ns minimum between
changes is needed. The minimum duration of any state
of CLK is eight periods of XTAL1.
The frequency change is synchronous: during a transition of the clock divider, no pulse is shorter than 45% of
the smallest period, and the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change
is effective for only eight periods of XTAL1 after the
command.
The f
duty factor depends on the input signal on
XTAL
XTAL1. To reach a 45% to 55% duty factor on CLK,
XTAL1 should have a 48% to 52% duty factor with transition times less than 5% of the period.
With a crystal, the duty factor on CLK can be 45% to
55% depending on the circuit layout and on the crystal
characteristics and frequency. In other cases, the duty
factor on CLK is guaranteed between 45% and 55% of
the clock period.
If the crystal oscillator is used or if the clock pulse on
XTAL1 is permanent, the clock pulse is applied to the
card as shown in the activation sequences in Figures 3
and 4. If the signal applied to XTAL1 is controlled by
the host microcontroller, the clock pulse is applied to
the card when it is sent by the system microcontroller
(after completion of the activation sequence).
Table 1. Clock Frequency Selection
I/O Transceivers
The three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
I/O and I/OIN are pulled high with an 11kΩ resistor (I/O
to VCC and I/OIN to VDD) in the inactive state. The first
side of the transceiver to receive a falling edge
becomes the master. When a falling edge is detected
(and the master is decided), the detection of falling
edges on the line of the other side is disabled; that side
then becomes a slave. After a time delay t
transistor on the slave side is turned on, thus transmit-
D(EDGE)
, an n
ting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay t
PU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high transitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
Inactive Mode
The DS8113 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.
• All card contacts are inactive (approximately 200Ω
to GND).
• Pins I/OIN, AUX1IN, and AUX2IN are in the highimpedance state (11kΩ pullup resistor to VDD).
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
• The internal oscillator is running at its low frequency.
Activation Sequence
After power-on and the reset delay, the host microcontroller can monitor card presence with signals OFF and
CMDVCC, as shown in Table 2.
DS8113
_______________________________________________________________________________________ 9
Table 2. Card Presence Indication
Page 10
Smart Card Interface
ATR
CMDVCC
RST
RSTIN
CLK
VCC
I/O
I/OIN
t
0t1t2
t
3
t
4
t5= t
ACT
If the card is in the reader (if PRES is active), the host
microcontroller can begin an activation sequence (start
a card session) by pulling
CMDVCC low. The following
events form an activation sequence (Figure 3):
CMDVCC is pulled low.
1)
2) The internal oscillator changes to high frequency (t
DS8113
3) The voltage generator is started (between t0and t1).
4) V
rises from 0 to 5V, 3V, or 1.8V with a con-
C
C
trolled slope (t2= t1+ 1.5 × T). T is 64 times the
internal oscillator period (approximately 25µs).
5) I/O, AUX1, and AUX2 are enabled (t3= t1+ 4T)
(they were previously pulled low).
6) The CLK signal is applied to the C3 contact (t
7) RST is enabled (t
= t1+ 7T).
5
To apply the clock to the card interface:
1) Set RSTIN high.
2) Set
CMDVCC low.
3) Set RSTIN low between t3and t5; CLK will now start.
4) RST stays low until t5, then RST becomes the copy
of RSTIN.
).
0
5) RSTIN has no further effect on CLK after t5.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t3(minimum
200ns after the transition on I/O, see Figure 4); after t5,
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform activation with RSTIN held permanently high.
Active Mode
).
4
When the activation sequence is completed, the
DS8113 card interface is in active mode. The host
microcontroller and the smart card exchange data on
the I/O lines.
Figure 3. Activation Sequence Using RSTIN and
10 ______________________________________________________________________________________
CMDVCC
Page 11
Smart Card Interface
ATR
CMDVCC
RST
RSTIN
CLK
VCC
I/O
I/OIN
t
0t1t2
t3t
4
t5= t
ACT
200ns
RST
CLK
VCC
CMDVCC
I/O
t
10
t
DE
t
12
t
13
t
14
t
15
DS8113
Figure 4. Activation Sequence at t
Figure 5. Deactivation Sequence
______________________________________________________________________________________ 11
3
Page 12
Smart Card Interface
Deactivation Sequence
When a session is completed, the host microcontroller
sets the
deactivation sequence and returns the card interface to
the inactive mode (Figure 5).
DS8113
CMDVCC line high to execute an automatic
1) RST goes low (t10).
2) CLK is held low (t12= t10+ 0.5 × T) where T is 64
times the period of the internal oscillator (approximately 25µs).
3) I/O, AUX1, and AUX2 are pulled low (t13= t10+ T).
4) VCCstarts to fall (t14= t10+ 1.5 × T).
5) When VCCreaches its inactive state, the deactivation sequence is complete (at tDE).
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at V
up through an 11kΩ resistor).
7) The internal oscillator returns to its lower frequency.
DD
VCCGenerator
The VCCgenerator has a capacity to supply up to
80mA continuously at 5V, 65mA at 3V, and 30mA at
1.8V. An internal overload detector triggers at approximately 120mA. Current samples to the detector are filtered. This allows spurious current pulses (with a
duration of a few µs) up to 200mA to be drawn without
causing deactivation. The average current must stay
below the specified maximum current value. To maintain VCCvoltage accuracy, a 100nF capacitor (with an
ESR < 100mΩ) should be connected to CGND and
placed near the DS8113’s VCC pin, and a 100nF or
220nF capacitor (220nF is the best choice) with the
same ESR should be connected to CGND and placed
near the smart card reader’s C1 contact.
(pulled
Fault Detection
The following fault conditions are monitored:
• Short-circuit or high current on VCC
• Removal of a card during a transaction
dropping
•V
D
D
• Card voltage generator operating out of the specified values (V
too high)
• Overheating
There are two different cases (Figure 6):
• CMDVCC High Outside a Card Session. Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The VDDsupply is
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the
ture detection is disabled because the card is not
powered up.
• CMDVCC Low Within a Card Session. Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed automatically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present). Depending on the connector’s card-present switch (normally closed or
normally open) and the mechanical characteristics
of the switch, bouncing can occur on the PRES signals at card insertion or withdrawal.
The DS8113 has a debounce feature with an 8ms typical duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
too low or current consumption
DA
D
OFF signal. Short-circuit and tempera-
12 ______________________________________________________________________________________
Page 13
Smart Card Interface
DEBOUNCE DEBOUNCE
VCC
PRES
OFF
DEACTIVATION CAUSED
BY CARDS WITHDRAWAL
DEACTIVATION CAUSED
BY SHORT CIRCUIT
CMDVCC
RST
CLK
VCC
PRES
OFF
I/O
t
10
t
DE
t
12
t
13
t
14
t
15
DS8113
Figure 6. Behavior of PRES,
Figure 7. Emergency Deactivation Sequence (Card Extraction)
OFF,CMDVCC
, and VCC
______________________________________________________________________________________ 13
Page 14
Smart Card Interface
CMDVCC
1_8V
5V/3V
STOP MODE
OFF
PRES
VCC
DEACTIVATE INTERFACE
ACTIVATE
STOP MODE
DEACTIVATE
STOP MODE
220µs DELAY
OFF FOLLOWS
PRES IN STOP MODE
OFF ASSERTED TO
WAIT FOR DELAY
8ms DEBOUNCE
Stop Mode (Low-Power Mode)
A low-power state, stop mode, can be entered by forcing the
logic-high state. Stop mode can only be entered when
the smart card interface is inactive. In stop mode all
internal analog circuits are disabled. The OFF pin follows the status of the PRES pin. To exit stop mode,
DS8113
change the state of one or more of the three control
CMDVCC, 5V/3V, and 1_8V input pins to a
pins to a logic-low. An internal 220µs (typ) power-up
delay and the 8ms PRES debounce delay are in effect
and
OFF is asserted to allow the internal circuitry to sta-
bilize. This prevents smart card access from occurring
after leaving the stop mode. Figure 8 shows the control
sequence for entering and exiting stop mode. Note that
an in-progress deactivation sequence always finishes
before the DS8113 enters low-power stop mode.
Figure 8. Stop-Mode Sequence
14 ______________________________________________________________________________________
Page 15
Smart Card Interface
VCC SELECT STOP MODE1.8V 1.8V3V3V5V
1_8V
5V/3V
CMDVCC
1_8V 5V/3V CMDVCC VCCSELECT (V) CARD INTERFACE STATUS
0 0 0 3 Activated
0 0 1 3 Inactivated
0 1 0 5 Activated
0 1 1 5 Inactivated
1 0 0 1.8 Activated
1 0 1 1.8 Inactivated
1 1 0 1.8 Reserved (Activated)
1 1 1 1.8 Not Applicable—Stop Mode
Smart Card Power Select
The DS8113 supports three smart card VCCvoltages:
1.8V, 3V, and 5V. The power select is controlled by the
1_8V and 5V/
3V signals as shown in Table 3. The 1_8V
signal has priority over 5V/3V. When 1_8V is asserted
high, 1.8V is applied to VCC when the smart card is
active. When 1_8V is deasserted, 5V/3V dictates V
power range. V
high state, and VCCis 3V if 5V/3V is pulled to a
is 5V if 5V/3V is asserted to a logic-
C
C
C
Table 3. VCCSelect and Operation Mode
logic-low state. Care must be exercised when switching
from one V
and 5V/
power selection to the other. If both 1_8V
CC
3V are high with CMDVCC high at the same
time, the DS8113 enters stop mode. To avoid accidental entry into stop mode, the state of 1_8V and 5V/
must not be changed simultaneously. A minimum delay
of 100ns should be observed between changing the
C
states of 1_8V and 5V/3V. See Figure 9 for the recommended sequence of changing the V
C
range.
C
DS8113
3V
Figure 9. Smart Card Power Select
______________________________________________________________________________________ 15
Page 16
Smart Card Interface
PART
LOW STOP-
MODE PO WER
LOW ACTIVE-
MODE PO WER
PINPACKAGE
DS8113-RNG+ Yes Yes 28 SO
Applications Information
Performance can be affected by the layout of the application. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST) and C3
(CLK) or C2 (RST) and C7 (I/O) can cause contact C2
to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
DS8113
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the
DS8113 and the connector; place the DS8113
very near to the connector; decouple the VDD and
VDDA lines separately. These lines are best positioned under the connector, connected in a star on
the main trace.
• The DS8113 and the host microcontroller must use
the same VDD supply. Pins CLKDIV1, CLKDIV2,
RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/3V,
1_8V, CMDVCC, and OFF are referenced to VDD;
if pin XTAL1 is to be driven by an external clock,
also reference this pin to VDD.
• Trace C3 (CLK) should be placed as far as possible from the other traces.
• The trace connecting CGND to C5 (GND) should
be straight (the two capacitors on C1 (VCC)
should be connected to this ground trace).
• Avoid ground loops among CGND, PGND, and
GND.
With all these layout precautions, noise should be kept
to an acceptable level and jitter on C3 (CLK) should be
less than 100ps. Reference layouts, designs, and an
evaluation kit are available on request.
Selector Guide
ote:Contact the factory for availability of other variants and
N
ackage options.
p
+Denotes a lead-free package.
Package Information
(For the latest package outline information, go to
www.maxim-ic.com/packages.)
PACKAGE TYPE DOCUMENT NO.
28 SO (300 mils)
21-0042
16 ______________________________________________________________________________________
Page 17
Smart Card Interface
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0 1/08 Initia l re lease. —
In the Recommended DC Operating Cond itions table, changed I/OIN,
AUX1IN/AUX2IN specs to reference V
D
D
rather than V
C
C
and corrected V
O
H
to µA.
5
1
2/08
In the Pin Description, removed reference s to active low from t he PRES
description.
7
Revision History
DS8113
EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accordance and for sufficient
conformance with the EMV Specifications, Version 3.1.1, as of the date of testing. EMVCo approval is not in any way an endorsement or warranty regarding
the completeness of the approval process or the functionality, quality or performance of any particular product or service. EMVCo does not warrant any
products or services provided by third parties, including, but not limited to, the producer or provider of the IFM and EMVCo approval does not under any
circumstances include or imply any product warranties from EMVCo, including, without limitation, any implied warranties of merchantability, fitness for purpose, or noninfringement, all of which are expressly disclaimed by EMVCo. All rights and remedies regarding products and services which have received
EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liability whatsoever in
connection therewith.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
____________________
17
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