Page 1
September 1999
DS78LS120
Dual Differential Line Receiver (Noise Filtering and
Fail-Safe)
General Description
The DS78LS120 is a high performance, dual differential,TTL
compatible line receiver for both balanced and unbalanced
digital data transmission. The inputs are compatible with
EIA, Federal and MIL standards.
The line receiver will discriminate a
over a common-mode range of
over a range of
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input be
open or short. Each receiver includes an optional 180Ω terminating resistor and the output gate contains a logic strobe
for time discrimination. The DS78LS120 is specified over a
−55˚C to +125˚C temperature range.
±
15V.
±
200 mV input signal
±
10V and a±300 mV signal
Connection Diagram
Input specifications meet or exceed those of the popular
DS7820 line receiver.
Features
n Meets EIA standards RS232-C, RS422 and RS423,
Federal Standards 1020, 1030 and MIL-188-114
n Input voltage range of
common-mode)
n Separate strobe input for each receiver
n 5k typical input impedance
n Optional 180Ω termination resistor
n 50mV input hysteresis
n 200mV input threshold
n Separate fail-safe mode
±
15V (differential or
DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)
Dual-In-Line-Package
DS007499-1
Top View
Order Number DS78LS120J/883 or DS78LS120W/883
See NS Package Number J16A or W16A
see RETS Data Sheet.
© 1999 National Semiconductor Corporation DS007499 www.national.com
Page 2
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage
Strobe Voltage 7V
Output Sink Current 50 mA
Storage Temperature Range −65˚C to +150˚C
±
25V
Maximum Power Dissipation at 25˚C
(Note 1) 1433 mV
Lead Temperature (Soldering, 4 sec) 260˚C
Operating Conditions
Supply Voltage (V
Temperature (T
) 4.5 5.5 V
CC
) −55 +125 ˚C
A
Common-Mode Voltage (V
Min Max Units
) −15 +15 V
CM
Electrical Characteristics (Notes 3, 4)
Symbol Parameter Conditions Min Typ Max Units
V
V
V
V
R
R
R
I
V
Differential Threshold Voltage I
TH
Differential Threshold Voltage I
TL
Differential Threshold Voltage I
TH
with Fail-Safe Offset=5V I
TL
Input Resistance −15V ≤ VCM≤ 15V, 0V ≤ VCC≤ 7V 4 5 kΩ
IN
Line Termination Resistance T
T
Offset Control Resistance T
O
Data Input Current (Unterminated) V
IND
Input Balance I
THB
(Note 6) R
V
V
I
I
I
V
V
I
Logical “1” Output Voltage I
OH
Logical “0” Output Voltage I
OL
Power Supply Current V
CC
Logical “1” Strobe Input Current V
IN (1)
Logical “0” Strobe Input Current V
IN (0)
Logical “1” Strobe Input Voltage VOL≤ 0.5, I
IH
Logical “0” Strobe Input Voltage VOH≥ 2.5V, I
IL
Output Short-Circuit Current V
OS
Note 1: Derate cavity package 9.6 mW/˚C above 25˚C.
Note 2: “Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating TemperatureRange” they
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78LS120. All typical values are for T
=
5V and V
Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 5: Only one output at a time should be shorted.
Note 6: Refer to EIA-RS422 for exact conditions.
=
0V.
CM
=
−400 µA, V
OUT
=
4 mA, V
OUT
=
−400 µA, V
OUT
=
4 mA, V
OUT
=
25˚C 100 180 300 Ω
A
=
25˚C 42 56 70 kΩ
A
=
10V 2 3.1 mA
CM
=
V
0V 0V ≤ V
CM
=
V
−10V −2 −3.1 mA
CM
=
−400 µA, V
OUT
=
500Ω
S
=
I
4 mA, V
OUT
=
R
500Ω
S
=
−400 µA, V
OUT
=
4 mA, V
OUT
=
5.5V V
CC
=
V
−0.5V, (Both Receivers) V
DIFF
=
=
=
0V, V
5.5V, V
0V, V
OUT
OUT
STROBE
STROBE
OUT
≥ 2.5V −7V ≤ VCM≤ 7V 0.06 0.2 V
OUT
≤ 0.5V −7V ≤ VCM≤7V −0.08 −0.2 V
OUT
≥ 2.5V −7V ≤ VCM≤ 7V 0.47 0.7 V
OUT
≤ 0.5V −7V ≤ VCM≤ 7V −0.2 −0.42 V
OUT
≥ 2.5V, −7V ≤ VCM7V 0.1 0.4 V
OUT
≤ 0.5V, −7V ≤ VCM≤ 7V −0.1 −0.4 V
OUT
=
1V, V
DIFF
=
−1V, V
DIFF
=
3V 1 100 µA
DIFF
=
−3V −290 −400 µA
DIFF
=
4mA 2.0 1.12 V
−15 ≤ V
−15V ≤ V
15V
=
4.5V 2.5 3 V
CC
=
4.5V 0.35 0.5 V
CC
CM
CM
≤15V 0.06 0.3 V
CM
≤
CM
≤ 7V 0 −0.5 mA
CC
=
15V 10 16 mA
=
−15V 10 16 mA
−0.08 −0.3 V
,=−400 µA 1.12 0.8 V
=
5.5V, V
CC
STROBE
=
0V,(Note 5) −30 −100 −170 mA
A
=
25˚C, V
CC
Switching Characteristics
=
V
CC
Symbol Parameter Conditions Min Typ Max Units
t
pd0(D)
t
pd1(D)
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=
5V, T
25˚C
A
Differential Input to “0” Output 38 60 ns
Differential Input to “1” Output Response Pin Open, C
=
L
15 pF, R
=
2kΩ 38 60 ns
L
Page 3
Switching Characteristics (Continued)
=
V
CC
Symbol Parameter Conditions Min Typ Max Units
t
pd0(S)
t
pd1(S)
=
5V, T
25˚C
A
Strobe Input to “0” Output 16 25 ns
Strobe Input to “1” Output 12 25 ns
AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
Includes probe and test fixture capacitance
Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).
DS007499-3
DS007499-4
Application Hints
Balanced Data Transmission
DS007499-5
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Application Hints (Continued)
Unbalanced Data Transmission
DS007499-6
Logic Level Translator
DS007499-7
The DS78LS120 may be used as a level translator to inter-
±
face between
ure, bias either input to a voltage equal to
12V MOS, ECL, TTL and CMOS. To config-
1
⁄2the voltage of
the input signal, and the other input to the driving gate.
LINE DRIVERS
Line drivers which will interface with the DS78LS120 are
listed below.
Balanced Drivers
DS26LS31: Quad RS-422 Line Driver, Dual CMOS
DS7830, DS8830: Dual TTL
DS7831, DS8831: Dual TRI-STATE TTL
DS7832, DS8832: Dual TRI-STATE TTL
DS1691A, DS3691: Quad RS-423/Dual RS-422 TTL
DS1692, DS3692: Quad RS-423/Dual TRI-STATE RS-422
TTL
DS3487: Quad TRI-STATE RS-422
Unbalanced Drivers
DS1488: Quad RS-232
DS75150: Dual RS-232
RESPONSE CONTROL AND HYSTERESIS
In unbalanced (RS-232/RS-423) applications it is recommended that the rise time and fall time of the line driver be
controlled to reduce cross-talk. Elimination of switching
noise is accomplished in the DS78LS120 by the 50 mV of
hysteresis incorporated in the output gate. This eliminates
the oscillations which may appear in a line receiver due to
the input signal slowly varying about the threshold level for
extended periods of time.
High frequency noise which is superimposed on the input
signal which may exceed 50 mV can be reduced in amplitude by filtering the device input. On the DS78LS120, a high
impedance response control pin in the input amplifier is
DS007499-8
available to filter the input signal without affecting the termination impedance of the transmission line. Noise pulse width
rejection vs the value of the response control capacitor is
shown in
Figure 1
and
Figure 2
. This combination of filters
followed by hysteresis will optimize performance in a worse
case noise environment.
DS007499-9
FIGURE 1. Noise Pulse Width vs
Response Control Capacitor
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Page 5
Application Hints (Continued)
DS007499-10
FIGURE 2.
TRANSMISSION LINE TERMINATION
On a transmission line which is electrically long, it is advisable to terminate the line in its characteristic impedance to
prevent signal reflection and its associated noise/cross-talk.
A 180Ω termination resistor is provided in the DS78LS120
line receiver. To use the termination resistor, connect pins 2
and 3 together and pins 13 and 14 together. The 180Ω resistor provides a good compromise between line reflections,
power dissipation in the driver, and IR drop in the transmission line. If power dissipation and IR drop are still a concern,
a capacitor may be connected in series with the resistor to
minimize power loss.
The value of the capacitor is recommended to be the line
length (time) divided by 3 times the resistor value. Example:
if the transmission line is 1,000 feet long, (approximately
1000 ns), and the termination resistor value is 180Ω, the capacitor value should be 1852 pF. For additional application
details, refer to application notes AN-22 and AN-108.
FAIL-SAFE OPERATION
Communication systems require elements of a system to detect the presence of signals in the transmission lines, and it
is desirable to have the system shut-down in a fail-safe
mode if the transmission line is open or shorted. To facilitate
the detection of input opens or shorts, the DS78LS120 incorporates an input threshold voltage offset. This feature will
force the line receiver to a specific logic state if presence of
either fault is a condition.
Given that the receiver input threshold is
signal greater than
specific logic state. When the offset control input (pins 1 and
15) is connected to V
from 200 mV to 700 mV, referred to the non-inverting input,
±
200 mV insures the receiver will be in a
=
5V,the input thresholds are offset
CC
±
200 mV, an input
or −200 mV to −700 mV, referred to the inverting input.
Therefore, if the input is open or shorted, the input will be
greater than the input threshold and the receiver will remain
in a specified logic state.
The input circuit of the receiver consists of a 5k resistor terminated to ground through 120Ω on both inputs. This network acts as an attenuator, and permits operation with
common-mode input voltages greater than
±
15V.The offset
control input is actually another input to the attenuator, but its
resistor value is 56k. The offset control input is connected to
the inverting input side of the attenuator, and the input voltage to the amplifier is the sum of the inverting input plus 0.09
times the voltage on the offset control input. When the offset
control input is connected to 5V the input amplifier will see
V
IN(INVERTING)
trol input is connected to 10V. The offset control input will not
+0.45V or V
IN(INVERTING)
+0.9V when the con-
significantly affect the differential performance of the receiver over its common-mode operating range, and will not
change the input impedance balance of the receiver.
It is recommended that the receiver be terminated (500Ω or
less) to insure it will detect an open circuit in the presence of
noise.
The offset control can be used to insure fail-safe operation
for unbalanced interface (RS-423) or for balanced interface
(RS-422) operation.
For unbalanced operation, the receiver would be in an indeterminate logic state if the offset control input was open.
Connecting the fail-safe offset pin to 5V, offsets the receiver
threshold to 0.45V. The output is forced to a logic zero state
if the input is open or shorted.
Unbalanced RS-423 and RS-232 Fail-Safe
DS007499-11
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Application Hints (Continued)
DS007499-12
Balanced RS-422 Fail-Safe
For balanced operation with inputs open or shorted, receiver
C will be in an indeterminate logic state. Receivers A and B
will be in a logic zero state allowing the NOR gate to detect
the open or short condition. The strobe will disable receivers
A and B and may therefore be used to sample the fail-safe
detector.Another method of fail-safe detection consists of filtering the output of NOR gate D so it would not indicate a
fault condition when receiver inputs pass through the threshold region, generating an output transient.
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DS007499-13
DS007499-14
In a communications system, only the control signals are required to detect input fault conditions. Advantages of a balanced data transmission system over an unbalanced transmission system are:
1. High noise immunity
2. High data ratio
3. Long line lengths
Page 7
Application Hints (Continued)
(For Balanced Fail-Safe)
Input Strobe A-Out B-Out C-Out D-Out
0 1 0100
1 1 1010
X 1 00X1
0 0 1100
1 0 1100
X 0 1100
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Schematic Diagram
DS007499-2
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Page 9
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DS78LS120J/883
NS Package Number J16A
Ceramic Dual-In-Line Package (W)
Order Number DS78LS120W/883
NS Package Number W16A
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Page 10
Notes
LIFE SUPPORT POLICY
DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
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Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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