Datasheet DS75325N Datasheet (NSC)

DS75325
Memory Drivers

General Description

The DS75325 is a monolithic memory driver which features
high current outputs as well as internal decoding of logic
inputs. This circuit is designed for use with magnetic memo­ries.

The circuit contains two 600 mA sink-switch pairs and two
600 mA source-switch pairs. Inputs A and B determine
source selection while the source strobe (S1) allows the
selected source turn on. In the same manner, inputs C and
D determine sink selection while the sink strobe (S2) allows
the selected sink turn on.

Sink-output collectors feature an internal pull-up resistor in
parallel with a clamping diode connected to V
tects the outputs from voltage surges associated with
switching inductive loads.

The source stage features Node R which allows extreme
flexibility in source current selection by controlling the
amount of base drive to each source transistor. This method
of setting the base drive brings the power associated with
the resistor outside the package thereby allowing the circuit

. This pro-

CC2

June 1992

to operate at higher source currents for a given junction
temperature. If this method of source current setting is not
desired, then Nodes R and R
activating an internal resistor connected from V
R. This provides adequate base drive for source currents up
to 375 mA with V

CC2

e

can be shorted externally,

INT

15V or 600 mA with V

CC2

CC2

to Node

e

24V.

Features

Y

600 mA output capability

Y

24V output capability

Y

Dual sink and dual source outputs

Y

Fast switching times

Y

Source base drive externally adjustable

Y

Input clamping diodes

Y

TTL compatible

DS75325 Memory Drivers

Connection Diagram

Dual-In-Line Package

Top View

Order Number DS75325N

See NS Package Number N14A

TL/F/9755– 2

Truth Table

Address Inputs Strobe Inputs Outputs

Source Sink Source Sink Source Sink

A B C D S1 S2 W X Y Z

L H X X L H ON OFF OFF OFF
H L X X L H OFF ON OFF OFF
X X L H H L OFF OFF ON OFF
X X H L H L OFF OFF OFF ON
X X X X H H OFF OFF OFF OFF
H H H H X X OFF OFF OFF OFF

HeHigh Level, LeLow Level, XeIrrelevant

Note: Not more than one output is to be on at any one time.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/F/9755

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage V

Supply Voltage V

(Note 5) 7V

CC1

(Note 5) 25V

CC2

Input Voltage (Any Address or Strobe Input) 5.5V

Maximum Power Dissipation* at 25

Cavity Package 1509 mW

C

§

Molded Package 1476 mW

*Derate Cavity Package 10.1 mW/§C above 25§C; derate molded package

C above 25§C.

11.8 mW/

§

Storage Temperature Range

Lead Temperature

(Soldering, 10 seconds) 300

Operating Conditions

Temperature (T

DS75325 0

Min Max Units

)

A

b

65§Ctoa150§C

a

70

C

§

C

§

Electrical Characteristics (Notes 2 and 3)

Symbol Parameter Conditions Min Typ Max Units

V

V

V

I

OFF

V

V

V

I

I

I

IH

I

IL

I

CC OFF

I

CC1

I

CC2

High Level Input Voltage

IH

Low Level Input Voltage

IL

Input Clamp Voltage V

I

Source Collectors Terminal V
‘‘Off’’ State Current

(Figures 1

(Figures 3

e

CC1

e

T

25§C

A

e

CC1

(Figure 1)

and

and

4.5V, V

(Figure 5)

4.5V, V

2)

2V

4)

CC2

CC2

e

e

eb

24V, I

12 mA

IN

b

24V Full Range DS55325 500 mA

DS75325 200 mA

e

T

25§C DS55325 3 150 mA

A

0.8 V

1.3b1.7 V

DS75325 3 200 mA

High Level Sink Output Voltage V

OH

Saturation Voltage Source V

SAT

Outputs R

Saturation Voltage V

SAT

Sink Outputs R

Input Current at Maximum V
Input Voltage V

High Level Input Current V

Low Level Input Current V

Supply Current, All Sources V
and Sinks ‘‘Off’’

Supply Current from V
Either Sink ‘‘On’’ T

Supply Current from V
Either Source ‘‘On’’ T

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.

Note 2: Unless otherwise specified min/max limits apply across the
the DS75325. All typical values are at T

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Note 4: Only one output at a time should be shorted.

Note 5: Voltage values are with respect to network ground terminal.

Note 6: These parameters must be measured using pulse techniques. t

,V

CC1

CC2,

e

25§C.

A

e

4.5V, V

CC1

e

4.5V, V

CC1

e

24X,

L

& b

I

SOURCE

(Figure 3)

I
(Notes 4 and 6)

V

V

T

V

CC1
L

SINK

CC1
I

CC1
I

CC1
I

CC1

A

CC1
A

CC1
A

e

e

e

e

e

e

e

(Notes 4 and 6)

e

4.5V, V

24X,

&

600 mA

e

5.5V, V

5.5V

(Figure 5)

e

5.5V, V

2.4V

(Figure 5)

e

5.5V, V

0.4V

(Figure 5)

e

5.5V, V

25§C

e

5.5V, V

25§C

e

5.5V, V

25§C

b

e

24V, I

CC2

e

15V, Full Range

CC2

600 mA

e

15V, Full Range

CC2

(Figure 4)

e

24V, Address Inputs 1 mA

CC2

e

24V, Address Inputs 3 40 mA

CC2

e

24V, Address Inputs

CC2

e

24V, V

CC2

(Figure 6)

e

24V, I

CC2

(Figure 7)

e

24V, I

CC2

(Figure 8)

55§Ctoa125§C temperature range for the DS55325 and across the 0§Ctoa70§C range for

e

200 ms, duty cycles2%.

W

e

0mA

OUT

(Figure 2)

19 23 V

0.9 V

e

25§C DS55325 0.43 0.7 V

T

A

DS75325 0.43 0.75 V

0.9 V

e

T

25§C DS55325 0.43 0.7 V

A

DS75325 0.43 0.75 V

Strobe Inputs 2 mA

Strobe Inputs 6 80 mA

b1b

1.6 mA

Strobe Inputs

CC1

V

CC2

e

50 mA,

SINK

eb

SOURCE

50 mA

b2b

3.2 mA

14 22 mA

7.5 20 mA

55 70 mA

32 50 mA

2

Switching Characteristics V

CC1

e

5V, T

e

25§C

A

Symbol Parameter Conditions Min Typ Max Units

t

PLH

t

PHL

t

TLH

t

THL

t

S

Propagation Delay Time, V
Low-to-High Level Output C

Propagation Delay Time, V
High-to-Low Level Output C

Transition Time, C
Low-to-High Level Output R

Transition Time, C
High-to-Low Level Output R

Storage Time, Sink Outputs V

e

CC2

e

25 pF

L

e

CC2

e

25 pF

L

e

25 pF Source Outputs, V

L

e

25 pF Source Outputs, V

L

e

CC2

15V, R

(Figure 9)

15V, R

(Figure 9)

15V, R

e

24X, Source Collectors 25 50 ns

L

Sink Outputs 20 45 ns

e

24X, Source Collectors 25 50 ns

L

Sink Outputs 20 45 ns

e

20V,

L

e

24X,C

e

1kX

L

Sink Outputs, V

e

R

24X

L

e

1kX

L

Sink Outputs, V

e

R

24X

L

e

25 pF

L

(Figure 9)

CC2

(Figure 10)

CC2

(Figure 9)

CC2

(Figure 10)

CC2

(Figure 9)

e

15V,

e

20V,

e

15V,

55 ns

715ns

7ns

920ns

15 30 ns

DC Test Circuits

Test Table

ABS1

GND GND 2V

2V 2V GND

FIGURE 1. I

OFF

3

TL/F/9755– 3

DC Test Circuits (Continued)

FIGURE 2. VIHand V

TL/F/9755– 4

OH

Test Table

CDS2Y Z

2V 4.5V GND VOHOPEN

GND 4.5V 2V VOHOPEN

4.5V 2V GND OPEN V

4.5V GND 2V OPEN V

OH

OH

Note 1:

Figure 3

and4parameters must be measured using pulse techniques, t

FIGURE 3. VILand Source V

4

TL/F/9755– 5

SAT

Test Table

ABS1W X

0.8V 4.5V 0.8V GND OPEN

4.5V 0.8V 0.8V OPEN GND

e

200 ms, duty cycles2%.

W

DC Test Circuits (Continued)

Note 1:

Figure 3

and4parameters must be measured using pulse techniques, t

W

Test Table

CDS2 Y Z

0.8V 4.5V 0.8V R

4.5V 0.8V 0.8V OPEN R

FIGURE 4. VILand Sink V

OPEN

L

L

SAT

e

200 ms, duty cycles2%.

TL/F/9755– 6

5

DC Test Circuits (Continued)

I

I,IIH

e

Apply V
Measure I

Apply V
Measure I

5.5V

I

I

e

2.4V

I

IH

Ground Apply 5.5V

A S1 B, C, S2, D

S1 A, B C, S2, D

B S1 A, C, S2, D

C S2 A, S1, B, D

S2 C, D A, S1, B

D S2 A, S1, B, C

Test Tables

FIGURE 5. VI,II,IIHand I

VI,I

IL

e

Apply V
Measure I

Apply I
Measure V

I

eb

I

0.4V

IL

10 mA

I

A S1, B, C, S2, D

S1 A, B, C, S2, D

B A, S1, C, S2, D

C A, S1, B, S2, D

S2 A, S1, B, C, D

D A, S1, B, C, S2

IL

TL/F/9755– 7

Apply 5.5V

6

DC Test Circuits (Continued)

FIGURE 6. I

CC1 (OFF)

and I

CC2 (OFF)

TL/F/9755– 8

7

DC Test Circuits (Continued)

Test Table

CDS2Y Z

GND 5V GND I

5V GND GND OPEN I

FIGURE 7. I

, Either Sink On

CC1

SINK

OPEN

SINK

TL/F/9755– 9

8

DC Test Circuits (Continued)

Test Table

ABS1

GND 5V GND

5V GND GND

FIGURE 8. I

, Either Source On

CC2

TL/F/9755– 10

9

DC Test Circuits (Continued)

Note 1: The pulse generator has the following characteristics: Z

Note 2: C

includes probe and jig capacitance.

L

Parameter Output Under Test Input Connect to 5V

t

and t

PLH

PHL

t

, Sink Output Y C and S2 A, B, D and S1

PLH,tPHL

t

TLH,tTHL

and t

Source Collectors A and S1 B, C, D and S2

S

Sink Output Z D and S2 A, B, C and S1

e

50X, duty cycles1%.

OUT

Voltage Waveforms

Test Table

B and S1 A, C, D and S2

FIGURE 9. Switching Times

10

TL/F/9755– 11

TL/F/9755– 12

DC Test Circuits (Continued)

Note 1: The pulse generator has the following characteristics: Z

Note 2: C

includes probe and jig capacitance.

L

e

50X, duty cycles1%.

OUT

TL/F/9755– 13

Voltage Waveforms

Test Table

Parameter Output Under Test Input Connect to 5V

t

TLH

and t

Source Output W A and S1 B, C, D and S2

THL

Source Output X B and S1 A, C, D and S2

FIGURE 10. Transition Times of Source Outputs

11

TL/F/9755– 14

Schematic Diagram

TL/F/9755– 1

12

Applications

EXTERNAL RESISTOR CALCULATION

A typical magnetic-memory word drive requirement is shown
in

Figure 11

delivers load current (I
other DS75325 sinks this current.

The value of the external pull-up resistor (R
lar memory application may be determined using the follow­ing equation:

where: R

V

CC2(Min)

is the source output voltage in volts with respect to ground,
I

is in mA.

L

The power dissipated in resistor R
pulse duration is calculated using Equation 2.

where: P

. A source-output transistor of one DS75325

). The sink-output transistor of an-

L

) for a particu-

ext

b

b

16[V

R

ext

e

ext

is in kX,

CC2(Min)

b

I

1.6[V

L

CC2(Min)

is the lowest expected value of V

ext

I

L

Rext

P

Rext

is in mW.

&

[

V

16

CC2(Min)

b

]

V

2.2

S

b

b

]

V

2.9

S

in volts, V

CC2

during the load current

b

]

V

2

S

After solving for R
current (I

CS

, the magnitude of the source collector

ext

) is determined from Equation 3.

CS

&

0.94 I

L

where: ICSis in mA.

As an example, let V
of 500 mA flows. Using Equation 1:

16 (20b3b2.2)

e

R

ext

(1)

and from Equation 2:

S

The amount of the memory system current source (I

500b1.6 (20b3b2.9)

500

&

P

Rext

16

CC2(Min)

[

20

e

b3b

20V and V

&

]

2

470 mW

L

e

from Equation 3 is:

&

I

0.94 (500)&470 mA

CS

In this example the regulated source-output transistor base
current through the external pull-up resistor (R

(2)

source gate is approximately 30 mA. This current and I
comprise IL.

e

3V while I

0.5 kX

ext

(3)I

CS

) and the

CS

L

)

Note 1: For clarity, partial logic diagrams of two DS55325s are shown.

Note 2: Source and sink shown are in different packages.

FIGURE 11. Typical Application Data

TL/F/9755– 15

13

Physical Dimensions inches (millimeters) (Continued)

DS75325 Memory Drivers

Molded Dual-In-Line Package (N)

Order Number DS75325N

NS Package Number N14A

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SEMICONDUCTOR CORPORATION. As used herein:

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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