Page 1
PRELIMINARY
May 9, 2008
DS32EL0124 DS32ELX0124
125 MHz — 312.5 MHz Deserializer with DDR LVDS Parallel
Interface
DS32EL0124/DS32ELX0124 125 — 312.5 MHz Deserializer with DDR LVDS Parallel Interface
General Description
The DS32EL0124/DS32ELX0124 integrates clock and data
recovery modules for high-speed serial communication over
FR-4 printed circuit board backplanes, balanced cables, and
optical fiber. This easy-to-use chipset integrates advanced
signal and clock conditioning functions, with an FPGA friendly
interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125
Gbps of high speed serial data to 5 LVDS outputs without the
need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers
without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA
I/O pins, board trace count and alleviates EMI issues, when
compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
Applications
Imaging: Industrial, Medical Security, Printers
■
Displays: LED walls, Commercial
■
Video Transport
■
Communication Systems
■
Test and Measurement
■
Industrial Bus
■
Features
5-bit LVDS parallel data interface
■
Programmable Receive Equalization
■
Selectable DC-balance decoder
■
Selectable De-scrambler
■
Remote Sense for automatic detection and negotiation of
■
link status
No external receiver reference clock required
■
LVDS parallel interface
■
Programmable LVDS output clock delay
■
Supports output data-valid signaling
■
Supports keep-alive clock output
■
On chip LC VCOs
■
Redundant serial input (ELX device only)
■
Retimed serial output (ELX device only)
■
Configurable PLL loop bandwidth
■
Configurable via SMBus
■
Loss of lock and error reporting
■
48-pin LLP package with exposed DAP
■
Key Specifications
1.25 to 3.125 Gbps serial data rate
■
125 to 312.5 MHz DDR parallel clock
■
-40° to +85°C temperature range
■
> 8 kV ESD (HBM) protection
■
High Jitter Tolerance TBD
■
Low Jitter Transfer TBD
■
Typical Application
30043101
© 2008 National Semiconductor Corporation 300431 www.national.com
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Pin Diagrams
DS32EL0124/DS32ELX0124
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30043102
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DS32EL0124/DS32ELX0124
30043103
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Pin Descriptions
Pin Name Pin Number I/O, Type Description
VDD33 1, 15, 18, 35 I, VDD 3.3V supply
VDD25 7, 25, 35 I, VDD 2.5V supply
VDD_PLL 28 I, VDD 3.3V supply
LF_CP 27 Analog Loop filter capacitor connection
LF_REF 26 Analog Loop filter ground reference
Exposed Pad 49 GND Exposed Pad must be connected to GND by 9 vias.
CML I/O
DS32EL0124/DS32ELX0124
RxIN0+
RxIN0-
RxIN1+
RxIN1-
TxOUT+
TxOUT-
LVDS Parallel Data Bus
RxCLKOUT+
RxCLKOUT-3738
RxOUT[0:4]+/- 39, 40, 41, 42, 43, 44, 45,
Control Pins
LT_EN 2 I, LVCMOS DS32ELX0124 only. When held high, retimed serialized high speed
RX_MUX_SEL 12 I, LVCMOS DS32ELX0124 only. RX_MUX_SEL selects the input of the deserializer.
VOD_CTRL 14 I, LVCMOS DS32ELX0124 only. VOD control. The deserializer loop through output
DC_B
RS
RESET 30 I, LVCMOS Reset pin. When held low, reset the device.
LOCK 31 O, LVCMOS Lock indication output. pin goes low when the deserializer is locked to the
SMBus
SCK I, SMBus 33 SMBus compatible clock.
SDA I/O, SMBus 32 SMBus compatible data line.
SMB_CS I, SMBus 34 SMBus chip select. When held high, SMBus management control is
Other
GPIO0 3 I/O, LVCMOS Software configurable IO pins.
GPIO1 4 I/O, LVCMOS Software configurable IO pins.
GPIO2 11 I/O, LVCMOS Software configurable IO pins.
16
17
19
20
21
22
46, 47, 48
5
6
I, CML Non-inverting and inverting high speed CML differential inputs of the
deserializer. These inputs are internally terminated.
I, CML DS32ELX0124 only. Non-inverting and inverting high speed CML
differential inputs of the deserializer. These inputs are internally
terminated.
O, CML DS32ELX0124 only. Retimed serialized high speed output. Non-inverting
and inverting speed CML differential outputs of the deserializer. These
outputs are internally terminated.
O, LVDS Deserializer output clock. RxCLKOUT+/- are the non-inverting and
inverting LVDS recovered clock output pins.
O, LVDS Deserializer output data. RxOUT[0:4]+/- are the non-inverting and
inverting LVDS deserialized output data pins.
output is enabled.
0 = RxIN0+/- selected
1 = RxIN1+/- selected
amplitude can be adjusted by connecting this pin to a pull-down resistor.
The value of the pull-down resistor determines the VOD. Use the following
equation to determine the value of the pull-down resistor.
I, LVCMOS DC-balance and Remote Sense pins. See Application section for device
behavior.
0 = Device Reset
1 = Normal operation
incoming data stream and begins to output data and clock on RxOUT and
RxCLKOUT respectively.
0 = Deserializer locked
1 = Deserializer not locked
enabled.
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DS32EL0124/DS32ELX0124
NC
2 ,8, 9, 10, 12, 13, 14, 19,
20, 21, 22, 23, 24, 29
8, 9, 10, 13, 23, 24, 29 Misc No Connect, for DS32ELX0124
Misc. No Connect, for DS32EL0124
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Supply Voltage (V
LVCMOS Input Voltage −0.3V to (V
LVCMOS Output Voltage -0.3V to (V
CML Input/Output Voltage -0.3V to 3.6V
LVDS Output Voltage -0.3V to +3.6V
DS32EL0124/DS32ELX0124
Junction Temperature +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Package Thermal Resistance
θ
JA
ESD Susceptibility
HBM
DD33
DD25
)
)
−0.3V to +4V
-0.3V to +3.0V
DD33
DD33
+ 0.3V)
+ 0.3V)
+25.0°C/W
≥8 kV
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (V
Supply Voltage (V
Supply Noise Amplitude
from 10 Hz to 50 MHz
Ambient Temperature (TA) −40 +25 +85 °C
) 3.135 3.3 3.485 V
DD33
) 2.375 2.5 2.625 V
DD25
100 mV
Electrical and Timing Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS ELECTRICAL SPECIFICATIONS
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
SMBus ELECTRICAL SPECIFICATIONS
V
SIL
V
SIH
I
SPULLUP
V
SDD
I
SLEAKB
I
SLEAKP
C
SI
R
STERM
SMBus TIMING SPECIFICATIONS
f
SMB
t
BUF
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
HIGH
High Level Input Voltage 2.0 V
DD
Low Level Input Voltage GND 0.8 V
High Level Output Voltage IOH = -2mA 2.7 3.3 V
Low Level Output Voltage IOL = 2mA 0.3V V
Input Clamp Voltage ICL = −18 mA -0.9 −1.5 V
Input Current VIN = 0.4V, 2.5V, or V
Output Short Circuit Current V
OUT
= 0V
DD33
-35 1 35
TBD V
(Note 5)
Data, Clock Input Low Voltage 0.8 V
Data, Clock Input High Voltage 2.1 V
SDD
Current through pull-up resistor or current source 4 mA
Nominal Bus Voltage 2.375 3.6 V
Input Leakage Per Bus Segment ±200 µA
Input Leakage Per Pin ±10 µA
Capacitance for SDA and SCK 10 pF
SMBus Termination Resistor Value V
= 3.3V 1000
SDD
Bus Operating Frequency 10 100 kHz
Bus free time between top and start condition 4.7
Hold time after (repeated) start condition. After this
At I
= MAX 4.0 µs
SPULLUP
period, the first clock is generated
Repeated Start Condition Setup Time 4.7 µs
Data Hold Time 300 ns
Data Setup Time 250 ns
Clock Low Time 4.7 µs
Clock High Time 4.0 50 µs
P-P
V
μA
V
Ω
μs
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Symbol Parameter Conditions Min Typ Max Units
t
F
t
R
t
SU:CS
t
POR
Clock/Data Rise Time 20% to 80% 300 ns
Clock/Data Rise Time 1000 ns
SMB_CS Setup Time 30 ns
Time in which the device must be operational after
500 ms
power on
LVDS ELECTRICAL SPECIFICATIONS
R
I
OS
V
ΔV
V
ΔV
I
OS
OUT
OD
OS
Output Termination Resistor Between OUT+ and OUT- 85 100 115
Output Short Circuit Current
Differential Output Voltage
V
= 0V, RL = 100Ω
OUT
RL = 100Ω
Changes in VOD between complimentary output
OD
states
Offset Voltage
Change in VOS between complimentary states 35 mV
OS
Output Short Circuit Current
V
= 0V, RL = 100Ω
OUT
TBD
230 310 mV
35 mV
1.125 1.25 1.375 V
50 mA
Ω
LVDS TIMING SPECIFICATIONS
t
ROTR
t
ROTF
t
ROCP
t
RODC
t
RBIT
t
ROSC
t
ROHC
t
ROJD
t
ROJR
t
ROJT
t
RD
t
RPLLS
t
RLAPL
t
RLA
t
LVSK
LVDS low-to-high transition time 300 ps
LVDS high-to-low transition time 300 ps
LVDS output clock period 2T ns
RxCLKOUT Duty Cycle 45 50 55 %
LVDS output bit width TBD
RxOUT Setup to RxCLKOUT OUT 200 ps
RxOUT Hold to RxCLKOUT OUT 200 ps
LVDS Output Deterministic Jitter TBD
LVDS Output Random Jitter 2.5 ps
Peak-to-Peak LVDS Output Jitter TBD
Deserializer propagation delay – Latency TBD
Deserializer phase lock loop set
TBD
Deserializer Link Acquisition After PLL Lock. TBD
Deserializer Lock Time TBD
LVDS Output Skew LVDS Differential Output Skew
20 ps
between + and - pins
CML INPUT TIMING SPECIFICATIONS
EQDJ Residual deterministic jitter at EQ Output TBD
TOL
Serial Input Jitter Tolerance TBD
JIT
CML INPUT ELECTRICAL SPECIFICATIONS
V
V
I
IN
R
ΔR
ID
IN
IT
Differential input voltage TBD
Single ended input voltage TBD
Input Current TBD
Input Termination TBD
Mismatch in input terminations TBD
IT
CML RETIMED LOOP THROUGH OUTPUT ELECTRICAL SPECIFICATIONS, DS32ELX0124 ONLY
V
R
ΔR
LTOD
LTOT
Output differential voltage TBD
Output termination TBD
Mismatch in output termination resistors TBD
LTOT
CML RETIMED LOOP THROUGH OUTPUT TIMING SPECIFICATIONS, DS32ELX0124 ONLY
t
JIT
t
OS
Additive Output Jitter TBD
Output Overshoot TBD
DS32EL0124/DS32ELX0124
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Symbol Parameter Conditions Min Typ Max Units
t
LTR
Retimed output driver differential low to high
TBD
transition time
t
LTF
Retimed output driver differential high to low
TBD
transition time
t
LTRFMM
t
LTDE
DS32EL0124/DS32ELX0124
Mismatch in Rise/Fall Time TBD
Retimed driver de-emphasis width TBD
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical and Timing Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 4: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 5: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 6: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
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Timing Diagrams
DS32EL0124/DS32ELX0124
30043106
FIGURE 1. SMBus Timing Parameters
30043110
FIGURE 2. LVDS Output Transition Time
FIGURE 3. Deserializer (LVDS Interface) Setup/Hold and High/Low Times
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30043111
Page 10
DS32EL0124/DS32ELX0124
30043114
FIGURE 4. Reset to Lock Time
30043113
FIGURE 5. Deserializer Propagation Delay
FIGURE 6. CML to LVDS Bit Map
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30043104
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DS32EL0124/DS32ELX0124
Functional Description
POWER SUPPLIES
The DS32EL0124 and DS32ELX0124 have several power
supply pins, at 2.5V as well as 3.3V. It is important that these
pins all be connected and properly bypassed. Bypassing
should consist of parallel 4.7μF and 0.1μF capacitors as a
minimum, with a 0.1μF capacitor on each power pin. A 22 μF
capacitor is required on the VDDPLL pin which is connected
to the 3.3V rail.
These devices have a large contact in the center on the bottom of the package. This contact must be connected to the
system GND as it is the major ground connection for the device.
POWER UP
It is recommended, although not necessary, to bring up the
3.3V power supply before the 2.5V supply. If the 2.5V supply
is powered up first, an initial current draw of approximately
600mA from the 2.5V rail may occur before settling to its final
value. Regardless of the sequence, both power rails should
monotonically ramp up to their final values.
POWER MANAGEMENT
These devices have two methods to reduce power consumption. To enter the first power save mode, the on board host
FPGA or controlling device can cease to output the DDR
transmit clock. To further reduce power, a write to the power
down register will put the device in its lowest power mode.
RESET
There are three ways to reset these devices. A reset occurs
automatically during power-up. The device can also be reset
by pulling the RESET
when the pin is driven high again. The device can also be
reset by writing to the reset register. This reset will put all of
the register values back to their default values, except it will
not affect the address register value if the SMBus default address has been changed.
LVDS OUTPUTS
The DS32EL0124 and DS32ELX0124 has standard LVDS
outputs, compatible with ANSI/TIA/EIA-644. It is recommended that the PCB trace between the FPGA and the deserializer
output be no more than 40-inches. Longer PCB traces may
introduce signal degradation as well as channel skew which
could cause serialization errors. The connection between the
host and the DS32EL0124 or DS32ELX0124 should be over
a controlled impedance transmission line with impedance that
pin low, with normal operation resuming
matches the termination resistor – usually 100Ω. Setup and
hold times are specified in the LVDS Switching Characteristics table, however the clock delay can be adjusted by writing
to register 30’h.
LOOP FILTER
The DS32EL0124 and DSELX0124 have an internal clock
data recovery module (CDR), which is used to recover the
input serial data. The loop filter for this CDR is external, and
for optimum results, a 30nF capacitor should be connected
between pins 26 and 27. See the Typical Interface Circuit
(Figure 11).
REMOTE SENSE
The remote sense feature can be used when a DS32EL0421
or DS32ELX0421 serializer is directly connected to a
DS32EL0124 or DS32ELX0124 deserializer. Active components in the signal path between the serializer and the deserializer may interfere with the back channel signaling of the
devices.
When remote sense is enabled, the deserializer will cycle
through five states to successfully establish a link and align
the data. The state diagram for the deserialiezr is shown in
Figure 7. The deserialzer will remain in the low power IDLE
state until it receives an input signal. Once the CDR of the
deserializer has locked to the input clock, the device will enter
the LINK DETECT state. While in this state, the serializer will
monitor the line to see if the deserializer is present. If a deserializer is detected the serializer will enter the LINK ACQUISITION state. The serializer will transmit the entire
training pattern and then enter the NORMAL state. If the deserializer is unable to successfully lock or maintain lock, it will
break the link sending the serializer back to the IDLE or LINK
DETECT states.
DC-BALANCE DECODER
The DS32EL0124 and DS32ELX0124 have a built-in DC-balance decoder to support AC-coupled applications. When enabled, the output signal RxOUT4+/-, is treated as a data valid
bit. If RxOUT+/- is low, then the data output from RxOUT0RxOUT3 has been successfully decoded using the 8b/10b
coding scheme. If RxOUT4+/- is high and the outputs RxOUT0 -RxOUT3 are high then an invalid 8b/10b code was
received, signifying a bit error. If RxOUT4+/- is high and the
outputs RxOUT0 -RxOUT3 are low then an idle character has
been received. The default idle character is a K28.5 code. In
order to properly receive other Kcodes, they must first be programmed into the deserializer via the SMBus.
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DS32EL0124/DS32ELX0124
30043115
FIGURE 7. Deserializer State Diagram
DESCRAMBLER
If the descrambler is enabled, the raw or DC balanced serialized data is descrambled after the CDR to properly decode
incoming data. Using the scrambler/descrambler helps to
lower EMI emissions by spreading the spectrum of the data.
Scrambling also creates transitions for a deserializer’s CDR
to properly lock onto.
The scrambler is enabled or disabled by default depending
on how the DC_B
and RS pins are configured. To override
the default scrambler setting two register writes must be performed. First, write to register XX’h and set bit X to unlock the
descrambler register. Next write to register XX’h and change
bit X to the desired value.
CML INPUT INTERFACING
The DS32ELX0124 has two inputs to support redundancy
and failover applications. Either input can be selected by using the RX_MUX_SEL pin or internal control registers.
Whichever input is selected will be routed to the CDR of the
deserializer. Only one input may be selected at a time.
The input stage is self-biased and does not need any external
bias circuitry. The DS32EL0124 and DS32ELX0124 include
integrated input termination resistors. These deserializers also support a wide common mode input from 50mV to Vcc 50mV and can be DC-coupled where there is no significant
Ground potential difference between the interfacing systems.
The serial inputs also provides input equalization control in
order to compensate for loss from the media. The level of
equalization is controlled by the SMBus interface. For the
DS32ELX0124, each input can have its own independent
equalizer settings.
It is recommended to use RxIN0+/- as the primary input for
system that utilze the retimed loop through driver of the
DS32ELX0124. When interfacing to RxIN1+/- and transmitting with the loop through driver on TxOUT+/-, it is important
to follow good layout practices as described in the layout
guidelines section and in the LVDS Owner’s Manual. Poor
layout techniques can result in excessive cross talk coupled
into RxIN1.
CML OUTPUT INTERFACING (DS32ELX0124 ONLY)
The retimed loop through serial outputs of the DS32ELX0124
provide low-skew differential signals. Internal resistors connected from TxOUT+ and TxOUT- to VDD25 terminate the
outputs. The output level can be programmed by adjusting the
pull-down resistor to the VOD_CTRL pin. The output terminations can also be programmed to be either 50 or 75 ohms.
The output buffer consists of a current mode logic(CML) driver
with user configurable de-emphasis control, which can be
used to optimize performance over a wide range of transmission line lengths and attenuation distortions resulting from low
cost CAT(-5, -6, -7) cable or FR4 backplane. Output de-emphasis is user programmable through SMBus interface. Users
can control the strength of the de-emphasis to optimize for a
specific system environment. Please see the Register Map
for details.
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DS32EL0124/DS32ELX0124
DEVICE CONFIGURATION
There are four ways to configure the DS32EL0124 and
DS32ELX0124 devices, these combinations are shown in
Table 1. Depending on which features are enabled, the deserializers operate in very different ways. The Remote Sense
and DC-Balance pins are active low configuration pins. The
scrambler can be disabled through register programming.
When Remote Sense is enabled, with RS
deserializer must be connected directly to a DS32EL0421/
DS32ELX0421 serializer without any active components between them. The Remote Sense module features both an
upstream and downstream communication method for the
serializer to detect a deserializer and vice versa. This feature
is used to pass link status information between the 2 devices.
If DC-Balance is enabled, the maximum number of parallel
LVDS lanes is four. The fifth lane becomes a Data Valid signal
(TXIN4±). Every time a DS32EL0421/DS32ELX0421 serializer establishes a link to a DS32EL0124/DS32ELX0124 deserializer with DC-Balance enabled, the Data Valid input to
the serializer must be held high for 20 LVDS clock periods. If
pin tied low, the
the Data Valid input to the serializer is logic high, then SYNC
characters are transmitted. If the deserializer receives a
SYNC character, then the LVDS data outputs will all be logic
low and the Data Valid outputs will be logic high. If the deserializer detects a DC-Balance code error, the output data pins
will be set to logic high with the Data Valid output also set to
logic high.
In the case where DC-Balance is enabled and Remote Sense
is disabled, with RS set to high and DC_B set to low, an external device must toggle the Data Valid input to the serializer
periodically to ensure constant lock. With these pin settings
the devices can interface with other active component in the
high speed signal path, such as fiber modules.
When both Remote Sense and DC-Balance are disabled,
RS and DC_B pins set to high, the data is not aligned. In this
configuration, data formatting is handled by an FPGA or external source. This pin setting also allows for the devices to
interface with other active components in the high speed signal path.
TABLE 1. Device Configuration Table
Remote Sense Pin (RS) DC-Balance Pin(DC_B) Configuration
0 0 Remote Sense enabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder disabled by default
0 1 Remote Sense enabled
DC-Balance disabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
1 0 Remote Sense disabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
1 1 Remote Sense disabled
DC-Balance disabled
No Data Alignment
De-Scrambler and NRZI decoder disabled by default
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SMBus INTERFACE
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the Chip
Select signal is required. Holding the SMB_CS pin HIGH enables the SMBus port, allowing access to the configuration
registers. Holding the SMB_CS pin LOW disables the
device's SMBus, allowing communication from the host to
other slave devices on the bus. In the STANDBY state, the
System Management Bus remains active. When communication to other devices on the SMBus is active, the SMB_CS
signal for the deserializer must be driven LOW.
The address byte for all DS32EL0124 and DS32ELX0124
DS32EL0124/DS32ELX0124
devices is B0'h. Based on the SMBus 2.0 specification, these
devices have a 7-bit slave address of 1011000'b. The LSB is
set to 0'b (for a WRITE), thus the 8-bit value is 1011 0000 'b
or AE'h.
The SCK and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is HIGH.
There are three unique states for the SMBus:
START A HIGH to LOW transition on SDA while SCK is
HIGH indicates a message START condition.
STOP A LOW to HIGH transition on SDA while SCK is
HIGH indicates a message STOP condition.
IDLE If SCK and SDA are both HIGH for a time exceeding
t
from the last detected STOP condition or if they
BUF
are HIGH for a total exceeding the maximum
specification for t
then the bus will transfer to
HIGH
the IDLE state.
SMBus Transactions
The devices support WRITE and READ transactions. See
Register Description Table for register address, type (Read/
Write, Read Only), default value and function information.
Writing to a Register
The devices support WRITE and READ transactions. See
Register Description Table for register address, type (Read/
Write, Read Only), default value and function information.
1.
The Host (Master) selects the device by driving its
SMBus Chip Select (SMB_CS) signal HIGH.
2.
The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3.
The Device (Slave) drives the ACK bit (“0”).
4.
The Host drives the 8-bit Register Address.
5.
The Device drives an ACK bit (“0”).
6.
The Host drive the 8-bit data byte.
7.
The Device drives an ACK bit (“0”).
8.
The Host drives a STOP condition.
9.
The Host de-selects the device by driving its SMBus CS
signal Low.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus
2.0 specification).
1.
The Host (Master) selects the device by driving its
SMBus Chip Select (SMB_CS) signal HIGH.
2.
The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
3.
The Device (Slave) drives the ACK bit (“0”).
4.
The Host drives the 8-bit Register Address.
5.
The Device drives an ACK bit (“0”).
6.
The Host drives a START condition.
7.
The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
8.
The Device drives an ACK bit “0”.
9.
The Device drives the 8-bit data value (register contents).
10.
The Host drives a NACK bit “1”indicating end of the
READ transfer.
11.
The Host drives a STOP condition.
12.
The Host de-selects the device by driving its SMBus CS
signal Low.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
SMBus Configurations
Many different configurations of the SMBus are possible and
depend upon the specific requirements of the applications.
Several possible applications are described.
Configuration 1
The deserializer SMB_CS may be tied High (always enabled)
since it is the only device on the SMBus. See Figure 8.
Configuration2
Since the multiple SER devices have the same address, the
use of the individual SMB_CS signals is required. To communicate with a specific device, its SMB_CS is driven High to
select the device. After the transaction is complete, its
SMB_CS is driven Low to disable its SMB interface. Other
devices on the bus may now be selected with their respective
chip select signals and communicated with. See Figure 9.
Configuration 3
The addressing field is limited to 7-bits by the SMBus protocol.
Thus it is possible that multiple devices may share the same
7-bit address. An optional feature in the SMBus 2.0 specification supports an Address Resolution Protocol (ARP). This
optional feature is not supported by the DS32EL0124/
DS32ELX0124 devices. Solutions for this include: the use of
the independent SMB_CS signals, independent SMBus segments, or other means.
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FIGURE 8. SMBus Configuration 1
DS32EL0124/DS32ELX0124
30043107
FIGURE 9. SMBus Configuration 2
FIGURE 10. SMBus Configuration 3
30043108
30043109
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Applications Information
GPIO PINS
The GPIO pins can be useful tools when debugging or evaluating the system. For specific GPIO configurations and functions refer to registers 2, 3, 4, 5 and 6 in the device register
map.
GPIO pins are commonly used when there are multiple deserializers on the same SMBus. In order to program individual
settings into each serializer, they will each need to have a
unique SMBus address. To reprogram multiple deserializers
on a single SMBus, configure the first deserializer such that
DS32EL0124/DS32ELX0124
the SMBus lines are connected to the FPGA or host controller.
The CS pin of the second serializer should be tied to GPIO0
of the first deserializer, with the CS pin of the next deseriazlier
tied to GPIO0 of its preceding deserializer. By holding all of
the GPIO0 pins low, the first deserializer’s address may now
be reprogrammed by writing to register 0. The first
deserializer’s GPIO pin can now be asserted and the second
deserializer’s address may now be reprogrammed.
HIGH SPEED COMMUNICATION MEDIA
Using the deserializer’s integrated equalizer blocks in combination with the DS32EL0421 or DS32ELX0421’s integrated
de-emphasis block allows data to be transmitted across a variety of media at high speeds. Factors that can limit device
performance include excessive input clock jitter, noisy power
rails, EMI from nearby noisy components and poor layout
techniques. Although many cables contain wires of similar
gauge and shielding, performance can vary greatly depending on the quality of the connector.
The DS32ELX0124 also has a programmable de-emphasis
block on its retimed loop through output TxOUT+/-. The deemphasis setting for the loop through driver is programmed
through the SMBus.
REDUNDANCY APPLICATIONS
The DS32ELX0124 has two high speed CML serial inputs.
SMBus register control allows the host device to monitor for
errors or link loss on the active input channel. This enables
the host device, usually an FPGA, to switch to teh secondary
input if problems occur with the primary input.
LINK AGGREGATION
Multiple DS32EL0421/DS32ELX0421 serializers and
D32EL0124/DS32ELX0124 deserializers can be aggregated
together if an application requires a data throughput of more
than 3.125 Gbps. By utilizing the data valid signal of each
device, the system can be properly deskewed to allow for a
single cable, such as CAT-6, DVI-D, or HDMI, to carry data
payloads beyond 3.125 Gbps. The ELXEVK01 evaluation kit
includes sample IP for a link aggregation system to operate
at an application throughput of 6.25 Gbps.
Link aggregation configurations can also be implemented in
applications which require longer cable lengths. In these type
of applications the data rate of each serializer and deserializer
chipset can be reduced, such that the applications' net data
throughput is still the same. Since each high speed channel
is now operating at a fraction of the original data rate, the loss
over the cable is reduced, allowing for greater lengths of cable
to be used in the system.
REACH EXTENSION
The DS32ELX0124 deserializer contains a retimed loop
through CML serial output. The loop through driver also has
programmable de-emphasis making this device capable of
reach extension applications.
DAISY CHAINING
The loop through driver of the DS32ELX0124 deserializer can
be used to string together deserializers in a daisy chain configuration. This allows a single data source such as a
DS32EL0421 serializer to communicate to multiple receiving
systems.
LAYOUT GUIDELINES
It is important to follow good layout practices for high speed
devices. The length of LVDS input traces should not exceed
40 inches. In noisy environments the LVDS traces may need
to be shorter to prevent data corruption due to EMI. Noisy
components should not be placed next to the LVDS or CML
traces. The LVDS and CML traces must have a controlled
differential impedance of 100Ω. Do not place termination resistors at the CML inputs or output, the DS32EL0124 and
DS32ELX0124 have internal termination resistors. It is recommended to avoid using vias. Each pair of vias creates an
impedance mismatch in the transmission line and result in
reflections, which can greatly lower the maximum distance of
the high speed data link. If vias are required, they should be
placed symmetrically on each side of the differential pair. For
more tips and detailed suggestions regarding high speed
board layout principles, please consult the LVDS Owner’s
Manual.
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Page 17
DS32EL0124/DS32ELX0124
FIGURE 11. Typical Interface Circuit
17 www.national.com
30043105
Page 18
Register Map
The register information for the deserializer is shown in the
table below. Some registers have been omitted or marked as
Addr (Hex) Name Bits Field R/W Default Description
00 Device ID 7:1 SMBus Address R/W 58'h Some systems will use all 8
0 Reserved 0
01 Reset 7:1 Reserved
DS32EL0124/DS32ELX0124
0 Software Reset R/W 0 Reset the device. Does not
02 GPIO0 Config 7:4 GPIO0 Mode R/W 0 0000: GP Out
3:2 GPIO0 R Enable R/W 01'b 00: Pullup/Pulldown
1 Input Enable R/W 0 0: Input buffer disabled
0 Output Enable R/W 1'b 0: Output Tri-State™
03 GPIO1 Config 7:4 GPIO1 Mode R/W 0 0000: Power On Reset
3:2 GPIO1 R Enable R/W 01'b 00: Pullup/Pulldown
1 Input Enable R/W 0 0: Input buffer disabled
0 Output Enable R/W 1 0: Output Tri-State™
04 GPIO2 Config 7:4 GPIO2 Mode R/W 0 0000: GP Out
3:2 GPIO2 R Enable R/W 01'b 00: Pullup/Pulldown
1 Input Enable R/W 0 0: Input buffer disabled
0 Output Enable R/W 1'b 0: Output Tri-State™
reserved; these are for internal testing and should not be written to. Some register bits require an override bit to be set
before they can be written to.
bits as the device ID. This
will shift the value from 58’h
to B0’h
affect device ID.
0001: Signal Detect RxIN0
0010: BIST Status
All Others: Reserved
disabled
01: Pulldown Enabled
10: Pullup Enabled
11: Reserved
1: Input buffer enabled
1: Output enabled
0001: GP Out
0010: Signal Detect RxIN1
0011:CDR Lock
All Others: Reserved
disabled
01: Pulldown Enabled
10: Pullup Enabled
11: Reserved
1: Input buffer enabled
1: Output enabled
0001: Always on Clock Out
0010: LVDS Tx CLK
0011: CDR CLK
All Others: Reserved
disabled
01: Pulldown Enabled
10: Pullup Enabled
11: Reserved
1: Input buffer enabled
1: Output enabled
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Page 19
Addr (Hex) Name Bits Field R/W Default Description
05 GP In 7:3 Reserved
2 GP In 2 R 0 Input value on GPIO2
1 GP In 1 R 0 Input value on GPIO1
0 GP In 0 R 0 Input value on GPIO0
06 GP Out 7:3 Reserved
2 GP Out 2 R/W 0 Output value on GPIO2
1 GP Out 1 R/W 0 Output value on GPIO1
0 GP Out 0 R/W 0 Output value on GPIO0
07 — 1F Reserved
20 7 Reserved 0
6 Disable Data Valid R/W 0
5:3 Reserved 0
2 Reverse Data Order R/W 0 0: Normal
1: Reverse output data
order
1 Reset Channel R/W 0 Reset input high speed
channel
0 Digital Powerdown R/W 0 Power down parallel, seria-
to-parallell, and always on
clock
21 Device Config 7 Reserved 0
6 NRZ Decode Enable R/W 0 Enable NRZ decoding of
incoming data; requires an
override bit
5 Descramble Enable R/W 0 Enabled the descrambler,
requires an override bit
4 Rx Mux R/W 0 RX_MUX_SEL control
register. requires an
override bit
3 Decode Bypass R/W 0 Bypass DC Balance
decoder. requires an
override bit
22 Device Config
Override
23 — 26 Reserved
2 Training Sequence
Enable
1:0 Device Configuartion R/W 0 MSB: Remote Sense
7 Reserved
6 NRZ Override R/W 0 Unlock bit 6 of register 21'h
5 Descramble Override R/W Unlock bit 5 of register 21'h
4 Rx Mux Override R/W Unlock bit 4 of register 21'h
3 Reserved
2 Decode Bypass Override R/W Unlock bit 3 of register 21'h
1 Traning Override R/W Unlock bit 2 of register 21'h
0 Device Config Override R/W Unlock bits 1 and 0 of
R/W 0 Enable training sequence.
requires an override bit
enable, active low
LSB: DC balance encoder
enable, active low
requires an override bit
register 21'h
DS32EL0124/DS32ELX0124
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Page 20
Addr (Hex) Name Bits Field R/W Default Description
27 LVDS Per Channel
Enable
7 LVDS VOD High R/W 0 0: LVDS VOD normal
operation. Setting used in
Electrical Characteristics
Table
1: Increases VOD. Allows for
longer traces to be driven,
but consume more power
6 LVDS Control R/W 0 1: Allow SMBus to control
LVDS per channel enable
DS32EL0124/DS32ELX0124
5 RxCLKOUT Enable R/W 0 Enables RxCLKOUT
output driver
4 RxOUT4 Enable R/W 0 Enables RxOUT4 output
driver
3 RxOUT3 Enable R/W 0 Enables RxOUT3 output
driver
2 RxOUT2 Enable R/W 0 Enables RxOUT2 output
driver
1 RxOUT1 Enable R/W 0 Enables RxOUT1 output
driver
0 RxOUT0 Enable R/W 0 Enables RxOUT0 output
driver
28 LVDS Config 7 Reserved 0
6 LVDS Reset R/W 0 Resets LVDS block
5 LVDS Clock Rate R/W 1 0:RxCLKOUT is DDR/2
1: RxCLKOUT is DDR
4 LVDS Clock Invert R/W 0 Inverts the polarity of the
RxCLKOUT signal
3:2 LVDS Clock Delay R/W 10'b 000: No clock delay
111: Max clock delay,
1000 ps See t
Switching Characteristics
for more details
1:0 Reserved 0
29 — 2A Reserved
2B Event Config 7:4 Reserved
3 Event Count Select R/W 0 0: Select CDR Event
Counter for reading. Events
include loss of signal detect
or loss of CDR lock.
1: Select Data Event
Counter for reading
2 Reset CDR Error Count R/W 0 Reset s CDR event count
1 Reset Link Error Count R/W 0 Reset data event count
0 Enable Count R/W 0 Enable event coutners
2C Reserved
LVDL
in LVDS
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Page 21
Addr (Hex) Name Bits Field R/W Default Description
2D Error Monitor 7:5 Reserved
4 Accumulate Error Enable R/W Enable counting
accumulation of errors
3 8b/10b Error disable R/W 1: Disables 8b/10b decode
errors from being counted
or flagged on LOCK pin
2 Clear Event Counter R/W 1: clears errors in both the
current and previous state
of teh errors count
1 Select Error Count R/W 0: Number of errors in
current run
1: Number of errors within
the selected timing window
0 Normal Error Disable R/W 1: Disable exiting NORMAL
state when the number of
errors exceeds the error
threshold
2E Error Threshold LSBs 7:0 Error Threshold R/W 10'h Error threshold above
which part stops
transmittion of data — LSB
2F Error Threshold MSBs 7:0 Error Threshold R/W 0 Error threshold above
which part stops
transmittion of data — MSB
30 — 3A Reserved
3B Data Rate 7 Reserved
6:4 Frequency Range R 111'b 001: Reserved
010: 1 — 1.3 Gbps
011: 1.2 — 1.8 Gbps
100: 1.5 — 2.1 Gbps
101: 1.9 — 2.7 Gbps
110: 2.4 — 3.2 Gbps
111: No Lock
3:2 BIST Status R 0 00: BIST passed
01: BIST failed to capture
PREAMBLE
10: BIST pattern mode
failed
11: BIST data sequence
failed
1 BIST Done R BIST pattern done. Set
when not using repeat.
0 BIST Allign Done R 0 Alignment of incoming data
done
3C Reserved
3D Event Status 7:0 Event Count R 0 Count of errors that caused
a loss of link
3E Error Status LSBs 7:0 Data Error Count R 0 Number of errors in data —
LSB
3F Errors Status MSBs 7:0 Data Error Count R 0 Number of errors in data —
MSB
40 — 49 Reserved
DS32EL0124/DS32ELX0124
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Addr (Hex) Name Bits Field R/W Default Description
49 Loop Through Driver
Config
DS32EL0124/DS32ELX0124
60 EQ Attenuator 7:4 Reserved 0
61 EQ Boost Control 7:5 EQ 0 Boost Control 0 Sets EQ level for RxIN0.
62 Reserved
63 EQ Override Control 7
7:5 Reserved 0
4 Termination Select R/W 1
3:1 Output Amplitude Adjust R/W 011'b 000: Level 7
0 Reserved 0
3 Attenuator 0 Override R/W 0 Overrides attenuation
2 Attenuator 1 Override R/W 0 Overrides attenuation
1 Attenuator 0 Enable R/W 0 1: enables attenuatorfor for
0 Attenuator 1 Enable R/W 0 Enables attenuato for EQ 1.
4:2 EQ 1 Boost Control 0 Sets EQ level for RxIN1.
1:0 Reserved
6
5 EQ 0 Enable R/W 1 Enables EQ for RxIN0
4 EQ 1 Enable R/W 0 Enables EQ for RxIN1
3:0 Reserved
0: 75Ω
1: 50 Ω
001: Level 8 (Highest
output)
010: Level 5
011: Level 6 (Normal
output)
100: Level 4
101: Level 3
110: Level 2
111: Level 1 (Lowest
output)
control in EQ 0
control in EQ 1
EQ 0. Requires bit 3 to be
set
Requires bit 2 to be set.r
Requires override bit
Requires override bit
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Page 23
Physical Dimensions inches (millimeters) unless otherwise noted
DS32EL0124/DS32ELX0124
(See AN-1187 for PCB Design and Assembly Recommendations)
NS Package Number SQA48A
23 www.national.com
Page 24
Notes
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DS32EL0124/DS32ELX0124 125 — 312.5 MHz Deserializer with DDR LVDS Parallel Interface
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