Datasheet DS1841 Datasheet (Maxim Integrated Producs)

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

Rev 0; 11/07

________________________________________________________________

Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

General Description

The DS1841 is a 7-bit, logarithmic, nonvolatile (NV) digi­tal resistor that features an on-chip temperature sensor
and associated analog-to-digital converter (ADC). The
integrated temperature sensor indexes a 72-byte NV
lookup table (LUT) encompassing a temperature range
from -40°C to +100°C. The LUT output can drive the
resistor directly or be added to an NV initial-value regis­ter (IVR) to drive the resistor. This flexible LUT-based
architecture allows the DS1841 to provide a tempera­ture-compensated resistor output with arbitrary slope.
Programming is accomplished by an I2C-compatible
interface, which can operate at speeds of up to 400kHz.

Applications

Optical Transceivers

Linear and Nonlinear Compensation

Instrumentation and Industrial Controls

Mechanical Potentiometer Replacement

Features

♦ 22kΩ to 3.7kΩ Adjustable Logarithmic Resistor

with a 3.6kΩ Fixed Resistor

♦ 128 Wiper Tap Points

♦ On-Chip Temperature Sensor and ADC

♦ 72-Byte Lookup Table (LUT)

♦ I

2

C-Compatible Serial Interface

♦ Address Pins Allow Up to Four DS1841s to Share

the Same I

2

C Bus

♦ Digital Supply of 2.7V to 5.5V

♦ -40°C to +100°C Operating Range

♦ 3mm x 3mm, 10-Pin TDFN Package

134

10 8 7

SCL RH RW

SDA

*EP

*EXPOSED PAD

V

CC

A1

2

9

N.C.

GND

5

6

RGND

A0

TDFN

3.0mm × 3.0mm × 0.8mm

TOP VIEW

DS1841

Pin Configuration

Ordering Information

0.1μF

3.3V

APD BIAS CONTROL APPLICATION

V

CC

V

OUT

FB

SDA
SCL

A1
A0

GND

100pF

RW

RGND

RH

V

APD

4.7kΩ

4.7kΩ

DC-DC

CONVERTER

DS1841

Typical Operating Circuit

+

Denotes a lead-free package.

T&R = Tape and reel.

Registers and Modes are capitalized for clarity.

PART TEMP RANGE PIN-PACKAGE

DS1841T+ -40°C to +100°C 10 TDFN

DS1841T+T&R -40°C to +100°C 10 TDFN

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

2 _______________________________________________________________________________________

RECOMMENDED OPERATING CONDITIONS

(TA= -40°C to +100°C)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on SDA, SCL, and

V

CC

Relative to GND .........................................-0.5V to +6.0V

Voltage Range on RH, RW, A0, and

A1 Relative to GND ................................-0.5V to (V

CC

+ 0.5V)

Operating Temperature Range .........................-40°C to +100°C

Programming Temperature Range .........................0°C to +70°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature .....................See IPC/JEDEC J-STD-020

RW Current............................................................................3mA

DC ELECTRICAL CHARACTERISTICS

(VCC= +2.7V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V

Input Logic 1
(SCL, SDA, A0, A1)

Input Logic 0
(SCL, SDA, A0, A1)

Resistor Inputs (RW, RH) V

Wiper Current I

WIPER

CC

V

V

RES

(Note 1) +2.7 +5.5 V

IH

IL

2mA

0.7 x
V

CC

-0.3

-0.3

V

CC

+ 0.3

0.3 x
V

CC

V

CC

+ 0.5

V

V

V

Input Leakage
(SDA, SCL, A0, A1)

VCC Supply C urrent I

Low-Leve l Output Voltage (SDA) V

I/O Capacitance C

Power-On Recall Voltage V

Power-Up Recall Delay tD (Note 4) 5 ms

Series Resistance RS 3.6 k

Minimum Resistance
(GND to RW)

End-to-End Resistance
(GND to RW)

R

TOTAL

Temp Coefficient TCV WR set to 40h ±250 ppm/°C

RH, RW Capacitance C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I

CC2

OL

I/O

POR

R

MIN

R

TOTAL

Tolerance TA= +25°C -20 +20 %

POT

-1 +1 μA

L

(Note 2) 350 μA

3mA sink current 0 0.4 V

5 10 pF

(Note 3) 1.6 2.6 V

(Note 5) 370 

22 k

10 pF

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

_______________________________________________________________________________________ 3

TEMPERATURE SENSOR CHARACTERISTICS

(VCC= +2.7V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)

ANALOG VOLTAGE MONITORING CHARACTERISTICS

(VCC= +2.7V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)

I2C AC ELECTRICAL CHARACTERISTICS (See Figure 3)

(VCC= +2.7V to +5.5V, TA= -40°C to +100°C, timing referenced to V

IL(MAX)

and V

IH(MIN)

.)

Temperature Error ±5 °C

Update Rate (Temperature and
Supply Conversion Time)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

t

FRAME

16 ms

Supply Resolution LSB Full-scale voltage of 6.5536V 25.6 mV

Input/Supply Accuracy ACC At factory setting 0.25 1.0

Update Rate (Temperature and
Supply Conversion Time)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

16 ms

t

FRAME

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCL Clock Frequenc y f

Bus Free Time Between STOP
and START Conditions

Hold Time (Repeated) START
Conditions

Low Period of SCL t

High Period of SCL t

Data Hold Time t

Data Setup Time t

START Setup Time t

SDA a nd SCL Ri se Time t

SDA and SCL Fall Time t

STOP Setup Time t

SDA a nd SCL Capacit i ve
Loading

t

HD: STA

HD:DAT

SU:DAT

SU:STA

SU:STO

SCL

t

BUF

LOW

HIGH

C

(Note 6) 0 400 kH z

1.3 μs

0.6 μs

1.3 μs

0.6 μs

0 0.9 μs

100 ns

0.6 μs

(Note 7)

R

(Note 7)

F

0.6 μs

(Note 7) 400 pF

B

20 +

0.1C

20 +

0.1C

300 ns

B

300 ns

B

% FS

(Full

Scale)

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

4 _______________________________________________________________________________________

Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are

negative.

Note 2:I

CC

is specified with the following conditions: SCL and SDA = VCC, RW and RH floating with Update Mode bit = 1.

Note 3: This is the minimum V

CC

voltage that causes NV memory to be recalled.

Note 4: This is the time from V

CC

> V

POR

until initial memory recall is complete.

Note 5: Guaranteed by design.
Note 6: I

2

C interface timing shown is for Fast-Mode (400kHz) operation. This device is also backward-compatible with I2C-

Standard Mode timing.

Note 7: C

B

—total capacitance of one bus line in picofarads.

Note 8: EEPROM write time begins after a STOP condition occurs.
Note 9: Guaranteed by characterization.

I2C AC ELECTRICAL CHARACTERISTICS (See Figure 3) (continued)

(VCC= +2.7V to +5.5V, TA= -40°C to +100°C, timing referenced to V

IL(MAX)

and V

IH(MIN)

.)

NONVOLATILE MEMORY CHARACTERISTICS

(VCC= +2.7V to +5.5V)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

EEPROM Write Time t

A0, A1 Setup Time t

A0, A1 Hold Time t

Input Capacitance on
A0, A1, SDA, or SCL

Startup Time t

SU:A

HD:A

C

ST

(Note 8) 10 20 ms

W

Before START 0.6 μs

After STOP 0.6 μs

5 10 pF

I

2 ms

EEPROM Write Cycles TA = +85°C 50,000 Writes

EEPROM Write Cycles TA = +25°C (Note 9) 200,000 Writes

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

DS1841 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

5.04.54.03.53.0

50

100

150

200

250

0

2.5 5.5

SDA = SCL = VCC

RH, RH, RW ARE FLOATING

SDA = SCL = V

CC

RGND, RH, RW ARE FLOATING

UPDATE MODE BIT = 0UPDATE MODE BIT = 0

LUT MODE AND LUT ADDER MODE

UPDATE MODE BIT = 1

LUT MODE AND LUT ADDER MODE

UPDATE MODE BIT = 1

SUPPLY CURRENT

vs. TEMPERATURE

DS1841 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

806040200-20

50

100

150

200

250

0

-40 100

SDA = SCL = VCC

RH, RH, RW ARE FLOATING

SDA = SCL = VCC = 5V

RGND, RH, RW ARE FLOATING

UPDATE MODE BIT = 0UPDATE MODE BIT = 0

LUT MODE AND LUT ADDER MODE

UPDATE MODE BIT = 1

LUT MODE AND LUT ADDER MODE

UPDATE MODE BIT = 1

SUPPLY CURRENT

vs. SCL FREQUENCY

DS1841 toc03

SCL FREQUENCY (kHz)

SUPPLY CURRENT (mA)

300200100

50

100

150

200

250

0

0 400

SDA = SCL = VCC

RH, RH, RW ARE FLOATING

SDA = VCC = 5V

RGND, RH, RW ARE FLOATING

UPDATE MODE BIT = 0UPDATE MODE BIT = 0

LUT MODE AND LUT ADDER MODE

UPDATE MODE BIT = 1

LUT MODE AND LUT ADDER MODE

UPDATE MODE BIT = 1

WIPER RESISTANCE (RW)

vs. SETTING

DS1841 toc04

SETTING (DEC)

WIPER RESISTANCE (kΩ)

125100755025

5

10

15

20

25

0

0

SDA = SCL = VCC = 5VSDA = SCL = VCC = 5V

WIPER CURRENT

vs. WIPER SETTING

DS1841 toc05

WIPE SETTING (DEC)

WIPER CURRENT (mA)

100755025

0.4

0.8

1.2

1.6

0

0 125

RGND = 0V
RW OPEN
FORCE 1.25V ON RH AND
MEASURE CURRENT

RGND = 0V
RW OPEN
FORCE 1.25V ON RH AND
MEASURE CURRENT

VCC = 5V

SDA AND SCL REFERENCED TO 5V

VCC = 5V

SDA AND SCL REFERENCED TO 5V

RW TO RGND RESISTANCE

vs. SUPPLY VOLTAGE

DS1841 toc06

SUPPLY VOLTAGE (V)

RESISTANCE AT RW (kΩ)

5.04.54.03.53.02.52.01.51.00.5

10

20

30

40

0

0 5.5

POR OCCURSPOR OCCURS

IVR IS LOADED

IVR IS LOADED

CONVERSIONS COMPLETE

LUT VALUE LOADED TO WR

CONVERSIONS COMPLETE

LUT VALUE LOADED TO WR

Typical Operating Characteristics

(VCC= +2.7V to +5.5V, TA= +25°C, unless otherwise noted.)

_______________________________________________________________________________________

5

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

6 _______________________________________________________________________________________

Pin Description

Detailed Description

The DS1841 operates in one of two modes: LUT Mode
and LUT Adder Mode. In LUT Mode and LUT Adder
Mode, the resistor’s wiper position is controlled as a
function of the temperature measured by the DS1841’s
internal temperature sensor. The difference between
the two LUT modes is the way the resistor’s wiper posi­tion is calculated. Detailed descriptions of these two
modes, as well as additional features of the DS1841,
are discussed in subsequent sections.

Digital Resistor Description

The DS1841’s resistor consists of 128 resistive steps
between RW and RGND with a series resistor, RS,
between RH and RW. The wiper position and the output
seen on RW are decoded based on the value in the
wiper register (WR). The step size of each position is
optimized to produce a linear response when used in
the feedback network of a DC-DC converter.

Mode Selection

The DS1841 mode of operation is determined by the
Update Mode bit (Control Register 1, address 03h, bit 0)
and the Adder Mode bit (Control Register 1, address
03h, bit 1). Table 1 illustrates how the two control bits
are used to select the operating mode. When shipped
from the factory, the DS1841 is programmed with the
Update Mode and Adder Mode bits set to 1, hence con­figuring the DS1841 in LUT Adder Mode. See Appendix
A for a detailed table of the control logic bit functions.

Table 1. Operating Modes

PIN NAME FUNCTION

1 SDA I2C Serial Data. Input/output for I2C data.

2 GND Ground

3 V

4 A1

5 A0

6 RGND Low Terminal of Re sistor. Must be connected to GND.

7 RW Wiper Terminal

8 RH Terminal with Fixed Resistor Added in Series with Digital Resistor

9 N.C. No Connection

10 SCL I2C Serial Clock. Input for I2C clock.

— EP Exposed Paddle. Must be connected to ground.

CC

Power Supply

Address Select Inputs. Determines I
Slave Address Byte and Address Pins section s for more details).

2

C slave address. Device address is 01010A1A0X (see the

UPDATE MODE

BIT

1 0 LUT Mode

1 1

ADDER MODE BIT MODE

LUT Adder Mode

(Default)

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

_______________________________________________________________________________________ 7

LUT Adder Mode (Default)

LUT Adder Mode is selected by setting the Update
Mode bit to 1 and the Adder Mode bit to 1. This mode
operates similar to LUT Mode with one major difference
(see the

LUT Mode and LUT Adder Mode Block

Diagram

). The WR is loaded with the sum of the values
of LUTVAL (the value pointed to by the address stored
in LUTAR) and IVR. Furthermore, in this mode, the val­ues programmed into the LUT are signed two’s com­plement. This allows convenient positive or negative
offsetting of the nominal IVR value. WR resistance val­ues clamp at 00h and 7Fh (the MSB is ignored).

LUT Mode

LUT Mode is selected by setting the Update Mode bit
(Control Register 1, address 03h, bit 0) to a 1 and the
Adder Mode bit (Control Register 1, address 03h, bit 1)
to a 0. An overview of the DS1841 in this mode is illus­trated in the

LUT Mode and LUT Adder Mode Block

Diagram

. The memory map for the LUT Mode and the
LUT Adder Mode is shown in Table 2. The major differ­ence between the two LUT modes is whether the value

in the IVR is added to the values stored in the LUT. The
dashed line/arrow shown in the

LUT Drive Mode Block

Diagram

is not active in LUT Mode. When in LUT Mode,
on power-up the IVR value is recalled into the WR. This
value remains there until completion of the first temper­ature conversion following power-up. The temperature
is measured every t

FRAME

. The temperature value is
used to calculate an index that points to the corre­sponding value in the LUT. This index is referred to as
the LUT Address Register (LUTAR) and is located at
address 08h. The value stored in the LUT at the loca­tion pointed to by LUTAR is called LUTVAL, and this
value is stored as the WR value (WR) at address 09h
when Update Mode bit = 1. The process then repeats
itself, continuously updating the wiper setting in a
closed-loop fashion. In this mode the 72-byte LUT is
populated with wiper settings for each two-degree tem­perature window. Valid wiper settings are 00h to 7Fh
(the MSB is ignored). Table 3 shows the memory
addresses of the LUT as well as the corresponding
temperature range for each byte in the LUT.

Table 2. LUT Mode and LUT Adder Mode Memory Map

*In LUT Mode and LUT Adder Mode, WR is accessed through memory address 09h, while IVR remains at memory address 00h.

REGISTER NAME

IVR Init ia l Value Reg ister 00h NV (Shadowed) 00h

CR0 Control Regi ster 0 02h Volatile 00h

CR1 Control Regi ster 1 03h NV (Shadowed) 03h

LUTAR LUT Address Register 08h Volatile 00h

WR LUT Value Register 09h* Volati le 00h

CR2 Control Register 2 0Ah Volatile 00h

TEMP Temperature Result 0Ch Volatile (Read Only) N/A

VOLTAGE Supply Voltage Resu lt 0Eh Volatile N/A

LUT

Temperature Lookup

Registers

ADDRESS

(HEX)

80h–C7h NV 00h

VOLATILE/NV

FACTORY/POWER-UP

DEFAULT

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

8 _______________________________________________________________________________________

Temperature Conversion and Supply

Voltage Monitoring

Temperature Conversion

The DS1841 features an internal 8-bit temperature sen­sor that can drive the LUT and provide a measurement
of the ambient temperature over I2C by reading the
value stored in address 0Ch. The sensor is functional
over the entire operating temperature range and is
stored in signed two’s complement format with a resolu­tion of 1°C/bit. See Table 2, Register 0Ch description for
the temperature sensor’s bit weights. To calculate the
temperature, treat the two’s complement binary value as
an unsigned binary number, then convert it to decimal.
If the result is greater than or equal to 128, subtract 256
from the result.

LUT

The DS1841 monitors the internal temperature by
repeatedly polling the sensor’s result with update rate
t

FRAME

. During each cycle, the DS1841 reads the inter­nal temperature, and, based on that temperature,
points to the corresponding LUT address. Every two
degrees of temperature will convert into one tempera­ture address slot. See Table 3 for a list of temperatures
and their corresponding LUT addresses.

The LUT features one-degree hysteresis to prevent
chattering if the measured temperature falls on the
boundary between two windows (see Figure 1).

Table 3. LUT Registers and Temperature Ranges

LUT Mode and LUT Adder Mode Block Diagram (Update Mode Bit = 1)

V

CC

GND

SCL

SDA

A0

A1

CONTROL

LOGIC/

2

C

I

INTERFACE

TEMP

SENSOR

V

CC

VOLTAGE

*NOTE THAT WHEN IN LUT OR LUT ADDER MODE, WR IS ACCESSED THROUGH 09h WHILE IVR REMAINS AT 00h.

REGISTERS

DATA

ADC

CONTROL

TEMP

0Ch

VCC (V)

0Eh

LUT

ADDRESS

REGISTER

(LUTAR)

08h

INITIAL VALUE REGISTER (IVR)

72-BYTE
LOOKUP

TABLE

LUTVAL

(LUT)

80h–C7h

00h*

IVR

ONLY WHEN IN

∑

LUTVAL+IVR

LUT ADDER MODE

LUTVAL

OR

WIPER

REGISTER

(WR)

09h*

ON POWER-UP

POS 7Fh

1 OF 128 MULTIPLEXERS

POS 00h

R

S

RGND

RW

RH

TEMPERATURE (°C)

-40 or le ss D8 80

-39 to -38 D9 to DA 81

-37 to -36 DB to DC 82

-35 to -34 DD to DE 83

— — —

+95 to +96 5F to 60 C4

+97 to +98 61 to 62 C5

+99 to +100 63 to 64 C6

+101 or more 65 C7

TEMPERATURE VALUE FOR GIVEN

TEMPERATURE (HEX)

CORRESPONDING LUT ADDRESS

(HEX)

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

_______________________________________________________________________________________ 9

Supply Voltage Monitoring

The DS1841 also features an internal 8-bit supply volt­age (VCC) monitor. A value of the supply voltage mea­surement can be read over I2C at the address 0Eh.

To calculate the supply voltage, simply convert the
hexadecimal result into decimal and then multiply it by
the LSB as shown in

the Analog Voltage Monitoring

Characteristics

electrical table.

Supply Current (ICC)

The DS1841 has two supply current levels of power sup­ply consumption. First, active current during I

2

C com­munications while in the LUT-Driven Mode is the “worst
case” supply current, I

CC

. All functionality including I2C
communication is operating simultaneously. Second,
active current without I2C while in the LUT-Driven Mode
is quantified by the supply current, I

CC2

. SDA and SCL

are held statically in the high logic level.

Slave Address Byte and Address Pins

The slave address byte consists of a 7-bit slave
address plus a R/W bit (see Figure 2). The DS1841’s
slave address is determined by the state of the A0 and
A1 address pins. These pins allow up to four devices to
reside on the same I2C bus. Address pins tied to GND
result in a 0 in the corresponding bit position in the
slave address. Conversely, address pins tied to V

CC

result in a 1 in the corresponding bit positions. For
example, the DS1841’s slave address byte is 50h when
A0 and A1 pins are grounded. I2C communication is
described in detail in the

I2C Serial Interface

Description

section.

Figure 1. LUT Hysteresis

Figure 2. Slave Address Byte

LUT34

LUT33

LUT32

LUT31

MEMORY LOCATION

LUT30

19 21 23 25 19 27

MSB

01 10 R/WA0A10

*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1.

DECREASING

TEMPERATURE

INCREASING

TEMPERATURE

1°C HYSTERESIS

WINDOW

TEMPERATURE (°C)

LSB

READ/WRITE BITSLAVE ADDRESS*

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

10 ______________________________________________________________________________________

Memory Description

The DS1841’s internal memory consists of both volatile
and NV registers that are organized into eight byte

rows. Three control registers as well as specialized
data registers are used to control the wiper and drive
the LUT.

Register 00h: Initial Value Register (IVR)

Register 02h: Control Register 0 (CR0)

Register Descriptions

FACTORY DEFAULT (IVR) 00h
MEMORY TYPE NV
MEMORY TYPE Vola tile

00h IVR

Bit 7 Bit 0

If SEE bit = 0, an I2C READ retrieves the IVR value and an I2C WRITE sets the wiper position in volatile memory and
updates IVR in NV memory with this new value. If SEE bit = 1, an I
sets the wiper position (volatile) and the IVR value is not modified. During power-up, IVR’s value is used to set the wiper
position.

FACTORY DEFAULT 00h
MEMORY TYPE Vola tile

02h SEE Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Bit 7 Bit 0

2

C READ retrieves the WR value and an I2C WRITE

SEE Controls IVR and WR functionality, as well as the memory type for Control Register 1.
0 = (Default) Issuing an I
WRITE to address 00h sets both the wiper’s position (volatile) and the IVR value (nonvolatile) to the

Bit 7

Bits 6 to 0 Reserved.

Control Register 0 determines how the wiper position values (volatile and NV versions) are set, as well as how writes to
Control Register 1 are stored.

The IVR i s located at memory address 00h and is implemented as EEPROM shadowed SRAM. This register can be
vi sualized as an SRAM byte (the WR portion) in parallel with an EEPROM byte (the IVR portion). The operation of the
register is control led b y the Shadow EEPROM (SEE ) bit in Control Register 0, address 02h, bit 7. When the SEE bit = 0
(default), data written to memory address 00h by I
SEE = 1, only the SRAM (WR) is written to the new value. The EEPROM byte (IVR) continue s to store the last value
written to it when SEE was 0. Reading memory address 00h reads the value stored in WR. The SEE bit is volatile and its
power-up default state is 0.

same value. Writes to Control Register 1 (03h) are stored in shadowed SRAM and EEPROM.
1 = Issuing an I
address 00h only sets the wiper’s position (volatile). The IVR value is not modified. Writes to Control
Regi ster 1 (03h) are stored in shadowed SRAM onl y.

2

C READ of the value in address 00h retrieves the WR value. Issu ing an I2C WRITE to

2

C READ of the value in address 00h retrieves the IVR value. Issuing an I2C

2

C actuall y gets stored in both SRAM (WR) and EEPROM (IVR). When

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

______________________________________________________________________________________ 11

Register 03h: Control Register 1 (CR1)

Register 08h: LUT Address Register (LUTAR)

Register 09h: LUT Value Register (WR*)

FACTORY DEFAULT 00h
MEMORY TYPE Shadowed NV

03h Reserved Re served Reserved Reserved Reserved Reserved Adder Mode Update Mode

Bit 7 Bit 0

Bits 7 to 2 Reserved.

Adder Mode This bit is va lid only if the Update Mode bit = 1.

Bit 1

Bit 0

Control Register 1 control s how the wiper position i s determined. The SEE bit controls whether the values of this register
are stored in EEPROM or in Shadowed SRAM. On power-up, the EEPROM value is recalled to thi s register, regardless of
the state of SEE.

While the registers other than 00h through 0Ah can be read, they are not updated by the ADC as the ADC is disab led
with the Update Mode bit = 0.

0 = (Default) The LUTV AL or IVR va lue i s directly loaded to W R though the mux.
1 = The LUTVAL is summed with the IVR value and is directly loaded to WR though the mux.
Update Mode
0 = (Default) CR0 is enabled. During power-up the IVR value is loaded into the WR to set the wiper

position. Updates to Temperature Result (0Ch) and Supply Voltage Result (0Eh) are halted.
1 = The WR is controlled directl y by I
controlled by the temperature-compensation/LUT circuitry. If temperature compensation is enabled, one
of the 72 temperature slots is selected (by the LUTAR) and this sl ot va lue i s copied into the LUTVAL,
which in turn sets the WR. Updates to Temperature Result (0Ch) and Supply Voltage Result (0Eh) are
enabled.

2

C communication though registers 08h or 09h, or the WR is

FACTORY DEFAULT 00h
POR DEFAULT 00h unti l t
MEMORY TYPE Vola tile

08h LUTA R

Bit 7 Bit 0

The LUTAR register serves as the index pointer to choose the corresponding temperature slot in the LUT based on the
internal temperature sensor result. The LUTAR can be directly read by acess ing address 08h; however, to write an new
value to LUTAR (to control WR manually), the LUTAR Mode bit must be set to a 1.

FACTORY DEFAULT 00h
MEMORY TYPE Vola tile

09h WR*

Bit 7 Bit 0

WR serves as an intermediate location, which is populated automatically with the results of the temperature-indexed
lookup. The WR can be directly read by acessing address 09h; however to write an new value to WR (to control it
manually), the wiper access control bit must be set to a 1. WR is an unsigned 7-bit value.

*WR i s updated every t

if Update Mode bit = 1. If Update Mode bit = 0, WR holds the value stored in register 00h.

FRAME

FRAME

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

12 ______________________________________________________________________________________

Register 0Ah: Control Register 2 (CR2)

Register 0Ch: Temperature Result (TEMP)

Register 0Eh: Supply Voltage Result (VOLTAGE)

FACTORY DEFAULT 00h
MEMORY TYPE Vola tile

0Ah Reser ved Reserved Reserved Reserved Re served

Bit 7 Bit 0

Bits 7 to 3 Reserved.

Wiper Access Control This bit is valid only in LUT Mode and in LUT Adder Mode.
0 = (Default) WR is loaded with the va lue from IVR summed with LUTVAL, or just the va lue of LUTVAL

Bit 2

Bit 1

Bit 0 Reserved. This bit must be set to a 0.

Control Register 2 controls how the wiper position i s determined.

FACTORY DEFAULT None
MEMORY TYPE Vola tile

based on the state of the Adder Mode bit.
1 = The DS1841 is placed in a manual mode, allowing WR (address 09h) to be programmed using I
commands.

LUTAR Mode This bit is valid only in LUT Mode and in LUT Adder Mode.
0 = (Default) The LUTAR value, located in at address 08h, is calculated following each temperature

conversion that points to the corresponding location in the LUT.
1 = Automatic updates of LUTAR are di sabled, allowing the LUTAR regi ster to be programmed using I
commands.

Wiper

Access

Control

LUTAR Mode Reserved

2

C

2

C

0Ch Sign 2

Bit 7 Bit 0

Thi s register holds the current temperature result. It is updated every conversi on time, t
temperature, treat the two’s complement binary value as an unsigned binary number, then convert it to decimal. If the
result is greater than or equal to 128, subtract 256 from the result. This regis ter is onl y updated when the Update Mode
bit = 1. When the Update Mode bit = 0, no ADC updates are made to this register.

FACTORY DEFAULT None
MEMORY TYPE Vola tile

0Eh Supply Voltage

Bit 7 Bit 0

This register holds the current supply voltage result. It is updated every conversion time, t
Monitoring section. This regi ster is only updated when the Update Mode bit = 1. When the Update Mode bit = 0, no ADC
updates are made to th is register.

6

2

5

2

4

2

3

2

2

2

FRAME

FRAME

1

2

. To calculate the

. See the Supply Voltage

0

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

______________________________________________________________________________________ 13

I2C Serial Interface Description

I2C Definitions

The following terminology is commonly used to describe
I2C data transfers. (See Figure 3 and I2C AC Electrical
Table for additional information.)

Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.

Slave devices: Slave devices send and receive data at
the master’s request.

Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.

START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.

STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.

Repeated START condition: The master can use a
repeated START condition at the end of one data trans­fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a spe­cific memory address to begin a data transfer. A repeat­ed START condition is issued identically to a normal
START condition.

Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.

Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses, including when it is reading bits from the
slave.

Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans­mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.

Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi­cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas­ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.

Registers 80h to C7h: Temperature Lookup Register (LUT)

FACTORY DEFAULT 00h
MEMORY TYPE NV

80h

to

C7h

Bit 7 Bit 0

These registers at location 80h to C7h are NV and serve to temperature compensate RW over the operating temperature
range of the DS1841.

The LUT entries are un signed 8-bit value s if the Adder Mode bit = 0. If the A dder Mode bit = 1, LUT entr ies are two ’s
complement, signed 7-bit values.

(See Table 3 for settings.)

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

14 ______________________________________________________________________________________

Byte read: A byte read is an 8-bit information transfer

from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.

Slave address byte: Each slave on the I2C bus
responds to a slave address byte sent immediately fol­lowing a START condition. The slave address byte con­tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.

The DS1841’s slave address is determined by the state
of the A0 and A1 address pins as shown in Figure 2.
Address pins tied to GND result in a 0 in the corre­sponding bit position in the slave address. Conversely,
address pins tied to VCCresult in a 1 in the corre­sponding bit positions.

When the R/W bit is 0 (such as in 50h), the master is
indicating that it will write data to the slave. If R/W = 1
(51h in this case), the master is indicating that it wants
to read from the slave.

If an incorrect slave address is written, the DS1841
assumes the master is communicating with another I

2

C
device and ignores the communication until the next
START condition is sent.

Memory address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans­mitted during a write operation following the slave
address byte.

I2C Communication

Writing a single byte to a slave: The master must gen­erate a START condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a STOP condition. Remember the
master must read the slave’s acknowledgment during
all byte write operations.

When writing to the DS1841, the potentiometer adjusts to
the new setting once it has acknowledged the new data
that is being written, and the EEPROM is written following
the STOP condition at the end of the write command. To
change the setting without changing the EEPROM, termi­nate the write with a repeated START condition before
the next STOP condition occurs. Using a repeated
START condition prevents the tWdelay required for the
EEPROM write cycle to finish.

Figure 3. I2C Timing Diagram

SDA

t

BUF

t

SCL

STOP

START

LOW

t

HD:STA

t

R

t

HD:DAT

t

F

t

HIGH

t

SU:DAT

REPEATED

START

t

SU:STA

t

HD:STA

t

SP

t

SU:STO

NOTE: TIMING IS REFERENCE TO V

IL(MAX)

AND V

IH(MIN)

.

DS1841

Temperature-Controlled, NV, I2C,

Logarithmic Resistor

______________________________________________________________________________________ 15

Writing multiple bytes to a slave: I2C write operations

of multiple bytes can also be performed. During a sin­gle write sequence, up to 8 bytes in one page can be
written at one time. If more than eight bytes are trans­mitted in the sequence, then only the last eight trans­mitted bytes are stored. After the last physical memory
location in a particular page (8-byte page write), the
address counter automatically wraps back to the first
location in the same page for subsequent byte write
operations.

Acknowledge polling: Any time a EEPROM byte is
written, the DS1841 requires the EEPROM write time
(tW) after the STOP condition to write the contents of
the byte to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS1841, which allows communication to continue as
soon as the DS1841 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
t

W

to elapse before attempting to access the device.

Reading a single byte from a slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read opera­tion occurs at the present value of the memory address

counter. To read a single byte from the slave, the master
generates a START condition, writes the slave address
byte with R/W = 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a STOP
condition. However, since requiring the master to keep
track of the memory address counter is impractical, the
following method should be used to perform reads from
a specified memory location.

Reading multiple bytes from a slave: The read opera­tion can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte it must NACK to indicate the end of
the transfer and generates a STOP condition. During a
single read sequence of multiple bytes, after the last
address counter position of FFh is accessed, the
address counter automatically wraps back to the first
location, 00h. Read operations can continue indefinitely.

Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen­erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-

Figure 4. I2C Communication Examples

2

C WRITE TRANSACTION

TYPICAL I

MSB LSB MSB LSB MSB LSB

START

0 1 0 1 0 A1 A0 R/W

SLAVE

ADDRESS*

EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE CONNECTED TO GND)

A)

SINGLE-BYTE WRITE

-WRITE CONTROL
REGISTER 0 TO 00h

B)

SINGLE-BYTE READ

-READ TEMPERATURE
REGISTER

C)

TWO-BYTE WRITE

- WRITE LUT VALUES FOR
REGISTERS 80h AND 81h

TWO-BYTE READ

D)

- READ LUT REGISTERS
80h AND 81h

START

START

START

START

READ/
WRITE

50h 02h

0 1010000

50h

0 1010000

50h 80h

0 1010000 10000000

50h 80h

0 1010000 10000000

SLAVE

b7 b6 b5 b4 b3 b2 b1 b0

ACK

REGISTER ADDRESS

*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.

0Ch

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

00000 010

00001 100

00000000

REPEATED

START

40h

100 0 0 00

0

REPEATED

START

SLAVE

b7 b6 b5 b4 b3 b2 b1 b0

ACK

SLAVE

STOP

ACK

51h DATA

51h

SLAVE

ACK

50h

101 0 0 00

0

SLAVE

01010 001

SLAVE

ACK

101 0 0 01

0

ACK

TEMP

SLAVE

ACK

DATA

DATA

MASTER

NACK

STOP

MASTER

ACK

STOP

REG81hREG80h

DATA

SLAVE

ACK

STOP

MASTER

ACK

STOP

DS1841

Temperature-Controlled, NV, I2C,
Logarithmic Resistor

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates a
STOP condition. See Figure 4 for I

2

C Communication

Examples.

Applications Information

Power-Supply Decoupling

To achieve the best results when using the DS1841,
decouple both the power-supply pin and the wiper-bias
voltage pin with a 0.01µF or 0.1µF capacitor. Use a
high-quality ceramic surface-mount capacitor if possi­ble. Surface-mount components minimize lead induc-

tance, which improves performance, and ceramic
capacitors tend to have adequate high-frequency
response for decoupling applications.

SDA and SCL Pullup Resistors

SDA is an I/O with an open-collector output that
requires a pullup resistor to realize high-logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for SCL. Pullup resistor values should be chosen to
ensure that the rise and fall times listed in the AC elec­trical characteristics are within specification. A typical
value for the pullup resistors is 4.7kΩ.

Appendix A: Control Bits Logic Table

Package Information

(For the latest package outline information, go to

www.maxim-ic.com/DallasPackInfo

.)

PACKAGE TYPE DOCUMENT NO.

10 TDFN

21-0137

WIPER

LUTAR

MODE BIT

X X X 0

0 0 0 1

0 0 1 1

X 1 0 1

X 1 1 1

1 0 0 1

1 0 1 1

ACCESS

CONTROL

ADDER

MODE BIT

BIT

UPDATE

MODE BIT

CONTROL OF WR AND REGISTER FUNCTIONALITY

IVR is loaded to WR on power-up. Subsequent writes to 00h set the va lue
of WR.

Temperature convers ion reference s the LUT, determining LUTAR value,
the LUTAR determines the LUTVAL value, the uns igned LUTVAL value
is then automatical ly loaded into WR.

Temperature convers ion reference s the LUT, determining LUTAR value,
the LUTA R sets the LUTVAL value, the signed LUTVAL value is then
summed with IVR, and the result is loaded into WR.

2

I

C Write (to 09h): The un signed value written to WR, register 09h, is

loaded into WR.

2

I

C Write (to 09h): The signed va lue of LU TVAL is summed with IVR, then

loaded into WR, register 09h.

2

I

C Write (to 08h): LUTAR references LUT address, va lue at LUT addres s
location is loaded into LUTVAL, the unsigned LUTVAL value is loaded
into WR.

2

C Write (to 08h): LUTAR references LUT address, the signed value at

I
LUT address location is loaded into LUTVAL, the signed LUTVAL value
is summed with IVR va lue, and the result i s loaded into WR.