Datasheet DS1673S-5, DS1673S-3, DS1673E-5, DS1673E-3 Datasheet (Dallas Semiconductor)

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DS1673

Portable System Controlle

FEATURES

 Provides Real Time Clock:

– Counts seconds, minutes, hours, date of

the month, month, day of the week, and
year with leap year compensation valid up
to 2100

– Power control circuitry supports system

power on from day/time alarm

 Microprocessor monitor:

– Halts microprocessor during power-fail
– Automatically restarts microprocessor

after power failure

– Monitors pushbutton for external override
– Halts and resets an out of control

microprocessor

 NV RAM control:

– Automatic battery backup and write

protection to external SRAM

 3-channel, 8-bit analog-to-digital converter
 Simple 3-wire interface
 +3.0 or +5.0V operation

PIN ASSIGNMENT

V

BAT

V

CCO

SCLK

I/O
CS

CEI

CEOL

CEOH

INT

GND

1
2

3
4
5
6
7
8
9
10

20-Pin TSSOP

20-Pin SOIC

20
19

18
17
16
15
14
13
12
11

ST
V

CC

X1
X2

IN0
IN1

IN2
RST
BLE
BHE

ORDERING INFORMATION

DS1673E - X 20-Pin TSSOP
DS1673S - X 20-Pin SOIC

3 +3V operation
5 +5V operation

DESCRIPTION

The Portable System Controller is a circuit which incorporates many of the functions necessary for low
power portable products integrated into one chip. The DS1673 provides a Real Time Clock, NV RAM
controller, microprocessor monitor, and a 3-channel, 8-bit analog-to-digital converter. Communication
with the DS1673 is established through a simple 3-wire interface.

The Real Time Clock (RTC) provides seconds, minutes, hours, day, date, month, and year information
with leap year compensation. The RTC also provides an alarm interrupt. This interrupt works when the
DS1673 is powered by the system power supply or when in battery backup operation so the alarm can be
used to wake up a system that is powered down.

1 of 20 050200

DS1673

Automatic backup and write protection of external SRAM is provided through the V

CEOH pins. The backup energy source used to power the RTC is also used to retain RAM data in the

absence of VCC through the V

pin. The chip enable outputs to RAM ( CEOL and CEOH) are controlled

CCO

, CEOL , and

CCO

during power transients to prevent data corruption.

The microprocessor monitor circuitry of the DS1673 provides three basic functions. First, a precision
temperature-compensated refe rence and comparator circuit monit ors the status of VCC. When an out-of­tolerance condition occurs, an internal power-fail signal is generated which forces the reset to the active
state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for
250 ms to allow the power supply and processor to stabilize. The second microprocessor monitor
function is pushbutton reset control. The DS1673 debounces a pushbutton input and guarantees an active
reset pulse width of 250 ms. The third function is a watchdog timer. The DS1673 has an internal timer
that forces the reset signals to the active state if the strobe input is not driven low prior to watchdog
time-out.

The DS1673 also provides a 3-channel, 8-bit successive approximation analog-to-digital converter. The
converter has an internal 2.55 volt (typical) reference voltage generated b y an on-board band-gap circuit.
The A/D converter is monotonic (no missing codes) and has an internal analog filter to reduce high
frequency noise.

OPERATION

The block diagram in Figure 1 shows the main elements of the DS1673. The following paragraphs
describe the function of each pin.

DS1673 BLOCK DIAGRAM Figure 1

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DS1673

SIGNAL DESCRIPTIONS

VCC, GND - DC power is provided to the device on these pins. VCC is the +3.0 volt or +5.0 volt input.

V

(Backup Power Supply) - Battery input for standard 3-volt lithium cell or other energy source.

BAT

SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface.

I/O (Data Input/Output) - The I/O pin is the bi-directional data pin for the 3-wire interface.

CS (Chip Select) - The Chip Select signal must be asserted high during a read or a write for

communication over the 3-wire serial interface.

V

(External SRAM Power Supply Output) - This pin is internally connected to VCC when VCC is

CCO

within nominal limits. However, during power-fail V
Switchover occurs when VCC drops below V

CCSW

.

INT (Interrupt Output) - The INT pin is an active high output of the DS1673 that can be used as an
interrupt input to a microprocessor. The INT output remains high as long as the status bit causing the
interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates when the
DS1673 is powered by VCC or V

BAT

.

is internally connected to the V

CCO

BAT

pin.

CEI (RAM Chip Enable In) - CEI must be driven low to enable the external RAM.

BLE (Byte Low Enable Input) - This pin when driven low activates the CEOL output if CEI is also

driven low.

BHE (Byte High Enable Input) - This pin when driven low activates the CEOH output if CEI is also

driven low.

CEOL (RAM Chip Enable Out Low) – Chip enable output for low order SRAM byte.

CEOH (RAM Chip Enable Out High) – Chip enable output for high order SRAM byte.

ST (Strobe Input) - The Strobe input pin is used in conjunction with the watchdog timer. If the ST pin

is not driven low within the watchdog time period, the

RST (Reset) - The RST pin functions as a microprocessor reset signal. This pin is driven low 1) when

is outside of nominal limits; 2) when the watchdog timer has “timed out”; 3) during the power-up

V

CC

reset period; and 4) in response to a pushbutton reset. The
input. When the

RST pin is driven low, the signal is debounced and timed such that a RST signal of at

RST pin is driven low.

RST pin also functions as a pushbutton reset

least 250 ms is generated. This pin has an internal 47 kΩ pullup resistor.

AIN0, AIN1, AIN2 (Analog Inputs) - These pins are the three analog inputs for the 3-channel analog-to­digital converter.

3 of 20

DS1673

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. For greatest accuracy, the DS1673 must
be used with a crystal that has a specified load capacitance of 6 pF. There is no need for external
capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they
and the crystal be guard-ringed with ground and that high frequency signals be kept awa y from the crystal
area. For more information on crystal selection and crystal layout considerations, please consult
Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.”

The DS1673 will not function without a crystal.

POWER-UP/POWER-DOWN CONSIDERATIONS

When VCC is applied to the DS1673 and reaches a level greater than V
device becomes fully accessible after t
When VCC drops below V

, the device is switched over to the V

CCSW

(250 ms typical). Before t

RPU

RPU

BAT

supply.

During power-up, when VCC returns to an in-tolerance condition, the RST pin is kept in the active state
for 250 ms (typical) to allow the power supply and microprocessor to stabilize.

(power-fail trip point), the

CCTP

elapses, all inputs are disabled.

ADDRESS/COMMAND BYTE

The command byte for the DS1673 is shown in Figure 2. Each data transfer is initiated by a command
byte. Bits 0 through 6 specify the address of the registers to be accessed. The MSB (bit 7) is the
Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is
selected if bit 7 is a 0 and a write operation is selected if bit 7 is a one. The address map for the DS1673
is shown in Figure 3.

ADDRESS/COMMAND BYTE Figure 2

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DS1673 ADDRESS MAP Figure 3

DS1673

CLOCK, CALENDAR AND ALARM

The time and calendar information is accessed by reading/writing the appropriate register bytes. Note
that some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note
that registers 0Fh to 7Fh are reserved. These registers will always read 0 regardless of how they are
written. The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD)
format. The DS1673 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as
the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5
is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hou r bit (20-23
hours).

The DS1673 also contains a time of day alarm. The alarm registers are located in registers 07h to 0Ah.
Bit 7 of each of the alarm re gisters are mask bits (see T able 1). When all of the mask bits are logic 0, a n
alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of
the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm
mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute
alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarm
will occur every second.

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DS1673

TIME OF DAY ALARM BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS MINUTES HOURS DAYS

1 1 1 1 Alarm once per second.
0 1 1 1 Alarm when seconds match.
0 0 1 1 Alarm when minutes and seconds match.
0 0 0 1 Alarm when hours, minutes and seconds match.
0 0 0 0 Alarm when day, hours, minutes and seconds

match.

SPECIAL PURPOSE REGISTERS

The DS1673 has two additional registers (control register and status register) that control the Real Time
Clock and interrupts.

CONTROL REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

EOSC

EOSC (Enable Oscillator) - This bit, when set to logic 0 will start the oscillator. When this bit is set to a

logic 1, the oscillator is stopped and the DS1673 is placed into a low-power standby mode with a current
drain of less than 200 nanoamps when in battery back-up mode. When the DS1673 is powered by VCC,

WP AIS1 AIS0 0 0 0 AIE

the oscillator is always on regardless of the status of the EOSC bit; however, the Real Time Clock is
incremented only when EOSC is a logic 0.

WP (Write Protect) - Before an y write operation to the Real Time Clock or any other registers, this bit
must be logic 0. When high, the write protect bit prevents a write operation to any register.

AIS0-AIS1 (Analog Input Select) - These 2 bits are used to determine the analog input for the analog-to­digital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.

AIE (Alarm Interrupt Enable) - When set to a logic 1, this bit permits the Interrupt Request Flag
(IRQF) bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not
initiate the INT signal.

ANALOG INPUT SELECTION Table 2

AIS1 AIS0 ANALOG INPUT

0 0 NONE
01 AIN0
10 AIN1
11 AIN2

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DS1673

STATUS REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CULOBAT00000IRQF

CU (Conversion Update In Progress) - When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488 µs. When this bit is a 0, an update to the ADC Register will not occur for at
least 244 µs.

LOBAT (Low Battery Flag) - This bit reflects the status of the backup power source connected to the
V

pin. When V

BAT

is greater than 2.5 volts, LOBAT is set to a logic 0. When V

BAT

is less than

BAT

2.3 volts, LOBAT is set to a logic 1.

IRQF (Interrupt Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.

NONVOLATILE SRAM CONTROLLER

The DS1673 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the V
pin. The DS1673 was specifically designed with the Intel 80186 and 386EX microprocessors in mind.
As such, the DS1673 has the capability to provide access to the external SRAM in either b yte-wide or
word-wide format. This capability is provided by the chip enable scheme. Three input signals and two

output signals are used for enabling the ex ternal SRAM(s) (see Figure 4). CEI (chip enable in), BHE
(byte high enable), and BLE (byte low enable ) are used for enabling either one or two ex ternal SRAMs
through the CEOL (chip en able low) and the CEOH (chip enable high) outputs. Table 3 illustrates the

function of these pins.

CCO

The DS1673 nonvolatilizes the external SRAM(s) by write-protecting the SRAM(s) and by providing a
back-up power supply in the absence of VCC. When VCC falls below VPF, access to the external SRAM(s)

are prohibited by forcing CEOL and CEOH high regardless of the level of CEI , BLE , and BHE . Upon
power-up, access is prohibited until the end of t

RPU

.

EXTERNAL SRAM CHIP ENABLE Table 3

CEI BHE BLE CEOL CEOH

0 0 0 0 0 Word transfer
0 0 1 1 0 Byte transfer in upper half of data bus (D15-D8)
0 1 0 0 1 Byte transfer in lower half of data bus (D7-D0)
0 1 1 1 1 External SRAMs disabled
1 X X 1 1 External SRAMs disabled

FUNCTION

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DS1673

EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1673 Figure 4

MICROPROCESSOR MONITOR

The DS1673 monitors three vital conditions for a microprocessor: power supply, software execution, and
external override.

First, a precision temperature-compensated reference and comparator circuit monit ors the status of VCC.
When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the

RST pin to the active state, thus warning a processor-based system of impending power failure. When

VCC returns to an in-tolerance condition upon power-up, the reset signal is kept in the active state for
250 ms (typical) to allow the power supply and microprocessor to stabilize. Note, however, that if the

EOSC bit is set to a logic 1 (to disable the oscillator during battery back-up mode), the reset signal will be

kept in an active state for 250 ms plus the start-up time of the oscillator.

The second monitoring function is push-button reset control. The DS1673 provides for a pushbutton
switch to be connected to the RST output pin. When the DS1673 is not in a reset cycle, it continuously
monitors the

RST signal for a low going edge. If an edge is detected, the DS1673 will debounce the

switch by pulling the RST line low. After the internal 250 ms timer has expired, the DS1673 will
continue to monitor the
looking for a rising edge. Upon detecting release, the DS1673 will force the

RST line. If the line is still low, the DS1673 will continue to monitor the line

RST line low and hold it

low for 250 ms.

The third microprocessor monitoring function provided by the DS1673 is a watchdog timer. The
watchdog timer function forces

RST to the active state w hen the ST input is not stimulated within the

predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.
The time delay can be set to 250 ms, 500 ms, or 1000 ms (see Figure 5). If TD0 and TD1 are both set to
zero, the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set

time period as soon as

RST is inactive. The default setting is for the watchdog timer to be enabled with

1000 ms time delay. If a high-to-low transition occurs on the

ST input pin prior to time-out, the

watchdog timer is reset and begins to time-out again. If the watchdog timer is allowed to time-out, then

RST signal is driven to the active state for 250 ms (typical). The ST input can be derived from

the
microprocessor address signals, data signals, and/or control signals. To guarantee that the watchdog
timer does not time-out, a high-to-low transition must occur at or less than the minimum period.

8 of 20

DS1673

WATCHDOG TIME-OUT CONTROL Figure 5

WATCHDOG REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

000000TD1TD0

WATCHDOG REGISTER

TD1 TD0 WATCHDOG TIME-OUT

0 0 WATCHDOG DISABLED
0 1 250 ms
1 0 500 ms
1 1 1000 ms

ANALOG-TO-DIGITAL CONVERTER

The DS1673 provides a 3-channel, 8-bit analog-to-digital converter. The A/D reference voltage (2.55V
typical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided
through the AIN0, AIN1, and AIN2 pins. The A/D converter is monotonic (no missing codes) and uses a
successive approximation technique to convert the analog signal into a digital code.

An A/D conversion is the process of assigning a digital code to an analog input voltage. This code
represents the input value as a fraction of the full-scale voltage (FSV) range. Thus the FSV range is then
divided by the A/D converter into 256 codes (8 bits). The FSV range is bounded by an upper limit equal
to the reference voltage and the lower limit which is ground. The DS1673 has a FSV of 2.55V (typical)
which provides a resolution of 10 mV. An input voltage equal to the reference voltage converts to FFh
while an input voltage equal to ground converts to 00h. The relative linearity of the A/D converter is
±0.5 LSB.

The A/D converter selects from one of three different analog inputs (AIN0 - AIN2). The input that is
selected is determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the
specific analog input that is selected by these 2 bits. Note also that the converter can be turned off by
these bits to reduce power. When the A/D is turned on by setting AIS0 and AIS1 to any value other than
0,0 the analog input voltage is converted and written to the ADC Register within 488 µs. An internal
analog filter at the input reduces high frequency noise. Subsequent updates occur approximately every
10 ms. If AIS0 and/or AIS1 are changed, updates will occur at the next 10 ms conversion time.

The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can
be read. When this bit is a 1, an update to the ADC Register will occur within 488 µs maximum.
However, when this bit is 0 an update will not occur for at least 244 µs. The CU bit should be polled
before reading the ADC Register to insure that the c ontents are stable during a read c ycle. Once a read
cycle to the ADC Register has been started, the DS1673 will not update that register until the read cycle
has been completed. It should also be mentioned that taking CS low will abort the read cycle and will
allow the ADC Register to be updated.

Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the
completion of that conversion.

9 of 20

DS1673

CU BIT TIMING Figure 6

3-WIRE SERIAL INTERFACE

Communication with the DS1673 is accomplished through a simple 3-wire interface consisting of the
Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.

All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data
must be valid during the rising edge of the clock and data bits are output on the falling edge of the clock.
If the CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state.

Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the
address/command byte to specify a read or write to a specific register followed by 1 or more bytes of
data. The address byte is always the first byte entered after CS is driven high. The most significant bit

(RD /WR) of this byte determines if a read or write will take place. If this bit is 0, one or more read
cycles will occur. If this bit is 1, one or more write cycles will occur.

Data transfers can occur 1 byte at a time or in multiple byte burst mode. After CS is driven high an
address is written to the DS1673. After the address, 1 or more data b ytes can be read or written. For a
single-byte transfer 1 byte is read or written and then CS is driven low. For a multiple-byte transfer,
multiple bytes can be read or written to the DS1673 after the address has been written. Each read or write
cycle causes the register address to automatically increment. Incrementing continues until the device is
disabled. After accessing register 0Eh, the address wraps to 00h.

Data transfer for single-byte transfer and multiple-byte burst transfer is illustrated in Figures 7 and 8.

10 of 20

SINGLE-BYTE DATA TRANSFER Figure 7

MULTIPLE-BYTE BURST TRANSFER Figure 8

DS1673

11 of 20

DS1673

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature See J-STD-020A

* This is a stress rating only and functional operation of the device at these or an y other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Power Supply Voltage
5 Volt Operation
Power Supply Voltage
3 Volt Operation
Input Logic 1 V
Input Logic 0 V
Battery Voltage V

V

V

CC

CC

IH
IL

BAT

4.5 5.0 5.5 V 1

2.7 3.0 3.3 V 1

2.0 VCC+0.3 V 1

-0.3 +0.8 V 1

2.5 3.7 V 1

DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=5.0V ±=10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage I
CS Leakage I
Logic 1 Output V
Logic 0 Output V
Active Supply Current (CS=VCC -0.2) I
A/D Converter Current I
Standby Current (CS=VIL)I
Oscillator Current I
Battery Standby Current (Oscillator Off) I

Internal RST Pullup Resistor
VCC Trip Point V
VCC Switchover V
A/D Reference Voltage V
Pushbutton Detect PB
Pushbutton Release PB
Output Voltage V
V

Output Current (Source=VCC)I

CCO

V

Output Current (Source=V

CCO

)I

BAT

LI

LO

OH

OL
CCA
ADC
CCS
OSC
BAT

R

P

CCTP

CCSW

ADC

DV
RD

CCO
CCO1
CCO2

-1 +1
150

µA
µA

7

2.4 V 2

0.4 V 3

1.5 2.0 mA 4
500
300

µA
µA

5
6

300 500 nA

200 nA

35 47 60

kΩ

4.25 4.35 4.50 V

2.60 2.70 2.80 V 12

2.47 2.55 2.63 V

0.8 2.0 V

0.3 0.8 V

VCC-0.3 V 11

150 mA 13
150

µA

14

12 of 20

DS1673

DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=3.0V ±=10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage I
CS Leakage I
Logic 1 Output V
Logic 0 Output V
Active Supply Current (CS=VCC -0.2) I
A/D Converter Current I
Standby Current (CS=VIL)I
Oscillator Current I
Battery Standby Current (Oscillator Off) I

Internal RST Pullup Resistor
VCC Trip Point V
VCC Switchover V
A/D Reference Voltage V
Pushbutton Detect PB
Pushbutton Release PB
Output Voltage V
V

Output Current (Source=VCC)I

CCO

V

Output Current (Source=V

CCO

)I

BAT

LI

LO

OH

OL

CCA

ADC

CCS
OSC
BAT

R

P

CCTP

CCSW

ADC

DV
RD

CCO
CCO1
CCO2

-1 +1
150

µA
µA

7

2.4 V 2

0.4 V 3

0.75 1.0 mA 4
200
100

µA
µA

5
6

300 500 nA

200 nA

35 47 60

kΩ

2.5 2.6 2.7 V

2.30 2.40 2.50 V 12

2.47 2.55 2.63 V

0.8 2.0 V

0.3 0.8 V

VCC-0.3 V 11

80 mA 13

100

µA

14

CAPACITANCE (tA=25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C
I/O Capacitance C
Crystal Capacitance C

I

I/O

X

10 pF
15 pF

6pF

13 of 20

DS1673

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=5.0V ±=10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Data to Clock Setup t
CLK to Data Hold t
CLK to Data Delay t
CLK to Low Time t
CLK to High Time t
CLK Frequency t

DC
CDH
CDD

CL

CH

CLK

CLK Rise and Fall tR, t
CS to CLK Setup t
CLK to CS Hold t
CS Inactive Time t
CS to I/O High-Z t
VCC Slew Rate (4.5V to 2.3V) t
VCC Slew Rate (2.3V to 4.5V) t

VCC Detect to RST (VCC Falling)
Reset Active Time t

CC
CCH
CWH

CDZ

t

RPD
RST

F
R

Pushbutton Debounce PB

t

VCC Detect to RST (VCC Rising)

ST Pulse Width

Chip Enable Propagation Delay to

RPU

t

t

CED

ST

External SRAM
Nominal Voltage to VCC Switchover

t

FB

Fall Time

F

DB

50 ns 8
70 ns 8

200 ns 8, 9, 10
250 ns 8
250 ns 8

2.0 MHz 8

500 ns

1

µs

8

60 ns 8

1

µs

8

70 ns 8
1ms
0ns

100 ns

250 ms 15
250 ms 15
250 ms 15, 16

20 ns

815 ns

200

µs

14 of 20

DS1673

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=3.0V ±=10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Data to Clock Setup t
CLK to Data Hold t
CLK to Data Delay t
CLK to Low Time t
CLK to High Time t
CLK Frequency t

DC
CDH
CDD

CL

CH

CLK

CLK Rise and Fall tR, t
CS to CLK Setup t
CLK to CS Hold t
CS Inactive Time t
CS to I/O High-Z t

CC
CCH
CWH

CDZ

VCC Slew Rate (2.7V to 2.3V) t
VCC Slew Rate (2.3V to 2.7V) t

t

VCC Detect to RST (VCC Falling)
Reset Active Time t

RPD
RST

Pushbutton Debounce PB

t

VCC Detect to RST (VCC Rising)

ST Pulse Width

Chip Enable Propagation Delay to

RPU

t

t

CED

ST

External SRAM
Nominal Voltage to VCC Switchover

t

FB

Fall Time

F

F
R

DB

150 ns 8
210 ns 8

600 ns 8, 9, 10
750 ns 8
750 ns 8

0.667 MHz 8
1500 ns

3

µs

8

180 ns 8

3

µs

8

210 ns 8

300

µs

0ns

200 ns

250 ms 15
250 ms 15
250 ms 15, 16

40 ns

825 ns

300

µs

15 of 20

TIMING DIAGRAM: READ DATA Figure 9

TIMING DIAGRAM: WRITE DATA Figure 10

DS1673

16 of 20

PUSHBUTTON RESET Figure 11

POWER-UP Figure 12

POWER-DOWN Figure 13

DS1673

17 of 20

DS1673

NOTES:

1. All voltages are referenced to ground.

2. Logic 1 voltages are specified at a source current of 0.4 mA at VCC=3.0V, VOH=VCC for capacitive

loads.

3. Logic 0 voltages are specified at a sink current of 1.5 mA at VCC=3.0, VOL=GND for capacitive

loads.

4. I

is specified with outputs open, CS set to a logic 1, SCLK=500 kHz, oscillator enabled, and D/A

CCA

converter enabled.

5. I

6. I

is specified with CS, V

ADC

is specified with CS, V

CCS

open and I/O, SCLK at logic zero. A/D converter is enabled.

CCO

open and I/O, SCLK at logic zero. A/D converter is disabled.

CCO

7. CS has a 40 kΩ pull-down resistor to ground.

8. Measured at VIH=2.0V or VIL=0.8V and 10 ns maximum rise and fall time.

9. Measured at VOH=2.4V or VOL=0.4V.

10. Load capacitance= 25 pF.

11. I

12. V

13. Current from VCC input pin to V

=100 mA, VCC > V

CCO

switchover from VCC to V

CCO

CCTP

.

occurs when VCC drops below the lower of V

BAT

output pin.

CCO

CCSW

and V

BAT

.

14. Current from V

input pin to V

BAT

output pin.

CCO

15. Timebase is generated by very accurate crystal oscillator. Accuracy of this time period is based on

the crystal that is used. A typical crystal with a specified load capacitance of 6 pF will provide an
accuracy within ±100 ppm over the 0°C to 70°C temperature range.

16. If the EOSC bit in the Control Register is set to a logic 1, t

is equal to 250 ms plus the start-up

RPU

time of the crystal oscillator.

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20-PIN TSSOP (PRELIMINARY)

DS1673

DIM MIN MAX

A MM

A1

MM

A2

MM
C MM
L MM

e1

MM
B MM
D MM
E MM

GMM

H MM

phi

-1.10

0.05 -

0.75 1.05

0.09 0.18

0.50 0.70

0.65 BSC

0.18 0.30

6.40 6.90

4.40 NOM

0.25 REF

6.25 6.55

0° 8°

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DS1673

20-PIN SOIC PACKAGE

The chamfer on the body is optional. If it is not present, a terminal 1 identifier must be positioned so that
1/2 or more of its area is contained in the hatched zone.

PKG 20-PIN

DIM MIN MAX

A IN.

MM

A1 IN.

MM

A2 IN.

MM

b IN.

MM

C IN.

MM

D IN.

MM

e IN.

MM

E1 IN.

MM

H IN.

MM

L IN.

MM

ΘΘΘΘ

0.094

2.38

0.004

0.102

0.089

2.26

0.013

0.33

0.009

0.229

0.498

12.65

0.050 BSC

0.290

7.37

0.398

10.11

0.016

0.406

0° 8°

0.105

2.68

0.012

0.30

0.095

2.41

0.020

0.51

0.013

0.33

0.511

12.99

1.27 BSC

0.300

7.62

0.416

10.57

0.040

1.20

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