Datasheet DS1306N, DS1306EN, DS1306E, DS1306 Datasheet (Dallas Semiconductor)

www.dalsemi.com

DS1306

Serial Alarm Real Time Clock (RTC)

FEATURES

 Real time clock counts seconds, minutes,

hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 2100

 96-byte nonvolatile RAM for data storage
 Two Time of Day Alarms - programmable on

combination of seconds, minutes, hours, and
day of the week

 1 Hz and 32.768 kHz clock outputs
 Serial interface supports Motorola Serial

Peripheral Interface (SPI) serial data ports or
standard 3-wire interface

 Burst Mode for reading/writing successive

addresses in clock/RAM

 Dual power supply pins for primary and

backup power supplies

 Optional trickle charge output to backup

supply

 2.0 - 5.5V operation
 Optional industrial temperature range

-40°C to +85°C

 Available in space-efficient 20-pin TSSOP

package

 Recognized by Underwriters Laboratory

ORDERING INFORMATION

DS1306 16-Pin DIP
DS1306N 16-Pin DIP (Industrial)
DS1306E 20-Pin TSSOP
DS1306EN 20-Pin TSSOP (Industrial)

PIN ASSIGNMENT

V

CC2

V

BAT

X1

NC

X2

NC
INT0
INT1

1 Hz

GND

1
2
3
4
5
6
7
8
9
10

DS1306 20-Pin TSSOP (173 mil)

CC2

BAT

X1
X2

1
2

3
4

5
6

7
8

V
V

INT0
INT1

1 Hz

GND

DS1306 16-Pin DIP (300 mil)

20
19
18
17
16
15
14
13
12
11

16
15

14
13

12
11

10

9

V

CC1

NC
32 kHz
V

CCIF

SDO
SDI
SCLK
NC
CE
SERMODE

V

CC1

32 kHz
V

CCIF

SDO
SDI

SCLK
CE
SERMODE

PIN DESCRIPTION

V

– Primary Power Supply

CC1

V

– Backup Power Supply

CC2

– +3V Battery Input

V

BAT

V

– Interface Logic Power Supply

CCIF

Input
GND – Ground
X1, X2 – 32.768 kHz Crystal Connection

INT0 – Interrupt 0 Output

INT1 – Interrupt 1 Output
SDI – Serial Data In
SDO – Serial Data Out
CE – Chip Enable
SCLK – Serial Clock
SERMODE – Serial Interface Mode
1 Hz - 1 Hz Output
32 kHz - 32.768 kHz Output

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DS1306

DESCRIPTION

The DS1306 Serial Alarm Real Time Clock provides a full BCD clock calendar which is accessed via a
simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically adjusted for months with less than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with
AM/PM indicator. In addition 96 bytes of nonvolatile RAM are provided for data storage.

An interface logic power supply input pin (V

) allows the DS1306 to drive SDO and 32 kHz pins to a

CCIF

level that is compatible with the interface logic. This allows an easy interface to 3-volt logic in mixed
supply systems. The DS1306 offers dual power supplies as well as a battery input pin. The dual power
supplies support a programmable trickle charge circuit which allows a rechar geable energy source (such
as a super cap or rechargeable battery) to be used for a backup supply. The V

pin allows the device to

BAT

be backed up by a non-rechargeable battery. The DS1306 is fully operational from 2.0 to 5.5 volts.

Two programmable time of day alarms are provided by the DS1306. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1 Hz and
a 32 kHz clock output are also available.

The DS1306 supports a direct interface to Motorola SPI serial data ports or standard 3-wir e interfac e. An
easy-to-use address and data format is implemented in which data transfers can occur 1 byte at a time or
in multiple-byte burst mode.

OPERATION

The block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The following
paragraphs describe the function of each pin.

DS1306 BLOCK DIAGRAM Figure 1

2 of 20

SIGNAL DESCRIPTIONS

V

- DC power is provided to the device on this pin. V

CC1

V

- This is the secondar y power supply pin. In systems using the trickle charger, the rechargeable

CC2

energy source is connected to this pin.

V

- Battery input for any standard 3-volt lithium cell or other energy source.

BAT

is the primary power supply.

CC1

DS1306

(Interface Logic Power Supply Input) - The V

V

CCIF

pin allows the DS1306 to drive SDO and

CCIF

32 kHz output pins to a level that is compatible with the i nterface l o gic, thus all owin g an easy interface to
3-volt logic in mixed supply systems. This pin is physically connected to the sou rce connection of the p­channel transistors in the output buffers of the SDO and 32 kHz pins.

SERMODE (Serial Interface Mode Input) - The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to VCC, Motorola SPI communication is selected.

SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.

SDI (Serial Data Input) - When SP I communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).

SDO (Serial Data Output) - W hen SPI communication is selected, the SDO pin is the serial dat a output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI
and SDO pins function as a single I/O pin when tied together).

CE (Chip Enable) - The Chip Enable signal must be asserted high during a read or a write for both
3-wire and SPI communication. This pin has an internal 55k pull-down resistor (typical).

INT0 (Interrupt 0 Output) - The INT0 pin is an active low output of the DS1306 that c an be used as an

interrupt input to a processor. The

INT0 pin can be programmed to be asserted by Alarm 0. The INT0

pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt
enable bit is set. The

INT0 pin operates when the DS1306 is powered by V

CC1

, V

CC2

, or V

. The INT0

BAT

pin is an open drain output and requires an external pullup resistor.
1 Hz (1 Hz Clock Output) - The 1 Hz pin provides a 1 Hz squarewave output. This output is active

when the 1 Hz bit in the control register is a logic 1.

Both

INT0 and 1 Hz pins are open drain outputs. The interrupt, 1 Hz signal, and the internal clock

continue to run regardless of the level of VCC (as long as a power source is present).

INT1 (Interrupt 1 Output) - The INT1 pin is an active high output of the DS1306 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by alarm 1. When an
alarm condition is present, the INT1 pin generates a 62.5 ms active high pulse. The INT1 pin operates
only when the DS1306 is powered by V
V

CC2

or V

. When inactive, the INT1 pin is internally pulled low.

BAT

CC2

or V

. When active, the INT1 pin is internally pulled up to

BAT

3 of 20

DS1306

32 kHz (32.768 kHz Clock Output) - The 32 kHz pin provides a 32.768 kHz output. This signal is
always present.

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6 pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
with Dallas Real Time Clocks.” The DS1306 can also be driven by an external 32.768 kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

RTC AND RAM ADDRESS MAP

The address map for the RTC and RAM registers of the DS1306 is shown in Figure 2. Data is written to
the RTC by writing to address locations 80h to 9Fh and is written to the RAM by writing to address
locations A0h to FFh. RTC data is read by reading address locations 00h to 1Fh and RAM data is read by
reading address locations 20h to 7Fh.

ADDRESS MAP Figure 2

00H

1FH
20H

7FH
80H

9FH
A0H

FFH

CLOCK/CALENDAR

READ ADDRESSES ONLY

96-BYTES USER RAM

READ ADDRESSES ONLY

CLOCK/CALENDAR

WRITE ADDRESSES ONLY

96-BYTES USER RAM

WRITE ADDRESSES ONLY

4 of 20

DS1306

CLOCK, CALENDAR, AND ALARM

The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time, calendar, and alarm are set or initialized by writing
the appropriate register bytes. Note that some bits are set to 0. These bits will always read 0 regardless
of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh ar e reserved.
These registers will always read 0 regardless of how they are written. The contents of the time, calendar,
and alarm registers are in the Binary-Coded Decimal (BCD) format.

RTC REGISTERS Figure 3
RTC REGISTERS DS1306

HEX ADDRESS

READ WRITE

00H 80H 0 10 SEC SEC 00-59
01H 81H 0 10 MIN MIN 00-59

03H 83H 0 0 0 0 0 DAY 01-07
04H 84H 0 0 10 DATE DATE 1-31
05H 85H 0 0 10 MONTH MONTH 01-12
06H 86H 10 YEAR YEAR 00-99

07H 87H M 10 SEC ALARM SEC ALARM 00-59
08H 88H M 10 MIN ALARM MIN ALARM 00-59

0AH 8AH M 0 0 0 0 DAY ALARM 01-07

0BH 8BH M 10 SEC ALARM SEC ALARM 00-59
0CH 8CH M 10 MIN ALARM MIN ALARM 00-59

0EH 8EH M 0 0 0 0 DAY ALARM 01-07

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RANGE

10 01-12 + P/A02H 82H 0 12/2

10 HR HOURS

4

P/A

Alarm 0

10 01-12 + P/A09H 89H M 12/2

10 HR HOUR ALARM

4

P/A

Alarm 1

10 01-12 + P/A0DH 8DH M 12/2

10 HR HOUR ALARM

4

P/A

00-23

00-23

00-23

0FH 8FH CONTROL REGIST ER
10H 90H STATUS REGISTER
11H 91H TRICKLE CHARGER REGISTER

12-1FH 92-9FH RESERVED

NOTE:

Range for alarm registers does not include mask’m’ bits.

5 of 20

DS1306

The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).

The DS1306 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to registers
87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. Bit 7 of each of the time
of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time of day alarm
will only occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when bit 7 of the
day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7 of the day and
hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minute when bit 7 of
the day, hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and
seconds alarm registers is set to a logic 1, an alarm will occur every second.

TIME OF DAY ALARM MASK BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS MINUTES HOURS DAYS

1 1 1 1 Alarm once per second
0 1 1 1 Alarm when seconds match
0 0 1 1 Alarm when minutes and seconds match
0 0 0 1 Alarm when hours, minutes, and seconds match
0 0 0 0 Alarm when day, hours, minutes, and seconds

match

SPECIAL PURPOSE REGISTERS

The DS1306 has three additional registers (Control Register, Status Register, and Trickle Charger
Register) that control the real time clock, interrupts, and trickle charger.

CONTROL REGISTER (READ 0FH, WRITE 8FH)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0 WP 0 0 0 1 Hz AIE1 AIE0

WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.

1 Hz (1 Hz output enable) - This bit controls the 1 Hz output. When this bit is a logic 1, the 1 Hz output
is enabled. When this bit is a logic 0, the 1 Hz output is high Z.

AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0. When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the

AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does
not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.

INT0 signal.

6 of 20

DS1306

STATUS REGISTER (READ 10H)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

000000IRQF1IRQF0

IRQF0 (Interrupt 0 Request Flag) - A logic 1 in the Interrupt Request Flag bi t i ndicates t hat the cu rrent
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the

INT0 pin will go low.

IRQF0 is cleared when any of the Alarm 0 registers are read or written.

IRQF1 (Interrupt 1 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 1 registers. If the AIE1 bit is also a logic 1, the INT1 pin will generate a

62.5- ms active high pulse. IRQF1 is cleared when any of the Alarm 1 registers are read or written.

TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)

This register controls the trickle charge characteristics of the DS1306. The simplified schematic of
Figure 4 shows the basic components of the trickle charger. The trickle ch arge select (TCS) bits (bits
4-7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern o f
1010 will enable the trickle charger. All other patterns will disable the trickle charger. The DS1306
powers up with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether one
diode or two diodes are connected between V
10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The
RS bits select the resistor that is connected between V
resistor select (RS) bits as shown in Table 2.

CC1

and V

. If DS is 01, one diode is selected. If DS is

CC2

CC1

and V

. The resistor is selected by the

CC2

PROGRAMMABLE TRICKLE CHARGER Figure 4

7 of 20

DS1306

TRICKLE CHARGER RESISTOR SELECT Table 2

RS BITS RESISTOR TYPICAL VALUE

00 None None
01 R1
10 R2
11 R3

If RS is 00, the trickle charger is disabled independently of TCS.

Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5 volts is applied to V
connected to V
between V

CC1

. Also assume that the trickle charger has been enabled with one diode and resister R1

CC2

and V

I

MAX

. The maximum current I MAX would therefore be calculated as follows:

CC2

= (5.0V - diode drop)/R1

~ (5.0V - 0.7V)/2 kΩ
~ 2.2 mA

2 kΩ
4 kΩ
8 kΩ

and a super cap is

CC1

Obviously, as the super cap charges, the voltage drop between V

CC1

and V

will decrease and therefore

CC2

the charge current will decrease.

POWER CONTROL

Power is provided through the V
are illustrated in Figure 5. Configuration 1 shows the DS1306 being backed up by a non-rechargeable
energy source such as a lithium battery. In this configuration, the system power supply is connected to
V

CC1

and V

is grounded. The DS1306 will be write-protected if V

CC2

Configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. In this case, the
V

pin is grounded, V

BAT

is connected to the primary power supply, and V

CC1

secondary supply (the rechargeable energy source). The DS1306 will operate from the larger of V
V

. When V

CC2

less than V

is greater than V

CC1

CC2

, V

will power the DS1306. The DS1306 does not write-protect itself in this

CC2

configuration.

Configuration 3 shows the DS1306 in battery operate mode where the device is powered only b y a singl e
battery. In this case, the V

CC1

and V

Only these three configurations are allowed. Unused supply pins must be grounded.

, V

CC1

CC2

, and V

CC2

+ 0.2 volt (typical), V

pins are grounded and the battery is connected to the V

BAT

pins. Three different power supply configurations

BAT

is less than V

CC1

CC2

will power the DS1306. When V

CC1

.

BAT

is connected to the

CC2

CC1

CC1

pin.

or

is

SERIAL INTERFACE

The DS1306 offers the flexibility to choose between two serial interface modes. The DS1306 can
communicate with the SPI interface or with a standard 3-wire interface. The interface method used is
determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected.
When this pin is connected to ground, standard 3-wire communication is selected.

SERIAL PERIPHERAL INTERFACE (SPI)

The serial peripheral interface (SPI) is a synchronous bus for address and data tr ansfer and is used when
interfacing with the SPI bus on specific Motorola microcontrollers such as the 68HC05C4 and the
68HC11A8. The SPI mode of serial communication is selected by tying the SERMODE pin to V

8 of 20

CC

.

DS1306

Four pins are used for the SPI. The four pins are the SDO (Serial Data Out), SDI (S erial Data In), CE
(Chip Enable), and SCLK (Serial Clock). The DS1306 is the slave device in an SPI application, with the
microcontroller being the master.

The SDI and SDO pins are the serial data input and output pins for the DS1306, respectively. The CE
input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data
movement between the master (microcontroller) and the slave (DS1306) devices.

The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data
transfer to any device on the SPI bus. The inactive clock polarity is programmable in some
microcontrollers. The DS1306 offers an important feature in that the level of the inactive clock is
determined by sampling SCLK when CE becomes active. Therefore either SCLK polarity can be
accommodated. Input data (SDI) is latched on the internal strobe edge and output data (SDO) is shifted
out on the shift edge (see Table 3 and Figure 6). There is one clock for each bit transfe rred. Address and
data bits are transferred in groups of eight.

POWER SUPPLY CONFIGURATIONS FOR THE DS1306 Figure 5

Configuration 1: Backup Supply is a Non-Rechargeable Lithium Battery

Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor

Configuration 3: Battery Operate Mode

9 of 20

FUNCTION TABLE Table 3

MODE CE SCLK SDI SDO

Disable Reset L Input Disabled Input Disabled High Z
Write H CPOL=1*

CPOL=0

Read H CPOL=1

CPOL=0

* CPOL is the “Clock Polarity” bit that is set in the control register of the microcontroller.

** SDO remains at High Z until 8 bits of data are ready to be shifted out during a read.

Data Bit Latch High Z

X Next data bit

shift**

NOTE:

CPHA bit polarity (if applicable) may need to be set accordingly.

SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER
CLOCK POLARITY (CPOL) Figure 6

DS1306

10 of 20

DS1306

ADDRESS AND DATA BYTES

Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data
output (SDO). Any transfer requires the address of the byte to specify a write or re ad to either a RTC or
RAM location, followed by 1 or more bytes of data. Data is transferred out of the SDO for a read
operation and into the SDI for a write operation (see figures 7 and 8).

SPI SINGLE-BYTE WRITE Figure 7

SPI SINGLE-BYTE READ Figure 8

* SCLK can be either polarity.

The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of
this byte determines if a read or write will take place. If A7 is 0, one or more read cycles will occur. If
A7 is 1, one or more write cycles will occur.

Data transfers can occur 1 byte at a time or in multiple-byte burst mode. After CE is driven high an
address is written to the DS1306. After the address, 1 or more data bytes can be written or read. For a
single-byte transfer 1 byte is read or written and then CE is driven low. For a multiple-byte transfer,
however, multiple bytes can be read or written to the DS1306 after the address has been written. Each
read or write cycle causes the RTC register o r RAM address to automatically increment. Increm enting
continues until the device is disabled. When the RTC is selected, the address wraps to 00h after
incrementing to 1Fh (during a read) and wraps to 80h after increm enting to 9Fh (during a write). When
the RAM is selected, the address wraps to 20h after incrementing to 7Fh (during a read) and wraps to
A0h after incrementing to FFh (during a write).

11 of 20

DS1306

SPI MULTIPLE-BYTE BURST TRANSFER Figure 9

3-WIRE INTERFACE

The 3-wire interface mode operates similar to the SPI mode. However, in 3-wire mode there is one I/O
instead of separate data in and data out signals. The 3-wire interface consists of the I/O (SD I and SDO
pins tied together), CE, and SCLK pins. In 3-wire mode, each byte is shifted in LSB first unlike SPI
mode where each byte is shifted in MSB first.

As is the case with the SPI mode, an address byte is written to the device followed by a single data byte
or multiple data bytes. Figure 10 illustrates a read and write cycle. In 3-wire mode, data is input on the
rising edge of SCLK and output on the falling edge of SCLK.

3-WIRE SINGLE BYTE TRANSFER Figure 10

SINGLE BYTE READ

RST

SCLK

I/O

SINGLE BYTE WRITE

RST

SCLK

I/O

I/O is SDI and SDO tied together
In burst mode, RST is kept high and additional SCLK cycles are sent until the end of the burst.

12 of 20

DS1306

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.5V to +7.0V
Operating Temperature 0°C to 70°C or –40°C to +85°C for Industrial (IND)
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds (DIP)

See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices

* This is a stress rating only and functional operation of the d evice at these or an y other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(0°C to 70°C or –40° to +85°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

V

Supply Voltage V

CC1

, V

CC2

V

Logic 1 Input V
Logic 0 Input V
V

Battery Voltage V

BAT

V

Supply Voltage V

CCIF

CC1

CC2

IH

IL

BAT

CCIF

,

VCC=2.0V -0.3 +0.3

VCC=5V -0.3 +0.8

2.0 5.5 V 1, 8

2.0 VCC+0.3 V 1
V1

2.0 5.5 V 1

2.0 5.5 V 14

DC ELECTRICAL CHARACTERISTICS

(0°C to 70°C or –40°C to +85°C; V

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage
Output Leakage

Logic 0 Output V

Logic 1 Output V

Logic 1 Output Current (INT1 pin)

V

Active Supply Current I

CC1

V

Timekeeping Current I

CC1

V

Active Supply Current I

CC2

V

Timekeeping Current I

CC2

I

INT1

*Unless otherwise noted.

I

LI

I

LO

OL

OH

OH

CC1A

CC1T

CC2A

CC2T

VCC=2.0 0.4
VCC=5V 0.4

V

=2.0V 1.6

CCIF

V

=5V 2.4

CCIF

,

(V

, V

CC2

BAT

-0.3V

V

=2.0V 0.425

CC1

V

=5V 1.28

CC1

V

=2.0V 25.3

CC1

V

=5V 81

CC1

V

=2.0V 0.4

CC2

V

=5V 1.2

CC2

V

=2.0V 0.4

CC2

V

=5V 1

CC2

-100 +500

-1 1

)

-100

= 2.0 to 5.5V*)

CC

µA
µA

V2

V12

µA

mA 4, 9

µA

mA 4, 10

µA

3,9

3, 10

13 of 20

DC ELECTRICAL CHARACTERISTICS (cont’d)

DS1306

(0°C to 70°C or –40°C to +85°C; V

= 2.0 to 5.5V*)

CC

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Battery Timekeeping Current I
Battery Timekeeping Current (IND) I

Trickle Charge Resistors

Trickle Charger Diode Voltage

BATT
BATT

R1
R2
R3

V

TD

V

=3V 550 nA 12

BAT

V

=3V 800 nA 12

BAT

2
4
8

kΩ
kΩ
kΩ

0.7 V

Drop

CAPACITANCE (t

= 25°C)

A

PARAMETER SYMBOL CONDITION TYP MAX UNITS NOTES

Input Capacitance C
Output Capacitance C
Crystal Capacitance C

I
O
X

10 pF
15 pF

6pF

3-WIRE AC ELECTRICAL CHARACTERISTICS

(0°C to 70°C or –40°C to +85°C; V

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Data to CLK Setup t

CLK to Data Hold t

CLK to Data Delay t

CLK Low Time t

CLK High Time t

CLK Frequency t

DC

CDH

CDD

CL

CH

CLK

CLK Rise and Fall tR, t

CE to CLK Setup t

CLK to CE Hold t

CE Inactive Time t

CE to Output High Z t

SCLK to Output High Z t

CC

CCH

CWH

CDZ

CCZ

*Unless otherwise noted.

VCC=2.0V 200

VCC=5V 50

VCC=2.0V 280

VCC=5V 70

VCC=2.0V 800

VCC=5V 200

VCC=2.0V 1000

VCC=5V 250

VCC=2.0V 1000

VCC=5V 250

VCC=2.0V 0.6

VCC=5V DC 2.0

VCC=2.0V 2000

F

VCC=5V 500

VCC=2.0V 4

VCC=5V 1

VCC=2.0V 240

VCC=5V 60

VCC=2.0V 4

VCC=5V 1

VCC=2.0V 280

VCC=5V 70

VCC=2.0V 280

VCC=5V 70

= 2.0V to 5.5V*)

CC

ns 5, 6

ns 5, 6

ns 5, 6, 7

ns 6

ns 6

MHz 6

ns
µs

ns 6
µs

ns 5, 6

ns 5, 6

6

6

14 of 20

TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER Figure 12

TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER Figure 13

DS1306

15 of 20

SPI AC ELECTRICAL CHARACTERISTICS

DS1306

(0°C to 70°C or –40°C to +85°C; V

= 2.0 to 5.5V*)

CC

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Data to CLK Setup t

CLK to Data Hold t

CLK to Data Delay t

CLK Low Time t

CLK High Time t

CLK Frequency t

DC

CDH

CDD

CL

CH

CLK

CLK Rise and Fall tR, t

CE to CLK Setup t

CLK to CE Hold t

CE Inactive Time t

CE to Output High Z t

CC

CCH

CWH

CDZ

VCC=2.0V 200

VCC=5V 50

VCC=2.0V 280

VCC=5V 70

VCC=2.0V 800

VCC=5V 200

VCC=2.0V 1000

VCC=5V 250

VCC=2.0V 1000

VCC=5V 250

VCC=2.0V 0.6

VCC=5V DC 2.0

VCC=2.0V 2000

F

VCC=5V 500

VCC=2.0V 4

VCC=5V 1

VCC=2.0V 240

VCC=5V 60

VCC=2.0V 4

VCC=5V 1

VCC=2.0V 280

VCC=5V 70

ns 5, 6

ns 5, 6

ns 5, 6, 7

ns 6

ns 6

MHz 6

ns

µs

ns 6

µs

ns 5, 6

6

6

*Unless otherwise noted.

16 of 20

TIMING DIAGRAM: SPI READ DATA TRANSFER Figure 14

TIMING DIAGRAM: SPI WRITE DATA TRANSFER Figure 15

DS1306

SCLK can be either polarity, timing shown for CPOL = 1.

17 of 20

DS1306

NOTES:

1. All voltages are referenced to ground.

2. Logic 0 voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.0V,

VOL=GND for capacitive loads.

3. I

4. I

5. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.

6. Measured with 50 pF load.

7. Measured at VOH=2.4V or VOL=0.4V.

8. VCC=V

9. V

10. V

11. V

12. Logic 1 voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at 2.0V,

13. V

and I

CC1T

and I

CC1A

(0-V

CC

=0V.

CC2

=0V.

CC1
CC1<VBAT

) at VCC=2.0V.

CC1

are specified with CE set to a logic 0.

CC2T

are specified with CE= VCC, SCLK=2 MHz (0-VCC) at VCC=5V; SCLK=500 kHz

CC2A

, when V

CC1>VCC2

+0.2V (typical); VCC=V

.

VOH=VCC for capacitive loads.

must be less than or equal to the largest of V

CCIF

CC2

CC1

, when V

, V

CC2

CC2>VCC1

, and V

BAT

.

.

18 of 20

DS1306 16-PIN DIP (300-mil)

PKG 16-PIN

DIM MIN MAX

A IN.

MM

B IN.

MM

C IN.

MM

D IN.

MM

E IN.

MM

F IN.

MM

G IN.

MM

H IN.

MM

J IN.

MM

K IN.

MM

0.740

18.80

0.240

6.10

0.120

3.05

0.300

7.62

0.015

0.38

0.120

3.04

0.090

2.29

0.320

8.13

0.008

0.20

0.015

0.38

0.780

19.81

0.260

6.60

0.140

3.56

0.325

8.26

0.040

1.02

0.140

3.56

0.110

2.79

0.370

9.40

0.012

0.30

0.021

0.53

DS1306

19 of 20

DS1306 20-PIN TSSOP

DS1306

DIM MIN MAX

A MM
A1 M M
A2 M M

C MM

L MM

e1 MM

B MM

D MM

E MM

G MM

H MM

phi

-1.10

0.05 -

0.75 1.05

0.09 0.18

0.50 0.70

0.65 BSC

0.18 0.30

6.40 6.90

4.40 NOM

0.25 REF

6.25 6.55
0° 8°

20 of 20