Datasheet DS1244W-120, DS1244YP-70, DS1244Y-70, DS1244WP-120IND, DS1244WP-120 Datasheet (Dallas Semiconductor)

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www.maxim-ic.com

www.maxim-ic.com

DS1244/DS1244P

256k NV SRAM

with Phantom Clock

FEATURES

§ Real-time clock (RTC) keeps track of

hundredths of seconds, minutes, hours, days,
date of the month, months, and years

§ 32k x 8 NV SRAM directly replaces volatile

static RAM or EEPROM

§ Embedded lithium energy cell maintains

calendar operation and retains RAM data

§ Watch function is transparent to RAM

operation

§ Month and year determine the number of

days in each month; valid up to 2100

§ Full 10% operating range

§ Operating temperature range: 0°C to +70°C

§ Over 10 years of data retention in the

absence of power

§ Lithium energy source is electrically

disconnected to retain freshness until power
is applied for the first time

§ DIP module only

§ Standard 28-pin JEDEC pinout

§ PowerCap® module board only

– Surface mountable package for direct

connection to PowerCap containing
battery and crystal

– Replaceable battery (PowerCap)
– Pin-for-pin compatible with DS1248P

and DS1251P

§ Underwriters Laboratory (UL) recognized

PIN ASSIGNMENT (Top View)

V

CC

WE

11

OE

10

CE
DQ7

DQ6
DQ5

DQ4

DQ3

34

32
31
30
29
28
27
26
25
24
23
22
21

X2

20
19
18

V

BAT

12

4
3

0

DQ0
DQ1

DQ2

GND

1

2
3
4

5
6

7
8

9
10

11
12

13

14

14/RST

DS2144

28-PDIP Module (740mil)

RST
N.C.
N.C.
N.C.

V

WE

OE
CE

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

1

2

3
4
5

CC

6
7
8
9
10
11
12
13
14
15

X1 GND
16
17

34-Pin PowerCap Module

(Uses DS9034PCX PowerCap)

28
27

26
25

24
23

22
21

20
19

18
17

16

15

DS1244P

N.C.
N.C.33

14

12
11

10
9

6
5
4
3

1
0

Package Dimension Information

http://www.maxim-ic.com/TechSupport/DallasPackInfo.htm

PowerCap is a registered trademark of Dallas Semiconductor.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata.

1 of 19 081902

DS1244/DS1244P

PIN DESCRIPTION

TYPICAL OPERATING CIRCUIT

A0–A14 - Address Inputs

CE - Chip Enable

OE - Output Enable

WE - Write Enable

V

CC

- Power-Supply Input
GND - Ground
DQ0–DQ7 - Data In/Data Out
N.C. - No Connection
X1, X2 - Crystal Connection
V

BAT

RST - Reset

- Battery Connection

ORDERING INFORMATION

PART PIN-PACKAGE TEMP RANGE TOP MARK

DS1244Y-70 28-Module (740mil) 0°C to +70°C DS1244Y-70
DS1244YP-70 34-PowerCap
DS1244W-120 28-Module (740mil) 0°C to +70°C DS1244W-120
DS1244W-120IND 28-Module (740mil) -40°C to +85°C DS1244W-120IND
DS1244WP-120 34-PowerCap
DS1244WP-120IND 34-PowerCap

*

DS9034PCX (PowerCap) Required. (Must be ordered separately.)

*

*

*

0°C to +70°C DS1244YP-70

0°C to +70°C DS1244WP-120

-40°C to +85°C DS1244WP-120IND

DESCRIPTION

The DS1244 256k NV SRAM with a Phantom clock is a fully static nonvolatile RAM (NV SRAM)
(organized as 32k words by 8 bits) with a built-in real-time clock. The DS1244 has a self-contained
lithium energy source and control circuitry, which constantly monitors VCC for an out-of-tolerance
condition. When such a condition occurs, the lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent garbled data in both the memory and real-time
clock.

The phantom clock provides timekeeping information for hundredths of seconds, seconds, minutes, hours,
days, date, months, and years. The date at the end of the month is automatically adjusted for months with
fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or
12-hour format with an AM/PM indicator.

PACKAGES

The DS1244 is available in two packages: 28-pin DIP and 34-pin PowerCap module. The 28-pin DIP­style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1244P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the Powercap is
DS9034PCX.

2 of 19

DS1244/DS1244P

RAM READ MODE

The DS1244 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable)

is active (low). The unique address specified by the 15 address inputs (A0–A14) defines which of the
32,768 bytes of data is to be accessed. Valid data is available to the eight data-output drivers within t

(access time) after the last address input signal is stable, providing that CE and OE (output enable)

access times and states are also satisfied. If

OE and CE access times are not satisfied, then data access

ACC

must be measured from the later occurring signal (

CE or OE ) and the limiting parameter is either tCO for

CE or tOE for OE , rather than address access.

RAM WRITE MODE

The DS1244 is in the write mode whenever the WE and CE signals are in the active (low) state after

address inputs are stable. The latter occurring falling edge of

write cycle. The write cycle is terminated by the earlier rising edge of

must be kept valid throughout the write cycle.

time (t

) before another cycle can be initiated. The OE control signal should be kept inactive (high)

WR

WE must return to the high state for a minimum recovery

during write cycles to avoid bus contention. However, if the output bus has been enabled (

active) then

WE will disable the outputs in tODW from its falling edge.

CE or WE will determine the start of the

CE or WE . All address inputs

CE and OE

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point, V

(battery supply level), device power is switched from the V

SO

operation and SRAM data are maintained from the battery until V

is below the power fail point, V

CC

(point at which write protection occurs), the

PF

falls below the battery switch

CC

pin to the backup battery. RTC

CC

is returned to nominal levels.

CC

is greater than V

CC

PF

.

The 3.3V device is fully accessible and data can be written or read only when V
When V
power is switched from V
than V
V

BAT

fall as below the V

CC

CC

, the device power is switched from VCC to the backup supply (V

BAT

. RTC operation and SRAM data are maintained from the battery until V

, access to the device is inhibited. If V

PF

to the backup supply (V

) when VCC drops below VPF. If V

BAT

is less than VBAT, the device

PF

BAT

is greater than V

CC

is greater

PF

) when VCC drops below

is returned to nominal

CC

PF

levels.

All control, data, and address signals must be powered down when V

is powered down.

CC

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of the chip enable, output enable, and write enable. Initially, a read cycle to any memory location using

3 of 19

.

DS1244/DS1244P

the CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer
to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the

phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either

receive or transmit data on DQ0, depending on the level of the

OE pin or the WE pin. Cycles to other

locations outside the memory block can be interleaved with

CE cycles without interrupting the pattern

recognition sequence or data transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.

Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.

4 of 19

Figure 1. PHANTOM CLOCK REGISTER DEFINITION

DS1244/DS1244P

Note: The pattern recognition in hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being

19

accidentally duplicated and causing inadvertent entry to the phantom clock is less than 1 in 10

. This

pattern is sent to the phantom clock LSB to MSB.

5 of 19

Figure 2. PHANTOM CLOCK REGISTER DEFINITION

DS1244/DS1244P

AM/PM/12/24 MODE

Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the second 10-hour bit (20–23 hours).

OSCILLATOR AND RESET BITS

Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the

RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET

bit is set to logic 0, a low input on the RESET pin will cause the phantom clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1.

ZERO BITS

Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.

6 of 19

DS1244/DS1244P

BATTERY LONGEVITY

The DS1244 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the V

supply is not present. The capability of this internal power supply

CC

is sufficient to power the DS1244 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25
in the absence of V

power. Each DS1244 is shipped from Dallas Semiconductor with its lithium energy

CC

source disconnected, guaranteeing full energy capacity. When V

PF , the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the

V
DS1244 will be much longer than 10 years since no lithium battery energy is consumed when V

°C with the internal clock oscillator running

is first applied at a level greater than

CC

is

CC

present.

See “Conditions of Acceptability” at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm.

CLOCK ACCURACY (DIP MODULE)

The DS1244 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is
calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements
and does not require additional calibration. For this reason, methods of field clock calibration are not
available and not necessary.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1244P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within

±1.53 minutes per month (35ppm) at +25°C.

7 of 19

DS1244/DS1244P

ABSOLUTE MAXIMUM RATINGS*

Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V
Storage Temperature Range -40ºC to +85ºC
Soldering Temperature Range See IPC/JEDEC J-STD-020A (DIP)

(Note 13)

OPERATING RANGE

RANGE TEMP RANGE V

Commercial 0°C to +70°C
Industrial -40°C to +85°C

*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.

3.3V

±10% or 5V ±10%

3.3V

±10% or 5V ±10%

CC

RECOMMENDED DC OPERATING CONDITIONS Over the operating range

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VCC = 5V ±10% 2.2 VCC + 0.3V

Input Logic 1

V

= 3.3V ±10%

CC

V

IH

V11

2.0 VCC + 3V

VCC = 5V ±15% -0.3 0.8

Input Logic 0

= 3.3V ±10%

V

CC

V

IL

-0.3 0.6

V11

DC ELECTRICAL CHARACTERISTICS Over the operating range (5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current I
I/O Leakage Current

CE ³ VIH ≤ V

CC

Output Current at 2.4V I

Output Current at 0.4V I

Standby Current CE = 2.2V

I

Standby Current

I

CE = VCC - 0.5V

Operating Current t

= 70ns I

CYC

Write Protection Voltage V

Battery Switchover Voltage V

IL

I

IO

OH

OL

CCS1

CCS2

CC01

PF

SO

-1.0 +1.0

-1.0 +1.0

mA

mA

12

-1.0 mA

2.0 mA

510mA

3.0 5.0 mA

85 mA

4.25 4.37 4.50 V 11

V

BAT

V11

8 of 19

DS1244/DS1244P

DC ELECTRICAL CHARACTERISTICS Over the operating range (3.3V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current
I/O Leakage Current

CE ³ VIH ≤ V

CC

Output Current at 2.4V I
Output Current at 0.4V I

Standby Current CE = 2.2V
Standby Current

CE = VCC - 0.5V

Operating Current t

= 70ns I

CYC

Write Protection Voltage V
Battery Switchover Voltage

I

I

I

CCS1

I

CCS2

CC01

V

IL

IO

OH

OL

SO

PF

-1.0 +1.0

-1.0 +1.0

mA

mA

12

-1.0 mA

2.0 mA
57mA

2.0 3.0 mA

50 mA

2.80 2.86 2.97 V 11

V

BAT

or V

PF

V11

CAPACITANCE (T

= +25°C)

A

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C
Input/Output Capacitance C

IN

I/O

510pF
510pF

MEMORY AC ELECTRICAL CHARACTERISTICS Over the operating range (5V)

PARAMETER SYMBOL

Read Cycle Time t
Access Time t

OE to Output Valid

CE to Output Valid

OE or CE to Output Active

Output High-Z from Deselection t
Output Hold from Address Change t
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t

Output High-Z from WE

Output Active from WE
Data Setup Time t

Data Hold Time from WE

ACC

t

t

t

COE

WC

WP

AW

WR

t

ODW

t

OEW

t

RC

OE

CO

OD

OH

DS

DH

DS1244Y-70

MIN MAX

UNITS NOTES

70 ns

70 ns
35 ns

70 ns

5ns5

25 ns 5

5ns
70 ns
50 ns 3

0ns

0ns

25 ns 5

5ns5

30 ns 4

5ns4

9 of 19

PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS

Over the operating range (5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Read Cycle Time t

CE Access Time

OE Access Time

CE to Output Low-Z

OE to Output Low-Z

CE to Output High-Z

OE to Output High-Z

Read Recovery t
Write Cycle Time t
Write Pulse Width t
Write Recovery t
Data Setup Time t
Data Hold Time t

CE Pulse Width

RESET Pulse Width

RC

t

CO

t

OE

t

COE

t

OEE

t

OD

t

ODO

RR

WC

WP

WR

DS

DH

t

CW

t

RST

65 ns

55 ns

55 ns

5ns

5ns

25 ns 5

25 ns 5

10 ns
65 ns
55 ns 3
10 ns 10
30 ns 4

0ns4

60 ns

65 ns

DS1244/DS1244P

POWER-DOWN/POWER-UP TIMING Over the operating range (5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

t

t

t

REC

PD

t

t

F

FB

R

CE at V

before Power-Down

IH

VCC Slew from V

V

PF(min)

( CE at VPF)
VCC Slew from V
VCC Slew from V

V

CE at V

PF(min)

( CE at VPF)

after Power-Up

IH

PF(max)

PF(min)

PF(max)

to

to V

to

SO

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Expected Data Retention Time

t

DR

Warning: Under no circumstances are negative undershoots of any amplitude allowed when device is in

battery-backup mode.

0

300

10

0

ms

ms

ms
ms

1.5 2.5 ms

(TA = +25°C)

10 years 9

10 of 19

MEMORY AC ELECTRICAL CHARACTERISTICS

DS1244/DS1244P

Over the operating range (3.3V)

PARAMETER SYMBOL

Read Cycle Time t
Access Time t

OE to Output Valid

CE to Output Valid

OE or CE to Output Active

Output High-Z from Deselection t
Output Hold from Address Change t
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t

Output High-Z from WE

Output Active from WE
Data Setup Time t

Data Hold Time from WE

RC

ACC

t

OE

t

CO

t

COE

OD

OH

WC

WP

AW

WR

t

ODW

t

OEW

t

DH

DS

DS1244W-120

MIN MAX

120 ns

120 ns

60 ns

120 ns

5ns5

40 ns 5

5ns

120 ns

90 ns 3

0ns

20 ns 10

40 ns 5

5ns5

50 ns 4
20 ns 4

PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS

Over the operating range (3.3V)

UNITS NOTES

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Read Cycle Time t

CE Access Time

OE Access Time

CE to Output Low-Z

OE to Output Low-Z

CE to Output High-Z

OE to Output High-Z

Read Recovery t
Write Cycle Time t
Write Pulse Width t
Write Recovery t
Data Setup Time t
Data Hold Time t

CE Pulse Width

RESET Pulse Width

RC

t

CO

t

OE

t

COE

t

OEE

t

OD

t

ODO

RR

WC

WP

WR

DS

DH

t

CW

t

RST

120 ns

100 ns

100 ns

5ns

5ns

40 ns 5

40 ns 5

20 ns
120 ns
100 ns 3

20 ns 10

45 ns 4

0ns4

105 ns

120 ns

11 of 19

DS1244/DS1244P

POWER-DOWN/POWER-UP TIMING Over the operating range (3.3V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

t

t

REC

PD

t

t

F

R

CE at V

before Power-Down

IH

VCC Slew from V

V

PF(MIN)

( CE at VIH)

VCC Slew from V

V

CE at V

PF(MIN)

( CE at VIH)

after Power-Up

IH

PF(MAX)

PF(MAX)

to

to

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Expected Data Retention Time t

DR

Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is

in battery-backup mode.

0

300

0

ms

ms

ms

1.5 2.5 ms

(T

= +25°C)

A

10 years 9

12 of 19

MEMORY READ CYCLE (Note 1)

MEMORY WRITE CYCLE 1 (Notes 2, 6, and 7)

DS1244/DS1244P

13 of 19

MEMORY WRITE CYCLE 2 (Notes 2 and 8)

DS1244/DS1244P

RESET FOR PHANTOM CLOCK

READ CYCLE TO PHANTOM CLOCK

14 of 19

WRITE CYCLE TO PHANTOM CLOCK

DS1244/DS1244P

15 of 19

POWER-DOWN/POWER-UP CONDITION, 5V

DS1244/DS1244P

POWER-DOWN/POWER-UP CONDITION, 3.3V

16 of 19

AC TEST CONDITIONS

Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V

Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns

NOTES:

1) WE is high for a read cycle.

DS1244/DS1244P

OE = V

2)

or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance

IH

state.

t

3)

4)

5)

6)

is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE

WP

going low to the earlier of

t

, tDS are measured from the earlier of CE or WE going high.

DH

CE or WE going high.

These parameters are sampled with a 50pF load and are not 100% tested.
If the CE low transition occurs simultaneously with or later than the WE low transition in Write

Cycle 1, the output buffers remain in a high-impedance state during this period.

If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

7)
buffers remain in a high-impedance state during this period.

If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,

8)
the output buffers remain in a high impedance state during this period.

The expected t

9)

is defined as cumulative time in the absence of VCC with the clock oscillator

DR

running.

t

10)

11)

12)

13)

is a function of the latter occurring edge of WE or CE .

WR

Voltages are referencd to ground.
RST (Pin 1) has an internal pullup resistor.

RTC modules can be successfully processed through conventional wave-soldering techniques as long

as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post­solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not
used.

In addition, for the PowerCap:

Dallas Semiconductor recommends that PowerCap module bases experience one pass through solder

1)
reflow oriented with the label side up (“live-bug”).

Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three

2)
seconds.

To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part,

–

apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove
solder.

17 of 19

DS1244P WITH DS9034PCX ATTACHED

DS1244/DS1244P

PKG INCHES

DIM MIN NOM MAX

A

0.920 0.925 0.930

B

0.955 0.960 0.965

C

0.240 0.245 0.250

D

0.052 0.055 0.058

E

0.048 0.050 0.052

F

0.015 0.020 0.025

G

0.020 0.025 0.030

COMPONENTS AND PLACEMENT MIGHT

VARY FROM EACH DEVICE TYPE

18 of 19

RECOMMENDED POWERCAP MODULE LAND PATTERN

PKG INCHES

DIM MIN NOM MAX

A
B
C
D
E

DS1244/DS1244P

—1.050 —
—0.826 —
—0.050 —
—0.030 —
—0.112 —

Note: Dallas Semiconductor recommends that PowerCap module bases experience one pass through

solder reflow oriented with the label side up (“live-bug”).

Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than three
seconds.

To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part, apply flux,
heat the lead frame pad until the solder reflows, and use a solder wick to remove solder.

19 of 19