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DS1225Y-200-IND

Datasheet DS1225Y-200-IND, DS1225Y-200, DS1225Y-170, DS1225Y-150-IND, DS1225Y-150 Datasheet (Dallas Semiconductor)

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Page 1
DS1225Y
64K Nonvolatile SRAM
DS1225Y
021998 1/8
FEATURES
• 10 years minimum data retention in the absence of
external power
• Data is automatically protected during power loss
PROM
• Unlimited write cycles
• Low-power CMOS
• JEDEC standard 28–pin DIP package
• Read and write access times as fast as 150 ns
• Full ±10% operating range
+85°C, designated IND
PIN ASSIGNMENT
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15
16
17
18
19
20
21
22
23
24
25
26
27
28NC
A12
A7 A6 A5 A4 A3 A2
A1
A0 DQ0 DQ1 DQ2
GND
VCC
NC A8 A9 A11
A10
DQ7 DQ6 DQ5 DQ4 DQ3
WE
OE
CE
28–PIN ENCAPSULATED PACKAGE
720 MIL EXTENDED
PIN DESCRIPTION
A0–A12 – Address Inputs DQ0–DQ7 – Data In/Data Out CE
– Chip Enable WE – Write Enable OE – Output Enable V
CC
– Power (+5V) GND – Ground NC – No Connect
DESCRIPTION
The DS1225Y 64K Nonvolatile SRAM is a 65,536–bit, fully static, nonvolatile RAM organized as 8192 words by 8 bits. Each NV SRAM has a self–contained lithium energy source and control circuitry which constantly monitors V
CC
for an out–of–tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is uncon­ditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 8K x 8 SRAMs
Page 2
DS1225Y
021998 2/8
READ MODE
The DS1225Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A
0–A12
) de­fines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output driv­ers within t
ACC
(Access Time) after the last address in­put signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either t
CO
for CE or tOE for OE rather than address ac-
cess.
WRITE MODE
The DS1225Y executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initi-
ated. The OE
control signal should be kept inactive (high) during write cycles to avoid bus contention. How­ever, if the output drivers are enabled (CE and OE ac­tive) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1225Y provides full functional capability for V
CC
CC
without any additional support circuitry. The DS1225Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs be­come “don’t care,” and all outputs become high imped­ance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power–up, when V
CC
rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and dis­connects the lithium energy source. Normal RAM oper­ation can resume after V
CC
exceeds 4.5 volts.
Page 3
DS1225Y
021998 3/8
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V Operating Temperature 0°C to 70°C; –40°C to +85°C for IND parts Storage Temperature –40°C to +70°C; –40°C to +85°C for IND parts Soldering T emperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYM MIN TYP MAX UNITS NOTES
Power Supply Voltage V
CC
4.5 5.0 5.5 V
Input Logic 1 V
IH
2.2 V
CC
V
Input Logic 0 V
IL
0.0 +0.8 V
DC ELECTRICAL CHARACTERISTICS (tA: See Note 10; VCC = 5V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current I
IL
–1.0 +1.0 µA
I/O Leakage Current CE
> VIH < V
CC
I
IO
–1.0 +1.0 µA
Output Current @ 2.4V I
OH
–1.0 mA
Output Current @ 0.4V I
OL
2.0 mA
Standby Current CE = 2.2V I
CCS1
5 10 mA
Standby Current CE = VCC–0.5V I
CCS2
3 5 mA
Operating Current t
CYC
=200 ns
(Commercial)
I
CCO1
75 mA
Operating Current t
CYC
=200 ns
(Industrial)
I
CCO1
85 mA
Write Protection Voltage V
TP
4.25 V 10
Page 4
DS1225Y
021998 4/8
AC ELECTRICAL CHARACTERISTICS (tA: See Note 10; VCC=5.0V ± 10%)
DS1225Y-150 DS1225Y-170 DS1225Y-200
PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Read Cycle Time t
RC
150 170 200 ns
Access Time t
ACC
150 170 200 ns
OE to Output Valid t
OE
70 80 100 ns
CE to Output Valid t
CO
150 170 200 ns
OE or CE to Output Active
t
COE
5 5 5 ns 5
Output High Z from De­selection
t
OD
35 35 35 ns 5
Output Hold from Ad­dress Change
t
OH
5 5 5 ns
Write Cycle Time t
WC
150 170 200 ns
Write Pulse Width t
WP
100 120 150 ns 3
Address Setup Time t
AW
0 0 0 ns
Write Recovery Time t
WR1
t
WR2
0
10
0
10
0
10
ns ns
12 13
Output High Z from WE t
ODW
35 35 35 ns 5
Output Active from WE t
OEW
5 5 5 ns 5
Data Setup Time t
DS
60 70 80 ns 4
Data Hold Time t
DH1
t
DH2
0
10
0
10
0
10
ns ns
12 13
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
10 pF
Input/Output Capacitance C
I/O
10 pF
Page 5
DS1225Y
021998 5/8
ADDRESSES
CE
OE
D
OUT
t
RC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
t
OH
V
IH
t
OD
t
OD
OUTPUT
DATA VALID
t
ACC
t
CO
t
OE
t
COE
t
COE
V
IH
V
IL
V
IH
V
IL
V
OL
V
OH
V
OL
V
OH
READ CYCLE
SEE NOTE 1
ADDRESSES
CE
WE
D
OUT
D
IN
t
WC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VILV
IL
VILV
IL
V
IH
V
IH
t
ODW
t
OEW
t
WP
t
WR1
t
DH1
t
DS
V
IH
V
IL
V
IH
V
IL
DATA IN STABLE
HIGH
IMPEDANCE
WRITE CYCLE 1
t
AW
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12
ADDRESSES
WRITE CYCLE 2
CE
WE
D
OUT
D
IN
t
WC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AW
t
WP
VILV
IL
VILV
IL
V
IH
V
IH
V
IL
V
IH
t
WR2
t
COE
t
ODW
DATA IN STABLE
V
IH
V
IL
V
IH
V
IL
t
DStDH2
SEE NOTE 2, 3, 4, 6, 7, 8 AND 13
Page 6
DS1225Y
021998 6/8
POWER–DOWN/POWER–UP CONDITION
3.2V
DATA RETENTION TIME
CE
V
CC
t
F
t
PD
t
R
t
REC
t
DR
LEAKAGE CURRENT I
L
SUPPLIED FROM
LITHIUM CELL
V
TP
SEE NOTE 11
POWER–DOWN/POWER–UP TIMING
PARAMETER SYM MIN MAX UNITS NOTES
CE at VIH before Power–Down t
PD
0 µs 11
VCC Slew from VTP to 0V t
F
100 µs
VCC Slew from 0V to V
TP
t
R
0 µs
CE at VIH after Power–Up t
REC
2 ms
(tA = 25°C)
PARAMETER SYM MIN MAX UNITS NOTES
Expected Data Retention Time t
DR
10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE
= VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE
or WE going high.
4. t
DS
is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE
low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE
high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
Page 7
DS1225Y
021998 7/8
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period.
9. Each DS1225Y is marked with a 4–digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The expected t
DR
is defined as starting at the date of manufacture.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial prod­ucts, this range is
0°Cto 70°C. For industrial products (IND), this range is –40°C to +85°C.
11.In a power down condition the voltage on any pin may not exceed the voltage on VCC.
12.t
WR1
, t
DH1
are measured from WE going high.
13.t
WR2
, t
DH2
are measured from CE going high.
14.DS1225Y modules are recognized by Underwriters Laboratory (U.L.) under file E99151 (R).
DC TEST CONDITIONS
Outputs open. All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0–3.0V Timing Measurement Reference Levels
Input:1.5V Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1225 TTP–
SSS –
III
Operating Temperature Range Blank: 0°Cto 70°C IND: –40°C to +85°C
Access 150: 170: 200:
Speed 150 ns 170 ns 200 ns
Package Type Blank: 28–pin 600 mil DIP
V
CC
T olerance
Y: 10%
Page 8
DS1225Y
021998 8/8
DS1225Y NONVOLATILE SRAM, 28–PIN 720 MIL EXTENDED MODULE
A
1
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
1.520
38.61
1.540
39.12
0.695
17.65
0.720
18.29
0.395
10.03
0.415
10.54
0.100
2.54
0.130
3.30
0.017
0.43
0.030
0.76
0.120
3.05
0.160
4.06
0.090
2.29
0.110
2.79
0.590
14.99
0.630
16.00
0.008
0.20
0.012
0.30
0.015
0.38
0.021
0.53
C
F
GKD
H B
E
J
28–PINPKG
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