Datasheet DS1225AD-85, DS1225AD-200-IND, DS1225AD-200, DS1225AD-170, DS1225AD-150-IND Datasheet (Dallas Semiconductor)

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A8A

A

A

DS1225AB/AD

64k Nonvolatile SRAM

FEATURES

 10 years minimum data retention in the

absence of external power

 Data is automatically protected during power

loss

 Directly replaces 8k x 8 volatile static RAM

or EEPROM

 Unlimited write cycles
 Low-power CMOS
 JEDEC standard 28-pin DIP package
 Read and write access times as fast as 70 ns
 Lithium energy source is electrically

disconnected to retain freshness until power
is applied for the first time

 Full ±10% VCC operating range (DS1225AD)
 Optional ±5% V

(DS1225AB)

 Optional industrial temperature range of

-40°C to +85°C, designated IND

operating range

CC

PIN ASSIGNMENT

1

NC

A12

DQ0
DQ1

DQ2

GND

A7
A6
A5
A4
A3

A2
A1
A0

2
3
4

5
6

7
8

9
10

11
12

13
14

28-Pin ENCAPSULATED PACKAGE

720-mil EXTENDED

28
27

26
25

24
23

22
21

20
19

18
17

16
15

VCC
WE
NC

9
11

OE

10
CE
DQ7
DQ6

DQ5
DQ4
DQ3

PIN DESCRIPTION

A0-A12 - Address Inputs
DQ0-DQ7 - Data In/Data Out

CE - Chip Enable
WE - Write Enable
OE - Output Enable

V

- Power (+5V)

CC

GND - Ground
NC - No Connect

DESCRIPTION

The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors V
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to
the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and
the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.

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for an out-of-tolerance condition. When such a condition occurs, the lithium

CC

DS1225AB/AD

READ MODE

The DS1225AB and DS1225AD execute a read cycle whenever WE (Write Enable) is inactive (high) and

CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13
address inputs (A
available to the eight data output drivers within t

stable, providing that
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is

-A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be

0

(Access Time) after the last address input signal is

ACC

CE and OE access times are al so satisfied. If CE and OE access times are not

either t

for CE or tOE for OE rather than address access.

CO

WRITE MODE

The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active
(low) after address inputs are stable. The later-occurring falling edge of
start of the write cycle. The write cycle is terminated by the earlier rising edge of
inputs must be kept valid throughout the write cycle.
recovery time (t

) before another cycle can be initiated. The OE control signal should be kept inactive

WR

WE must return to the high state for a minimum

(high) during write cycles to avoid bus contention. However, if the output drivers are enabled (

OE active) then WE will disable the outputs in t

from its falling edge.

ODW

CE or WE will determine the

CE or WE . All address

CE and

DATA RETENTION MODE

The DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by

4.5 volts. The DS1225AD provides full-functional capability for V
protects by 4.25 volts. Data is maintained in the absence of V
The nonvolatile static RAMs constantly monitor V

. Should the supply voltage decay, the NV SRAMs

CC

without any additional support circuitry.

CC

automatically write protect themselves, all inputs become “don’t care,” and all outputs become high­impedance. As V

falls below approximately 3.0 volts, the power switching circuit connects the lithium

CC

energy source to RAM to retain data. During power-up, when V
the power switching circuit connects external V
Normal RAM operation can resume after V

CC

to RAM and disconnects the lithium energy source.

CC

exceeds 4.75 volts for the DS1225AB and 4.5 volts for the

DS1225AD.

greater than 4.5 volts and write

CC

rises above approximately 3.0 volts,

CC

FRESHNESS SEAL

Each DS1225 is shipped from Dallas Semiconductor with the lithium energy source disconnected,
guaranteeing full energy capacit y. When V
energy source is enabled for battery backup operation.

is first applied at a level of greater than VTP , the lithium

CC

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DS1225AB/AD

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C; -40°C to +85°C for IND parts
Storage Temperature -40°C to +70°C; -40°C to +85°C for IND parts
Soldering Temperature 260°C for 10 seconds

∗ This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended per iods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

DS1225AB Power Supply Voltage V
DS1225AD Power Supply Voltage V
Logic 1 V
Logic 0 V

CC
CC

IH
IL

4.75 5.0 5.25 V

4.50 5.0 5.5 V

2.2 V

CC

V

0.0 +0.8 V

(VCC =5V ± 5% for DS1225AB)

: See Note 10)

(T

A

DC ELECTRICAL CHARACTERISTICS (V

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Leakage Current
I/O Leakage Current

CE> VIH< V

CC

Output Current @ 2.4V I
Output Current @ 0.4V I

Standby Current CE =2.2V
Standby Current CE =VCC -0.5V

Operating Current t

CYC

=200 ns
(Commercial)
Operating Current t

CYC

=200 ns
(Industrial)
Write Protection Voltage
(DS1225AB)
Write Protection Voltage
(DS1225AD)

I
I

I

CCS1

I

CCS2

I

CC01

I

CC01

V

V

IL

IO

OH
OL

TP

TP

-1.0 +1.0

-1.0 +1.0

-1.0 mA

2.0 mA

4.50 4.62 4.75 V

4.25 4.37 4.5 V

=5V ± 10% for DS1225AD)

CC

µA
µA

5.0 10.0 mA

3.0 5.0 mA
75 mA

85 mA

CAPACITANCE (TA =25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Input Capacitance C
Input/Output Capacitance C

IN

I/O

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510pF
510pF

(VCC =5V ± 5% for DS1225AB)

AC ELECTRICAL CHARACTERISTICS (V

DS1225AB-70

PARAMETER SYMBOL

Read Cycle Time t
Access Time t

OE to Output Valid
CE to Output Valid

OE or CE to Output Active

Output High Z from Deselection t
Output Hold from Address
Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t

Output High Z from WE
Output Active from WE

Data Setup Time t
Data Hold Time t

ACC

t

t

t

COE

t

WC
WP
AW

WR1

t

WR2

t

ODW

t

OEW

DH1

t

DH2

RC

OE
CO

OD

OH

DS

DS1225AD-70

MIN MAX MIN MAX

70 85 ns

70 85 ns
35 45

70 85

5

25 30 ns 5

5

70 85 ns
55 65 ns 3

00 ns
0

10

25 30

5

30 35 ns 4

0

10

DS1225AB/AD

(T

: See Note 10)

A

=5V ± 10% for DS1225AD)

CC

DS1220AB-85
DS1220AD-85

UNITS NOTES

ns
ns

5ns5

5ns

0

10

ns
ns

12
13

ns 5

5ns5

0

10

ns
ns

12
13

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AC ELECTRICAL CHARACTERISTICS (cont’d)

DS1225AB- 150

PARAMETER SYMBOL

Read Cycle Time t
Access Time t

OE to Output Valid
CE to Output Valid

OE or CE to Output Active

Output High Z from Deselection t
Output Hold from Address
Change
Write Cycle Time t
Write Pulse Width t
Address Setup Time t
Write Recovery Time t

Output High Z from WE
Output Active from WE

Data Setup Time t
Data Hold Time t

ACC

t
t

t

COE

OD

t

OH

WC
WP
AW

WR1

t

WR2

t

ODW

t

OEW

DH1

t

DH2

RC

OE
CO

DS

DS1225AD- 150

MIN MAX MIN MAX

150 200 ns

150 200 ns

70 100

150 200

5

35 35 ns 5

5

150 200 ns
100 100 ns 3

00 ns
0

10

35 35

5

60 80 ns 4

0

10

DS1225AB/AD

DS1220AB-200
DS1220AD-200

UNITS NOTES

ns
ns

5ns5

5ns

0

10

ns
ns

12
13

ns 5

5ns5

0

10

ns
ns

12
13

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READ CYCLE

SEE NOTE 1

WRITE CYCLE 1

DS1225AB/AD

SEE NOTES 2, 3, 4, 6, 7, 8 AND 12

WRITE CYCLE 2

SEE NOTES 2, 3, 4, 6, 7, 8 AND 13

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DS1225AB/AD

POWER-DOWN/POWER-UP CONDITION

SEE NOTE 11

POWER-DOWN/POWER-UP TIMING (TA : See Note 10)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE at VIH before Power-Down
VCC slew from VTP to 0
VCC slew from 0V to V

V

TP

CE at VIH after Power-Up

t

t

REC

PD

t

t

0

F
R

300
300

2

125 ms

µs
µs

µs

11

(TA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Expected Data Retention Time t

DR

10 years 9

WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.

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DS1225AB/AD

NOTES:

1. WE is high for a read cycle.

2.

OE = V

state.

t

3.

is specified as the logical AND of CEandWE . tWP is measured from the latter of CE or WE

WP

going low to the earlier of

t

4.

5.

6.

are measured from the earlier of CE or WE going high.

DS

These parameters are sampled with a 5 pF load and are not 100% tested.
If the CE low transition occurs simultaneously with or later than the WE low transition, the output

buffers remain in a high-impedance state during this period.

7.

If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in a high-impedance state during this period.

8.

If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,

the output buffers remain in a high-impedance state during this period.

or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance

IH

CE or WE going high.

9.

Each DS1225AB and each DS1225AD has a built-in switch that disconnects the lithium source until

V

is first applied by the user. The expected tDR is defined as accumulative tim e in the absence of

CC

V

starting from the time power is f irst applied by the user.

CC

10.

All AC and DC electrical characteristics are valid over the full operating temperature range. For

commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.

11.

In a power down condition the voltage on any pin may not exceed the voltage on V
t

, t

12.

WR1

t

13.

WR2

14.

DS1225AB and DS1225AD modules are recognized by Underwriters Laboratory (U.L.) under file

are measured from WE going high.

DH1

, t

are measured from CE going high.

DH2

CC

.

E99151.

DC TEST CONDITIONS

Outputs Open
All Voltages Are Referenced to Ground

AC TEST CONDITIONS

Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels

Input: 1.5V
Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

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ORDERING INFORMATION

DS1225AB/AD

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DS1225AB/AD

DS1225AB/AD NONVOLATILE SRAM, 28-PIN, 720-MIL EXTENDED MODULE

PKG 28-PIN
DIM MIN MAX

A IN.

MM

B IN.

MM

C IN.

MM

D IN.

MM

E IN.

MM

F IN.

MM

G IN.

MM

H IN

MM
J IN.
MM

K IN.

MM

1.520

38.61

0.695

17.65

0.395

10.03

0.100

2.54

0.017

0.43

0.120

3.05

0.090

2.29

0.590

14.99

0.008

0.20

0.015

0.38

1.540

39.12

0.720

18.29

0.415

10.54

0.130

3.30

0.030

0.76

0.160

4.06

0.110

2.79

0.630

16.00

0.012

0.30

0.021

0.53

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