Datasheet DS1044 Datasheet (dallas semiconductor)

Page 1
查询DS1044供应商
DS1044
DS1044
4–in–1 High–Speed Silicon Delay Line
FEATURES
All–silicon timing circuit
Four independent buffered delays
Initial delay tolerance ±1.5 ns
Leading and trailing edge precision preserves the
input symmetry
Standard 14–pin DIP, 14–pin SOIC (150 mil)
Vapor phase, IR and wave solderable
Available in Tape and Reel
PIN ASSIGNMENT
1
IN1
2
NC
3
IN2
4
IN3
5
IN4
6
NC
7
GND
DS1044 14–PIN DIP
DS1044R 14–PIN SOIC (150 MIL)
See Mech. Drawings
14 13 12 11 10
9 8
Section
PIN DESCRIPTION
IN1–IN4 – Input Signals OUT1–OUT4 – Output Signals NC – No Connection V
CC
GND – Ground
– +5 Volt Supply
V
CC
NC OUT1 NC OUT2 OUT3 OUT4
DESCRIPTION
The DS1044 series is a 4–in–1 version of the low– power, +5 V olt, high speed, DS1035.
The DS1044 series of delay lines have four independent logic buffered delays in a single package. The device is Dallas Semiconductor’s fastest 4–in–1 delay line. It is available in a standard 14–pin DIP and 14–pin SOIC.
The device features precise leading and trailing edge accuracies. It has the inherent reliability of an all–silicon
delay line solution. The DS1044’s nominal tolerance is ±1.5 ns and an additional tolerance over temperature and voltage of ±1.0 ns for the faster delays. Each output is capable of driving up to 10 LS loads.
Standard delay values are indicated in Table 1. Cus­tomers may contact Dallas Semiconductor at (972) 371–4348 for further information.
021798 1/6
Page 2
DS1044
LOGIC DIAGRAM Figure 1
IN OUT
PART NUMBER DELAY TABLE (t
PART NUMBER
DELAY PER OUTPUT
PLH
(ns)
, t
PHL
TIME DELAY
ONE OF FOUR
) Table 1
INITIAL TOLERANCE
DS1044–5 5 ±1.5 ns ±1.0 ns DS1044–6 6 ±1.5 ns ±1.0 ns DS1044–7 7 ±1.5 ns ±1.0 ns
DS1044–8 8 ±1.5 ns ±1.0 ns DS1044–10 10 ±1.5 ns ±1.0 ns DS1044–12 12 ±1.5 ns ±1.0 ns DS1044–14 14 ±1.5 ns ±1.5 ns DS1044–18 18 ±1.5 ns ±1.5 ns DS1044–20 20 ±1.5 ns ±1.5 ns DS1044–25 25 ±2.0 ns ±1.5 ns
NOTES:
1. Nominal conditions are +25°C and VCC=+5.0 volts.
2. T emperature range of 0°C to 70° C and voltage range of 4.75 volts to 5.25 volts.
3. Delay accuracy are for both leading and trailing edges.
TOLERANCE OVER
(temp and voltage)
021798 2/6
Page 3
DS1044
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1044. The input waveform is produced by a precision pulse gener­ator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected
DS1044 TEST CIRCUIT Figure 2
PULSE
GENERATOR
4 INPUTS
UNIT UNDER
TEST
to the output. The DS1044 output taps are selected and connected to the interval counter by a VHF switch con­trol unit. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus.
START
VHF
SWITCH
CONTROL
UNIT
50
OUT
TIME INTERVAL
COUNTER
STOP
50
OUTPUTS 1–4
021798 3/6
Page 4
DS1044
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –1.0V to +7.0V Operating Temperature 0°C to 70°C Storage Temperature –55°C to +125°C Soldering Temperature 260°C for 10 seconds Short Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=+5V ± 5%)
PARAMETER SYMBOL
Supply Voltage V Active Current I
High Level Input Voltage V Low Level Input Voltage V Input Leakage I High Level Output Current I
Low Level Output Current I
CC
CC
IH IL L
OH
OL
TEST
CONDITION
VCC=5.25V Period=1µs
0V<VI<V
CC
VCC=4.75V
=4V
V
OH
VCC=4.75V
=0.5V
V
OL
MIN TYP MAX UNITS
4.75 5.00 5.25 V 45 mA
2.2 VCC+0.5 V –0.5 0.8 V –1.0 1.0 µA
–1.0 mA
12 mA
AC ELECTRICAL CHARACTERISTICS (+25°C; VCC=5V ± 5%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Period t
PERIOD
Input Pulse Width t
Input–to–Tap Output Delay t
PLH,
Output Rise or Fall Time tOR, t Power–up Time t
PU
WI
2 (tWI) ns 3
100% of
Tap Delay
t
PHL
OF
Table 1 ns
2.0 2.5 ns 100 ms
ns 3
CAPACITANCE (tA=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
021798 4/6
IN
10 pF
Page 5
DS1044
TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C Supply Voltage (VCC): 5.0V ± 0.1V Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V Source Impedance: 50 Max. Rise and Fall Time: 3.0 ns Max. – Measured between 0.6V and 2.4V. Pulse Width: 500 ns Pulse Period: 1 µs Output Load Capacitance: 15 pF Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM
PERIOD
t
RISE
t
FALL
80%
20%
IN
OUT
1.5V
1.5V
t
WI
t
PHL
t
PLH
1.5V
1.5V
t
WI
1.5V
NOTES:
1. All voltages are referenced to ground.
2. @ V
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive
=5 volts and 25°C, delay accuracy on both the rising and falling edges within tolerances given in
CC
Table 1.
with respect to de–coupling, layout, etc.
021798 5/6
Page 6
DS1044
TERMINOLOGY
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following pulse.
t
(Pulse Width): The elapsed time on the pulse
WI
between the 1.5 volt point on the leading edge and the
1.5 volt point on the trailing edge or the 1.5 volt point on the trailing edge and the 1.5 volt point on the leading edge.
t
(Input Rise Time): The elapsed time between the
RISE
20% and the 80% point on the leading edge of the input pulse.
Input Fall Time): The elapsed time between the
t
(
FALL
80% and the 20% point on the trailing edge on the input pulse.
t
(Time Delay, Rising): The elapsed time between
PLH
the 1.5 volt point on the leading edge of the input pulse and the 1.5 volt point on the leading edge of the output pulse.
t
(Time Delay, Falling): The elapsed time between
PHL
the 1.5 volt point on the falling edge of the input pulse and the 1.5 volt point on the falling edge of the output pulse.
021798 6/6
Loading...